1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "mt7915.h" 7 #include "../dma.h" 8 #include "mac.h" 9 10 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 11 12 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 13 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 14 IEEE80211_RADIOTAP_HE_##f) 15 16 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 18 .radar_pattern = { 19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 27 }, 28 }; 29 30 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 32 .radar_pattern = { 33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 38 }, 39 }; 40 41 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 43 .radar_pattern = { 44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 52 }, 53 }; 54 55 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 56 u16 idx, bool unicast) 57 { 58 struct mt7915_sta *sta; 59 struct mt76_wcid *wcid; 60 61 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 62 return NULL; 63 64 wcid = rcu_dereference(dev->mt76.wcid[idx]); 65 if (unicast || !wcid) 66 return wcid; 67 68 if (!wcid->sta) 69 return NULL; 70 71 sta = container_of(wcid, struct mt7915_sta, wcid); 72 if (!sta->vif) 73 return NULL; 74 75 return &sta->vif->sta.wcid; 76 } 77 78 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 79 { 80 } 81 82 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 83 { 84 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 85 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 86 87 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 88 0, 5000); 89 } 90 91 static u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid) 92 { 93 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 94 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 95 96 return MT_WTBL_LMAC_OFFS(wcid, 0); 97 } 98 99 /* TODO: use txfree airtime info to avoid runtime accessing in the long run */ 100 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 101 { 102 static const u8 ac_to_tid[] = { 103 [IEEE80211_AC_BE] = 0, 104 [IEEE80211_AC_BK] = 1, 105 [IEEE80211_AC_VI] = 4, 106 [IEEE80211_AC_VO] = 6 107 }; 108 struct ieee80211_sta *sta; 109 struct mt7915_sta *msta; 110 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 111 LIST_HEAD(sta_poll_list); 112 int i; 113 114 spin_lock_bh(&dev->sta_poll_lock); 115 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 116 spin_unlock_bh(&dev->sta_poll_lock); 117 118 rcu_read_lock(); 119 120 while (true) { 121 bool clear = false; 122 u32 addr; 123 u16 idx; 124 125 spin_lock_bh(&dev->sta_poll_lock); 126 if (list_empty(&sta_poll_list)) { 127 spin_unlock_bh(&dev->sta_poll_lock); 128 break; 129 } 130 msta = list_first_entry(&sta_poll_list, 131 struct mt7915_sta, poll_list); 132 list_del_init(&msta->poll_list); 133 spin_unlock_bh(&dev->sta_poll_lock); 134 135 idx = msta->wcid.idx; 136 addr = mt7915_mac_wtbl_lmac_addr(dev, idx) + 20 * 4; 137 138 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 139 u32 tx_last = msta->airtime_ac[i]; 140 u32 rx_last = msta->airtime_ac[i + 4]; 141 142 msta->airtime_ac[i] = mt76_rr(dev, addr); 143 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 144 145 tx_time[i] = msta->airtime_ac[i] - tx_last; 146 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 147 148 if ((tx_last | rx_last) & BIT(30)) 149 clear = true; 150 151 addr += 8; 152 } 153 154 if (clear) { 155 mt7915_mac_wtbl_update(dev, idx, 156 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 157 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 158 } 159 160 if (!msta->wcid.sta) 161 continue; 162 163 sta = container_of((void *)msta, struct ieee80211_sta, 164 drv_priv); 165 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 166 u8 q = mt7915_lmac_mapping(dev, i); 167 u32 tx_cur = tx_time[q]; 168 u32 rx_cur = rx_time[q]; 169 u8 tid = ac_to_tid[i]; 170 171 if (!tx_cur && !rx_cur) 172 continue; 173 174 ieee80211_sta_register_airtime(sta, tid, tx_cur, 175 rx_cur); 176 } 177 } 178 179 rcu_read_unlock(); 180 } 181 182 static void 183 mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 184 struct ieee80211_radiotap_he *he, 185 __le32 *rxv) 186 { 187 u32 ru_h, ru_l; 188 u8 ru, offs = 0; 189 190 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0])); 191 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1])); 192 ru = (u8)(ru_l | ru_h << 4); 193 194 status->bw = RATE_INFO_BW_HE_RU; 195 196 switch (ru) { 197 case 0 ... 36: 198 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 199 offs = ru; 200 break; 201 case 37 ... 52: 202 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 203 offs = ru - 37; 204 break; 205 case 53 ... 60: 206 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 207 offs = ru - 53; 208 break; 209 case 61 ... 64: 210 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 211 offs = ru - 61; 212 break; 213 case 65 ... 66: 214 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 215 offs = ru - 65; 216 break; 217 case 67: 218 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 219 break; 220 case 68: 221 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 222 break; 223 } 224 225 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 226 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 227 le16_encode_bits(offs, 228 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 229 } 230 231 static void 232 mt7915_mac_decode_he_radiotap(struct sk_buff *skb, 233 struct mt76_rx_status *status, 234 __le32 *rxv, u32 phy) 235 { 236 /* TODO: struct ieee80211_radiotap_he_mu */ 237 static const struct ieee80211_radiotap_he known = { 238 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 239 HE_BITS(DATA1_DATA_DCM_KNOWN) | 240 HE_BITS(DATA1_STBC_KNOWN) | 241 HE_BITS(DATA1_CODING_KNOWN) | 242 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 243 HE_BITS(DATA1_DOPPLER_KNOWN) | 244 HE_BITS(DATA1_BSS_COLOR_KNOWN), 245 .data2 = HE_BITS(DATA2_GI_KNOWN) | 246 HE_BITS(DATA2_TXBF_KNOWN) | 247 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 248 HE_BITS(DATA2_TXOP_KNOWN), 249 }; 250 struct ieee80211_radiotap_he *he = NULL; 251 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 252 253 he = skb_push(skb, sizeof(known)); 254 memcpy(he, &known, sizeof(known)); 255 256 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 257 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 258 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 259 le16_encode_bits(ltf_size, 260 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 261 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 262 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 263 264 switch (phy) { 265 case MT_PHY_TYPE_HE_SU: 266 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 267 HE_BITS(DATA1_UL_DL_KNOWN) | 268 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) | 269 HE_BITS(DATA1_SPTL_REUSE_KNOWN); 270 271 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 272 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 273 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 274 break; 275 case MT_PHY_TYPE_HE_EXT_SU: 276 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 277 HE_BITS(DATA1_UL_DL_KNOWN); 278 279 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 280 break; 281 case MT_PHY_TYPE_HE_MU: 282 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 283 HE_BITS(DATA1_UL_DL_KNOWN) | 284 HE_BITS(DATA1_SPTL_REUSE_KNOWN); 285 286 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 287 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 288 289 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 290 break; 291 case MT_PHY_TYPE_HE_TB: 292 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 293 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 294 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 295 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 296 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 297 298 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | 299 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 300 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 301 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 302 303 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 304 break; 305 default: 306 break; 307 } 308 } 309 310 int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) 311 { 312 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 313 struct mt76_phy *mphy = &dev->mt76.phy; 314 struct mt7915_phy *phy = &dev->phy; 315 struct ieee80211_supported_band *sband; 316 struct ieee80211_hdr *hdr; 317 __le32 *rxd = (__le32 *)skb->data; 318 __le32 *rxv = NULL; 319 u32 mode = 0; 320 u32 rxd1 = le32_to_cpu(rxd[1]); 321 u32 rxd2 = le32_to_cpu(rxd[2]); 322 u32 rxd3 = le32_to_cpu(rxd[3]); 323 bool unicast, insert_ccmp_hdr = false; 324 u8 remove_pad; 325 int i, idx; 326 327 memset(status, 0, sizeof(*status)); 328 329 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) { 330 mphy = dev->mt76.phy2; 331 if (!mphy) 332 return -EINVAL; 333 334 phy = mphy->priv; 335 status->ext_phy = true; 336 } 337 338 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 339 return -EINVAL; 340 341 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 342 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 343 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 344 345 if (status->wcid) { 346 struct mt7915_sta *msta; 347 348 msta = container_of(status->wcid, struct mt7915_sta, wcid); 349 spin_lock_bh(&dev->sta_poll_lock); 350 if (list_empty(&msta->poll_list)) 351 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 352 spin_unlock_bh(&dev->sta_poll_lock); 353 } 354 355 status->freq = mphy->chandef.chan->center_freq; 356 status->band = mphy->chandef.chan->band; 357 if (status->band == NL80211_BAND_5GHZ) 358 sband = &mphy->sband_5g.sband; 359 else 360 sband = &mphy->sband_2g.sband; 361 362 if (!sband->channels) 363 return -EINVAL; 364 365 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 366 status->flag |= RX_FLAG_FAILED_FCS_CRC; 367 368 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 369 status->flag |= RX_FLAG_MMIC_ERROR; 370 371 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 372 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 373 status->flag |= RX_FLAG_DECRYPTED; 374 status->flag |= RX_FLAG_IV_STRIPPED; 375 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 376 } 377 378 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 379 status->flag |= RX_FLAG_AMPDU_DETAILS; 380 381 /* all subframes of an A-MPDU have the same timestamp */ 382 if (phy->rx_ampdu_ts != rxd[14]) { 383 if (!++phy->ampdu_ref) 384 phy->ampdu_ref++; 385 } 386 phy->rx_ampdu_ts = rxd[14]; 387 388 status->ampdu_ref = phy->ampdu_ref; 389 } 390 391 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 392 393 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 394 return -EINVAL; 395 396 rxd += 6; 397 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 398 rxd += 4; 399 if ((u8 *)rxd - skb->data >= skb->len) 400 return -EINVAL; 401 } 402 403 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 404 u8 *data = (u8 *)rxd; 405 406 if (status->flag & RX_FLAG_DECRYPTED) { 407 status->iv[0] = data[5]; 408 status->iv[1] = data[4]; 409 status->iv[2] = data[3]; 410 status->iv[3] = data[2]; 411 status->iv[4] = data[1]; 412 status->iv[5] = data[0]; 413 414 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 415 } 416 rxd += 4; 417 if ((u8 *)rxd - skb->data >= skb->len) 418 return -EINVAL; 419 } 420 421 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 422 rxd += 2; 423 if ((u8 *)rxd - skb->data >= skb->len) 424 return -EINVAL; 425 } 426 427 /* RXD Group 3 - P-RXV */ 428 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 429 u32 v0, v1, v2; 430 431 rxv = rxd; 432 rxd += 2; 433 if ((u8 *)rxd - skb->data >= skb->len) 434 return -EINVAL; 435 436 v0 = le32_to_cpu(rxv[0]); 437 v1 = le32_to_cpu(rxv[1]); 438 v2 = le32_to_cpu(rxv[2]); 439 440 if (v0 & MT_PRXV_HT_AD_CODE) 441 status->enc_flags |= RX_ENC_FLAG_LDPC; 442 443 status->chains = mphy->antenna_mask; 444 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 445 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 446 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 447 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 448 status->signal = status->chain_signal[0]; 449 450 for (i = 1; i < hweight8(mphy->antenna_mask); i++) { 451 if (!(status->chains & BIT(i))) 452 continue; 453 454 status->signal = max(status->signal, 455 status->chain_signal[i]); 456 } 457 458 /* RXD Group 5 - C-RXV */ 459 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 460 u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2); 461 u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2); 462 bool cck = false; 463 464 rxd += 18; 465 if ((u8 *)rxd - skb->data >= skb->len) 466 return -EINVAL; 467 468 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); 469 mode = FIELD_GET(MT_CRXV_TX_MODE, v2); 470 471 switch (mode) { 472 case MT_PHY_TYPE_CCK: 473 cck = true; 474 fallthrough; 475 case MT_PHY_TYPE_OFDM: 476 i = mt76_get_rate(&dev->mt76, sband, i, cck); 477 break; 478 case MT_PHY_TYPE_HT_GF: 479 case MT_PHY_TYPE_HT: 480 status->encoding = RX_ENC_HT; 481 if (i > 31) 482 return -EINVAL; 483 break; 484 case MT_PHY_TYPE_VHT: 485 status->nss = 486 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 487 status->encoding = RX_ENC_VHT; 488 if (i > 9) 489 return -EINVAL; 490 break; 491 case MT_PHY_TYPE_HE_MU: 492 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 493 fallthrough; 494 case MT_PHY_TYPE_HE_SU: 495 case MT_PHY_TYPE_HE_EXT_SU: 496 case MT_PHY_TYPE_HE_TB: 497 status->nss = 498 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 499 status->encoding = RX_ENC_HE; 500 status->flag |= RX_FLAG_RADIOTAP_HE; 501 i &= GENMASK(3, 0); 502 503 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 504 status->he_gi = gi; 505 506 status->he_dcm = !!(idx & MT_PRXV_TX_DCM); 507 break; 508 default: 509 return -EINVAL; 510 } 511 status->rate_idx = i; 512 513 switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) { 514 case IEEE80211_STA_RX_BW_20: 515 break; 516 case IEEE80211_STA_RX_BW_40: 517 if (mode & MT_PHY_TYPE_HE_EXT_SU && 518 (idx & MT_PRXV_TX_ER_SU_106T)) { 519 status->bw = RATE_INFO_BW_HE_RU; 520 status->he_ru = 521 NL80211_RATE_INFO_HE_RU_ALLOC_106; 522 } else { 523 status->bw = RATE_INFO_BW_40; 524 } 525 break; 526 case IEEE80211_STA_RX_BW_80: 527 status->bw = RATE_INFO_BW_80; 528 break; 529 case IEEE80211_STA_RX_BW_160: 530 status->bw = RATE_INFO_BW_160; 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 537 if (mode < MT_PHY_TYPE_HE_SU && gi) 538 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 539 } 540 } 541 542 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 543 544 if (insert_ccmp_hdr) { 545 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 546 547 mt76_insert_ccmp_hdr(skb, key_id); 548 } 549 550 if (rxv && status->flag & RX_FLAG_RADIOTAP_HE) 551 mt7915_mac_decode_he_radiotap(skb, status, rxv, mode); 552 553 hdr = mt76_skb_get_hdr(skb); 554 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control)) 555 return 0; 556 557 status->aggr = unicast && 558 !ieee80211_is_qos_nullfunc(hdr->frame_control); 559 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; 560 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 561 562 return 0; 563 } 564 565 #ifdef CONFIG_NL80211_TESTMODE 566 void mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 567 { 568 struct mt7915_phy *phy = &dev->phy; 569 __le32 *rxd = (__le32 *)skb->data; 570 __le32 *rxv_hdr = rxd + 2; 571 __le32 *rxv = rxd + 4; 572 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 573 bool ext_phy; 574 s32 foe; 575 u8 snr; 576 int i; 577 578 ext_phy = FIELD_GET(MT_RXV_HDR_BAND_IDX, le32_to_cpu(rxv_hdr[1])); 579 if (ext_phy) 580 phy = mt7915_ext_phy(dev); 581 582 rcpi = le32_to_cpu(rxv[6]); 583 ib_rssi = le32_to_cpu(rxv[7]); 584 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 585 586 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 587 if (i == 3) 588 wb_rssi = le32_to_cpu(rxv[9]); 589 590 phy->test.last_rcpi[i] = rcpi & 0xff; 591 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 592 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 593 } 594 595 v20 = le32_to_cpu(rxv[20]); 596 v21 = le32_to_cpu(rxv[21]); 597 598 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 599 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 600 601 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 602 603 phy->test.last_freq_offset = foe; 604 phy->test.last_snr = snr; 605 606 dev_kfree_skb(skb); 607 } 608 #endif 609 610 static void 611 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 612 struct sk_buff *skb) 613 { 614 #ifdef CONFIG_NL80211_TESTMODE 615 struct mt76_testmode_data *td = &phy->mt76->test; 616 u8 rate_idx = td->tx_rate_idx; 617 u8 nss = td->tx_rate_nss; 618 u8 bw, mode; 619 u16 rateval = 0; 620 u32 val; 621 622 if (skb != phy->mt76->test.tx_skb) 623 return; 624 625 switch (td->tx_rate_mode) { 626 case MT76_TM_TX_MODE_CCK: 627 mode = MT_PHY_TYPE_CCK; 628 break; 629 case MT76_TM_TX_MODE_HT: 630 nss = 1 + (rate_idx >> 3); 631 mode = MT_PHY_TYPE_HT; 632 break; 633 case MT76_TM_TX_MODE_VHT: 634 mode = MT_PHY_TYPE_VHT; 635 break; 636 case MT76_TM_TX_MODE_HE_SU: 637 mode = MT_PHY_TYPE_HE_SU; 638 break; 639 case MT76_TM_TX_MODE_HE_EXT_SU: 640 mode = MT_PHY_TYPE_HE_EXT_SU; 641 break; 642 case MT76_TM_TX_MODE_HE_TB: 643 mode = MT_PHY_TYPE_HE_TB; 644 break; 645 case MT76_TM_TX_MODE_HE_MU: 646 mode = MT_PHY_TYPE_HE_MU; 647 break; 648 case MT76_TM_TX_MODE_OFDM: 649 default: 650 mode = MT_PHY_TYPE_OFDM; 651 break; 652 } 653 654 switch (phy->mt76->chandef.width) { 655 case NL80211_CHAN_WIDTH_40: 656 bw = 1; 657 break; 658 case NL80211_CHAN_WIDTH_80: 659 bw = 2; 660 break; 661 case NL80211_CHAN_WIDTH_80P80: 662 case NL80211_CHAN_WIDTH_160: 663 bw = 3; 664 break; 665 default: 666 bw = 0; 667 break; 668 } 669 670 if (td->tx_rate_stbc && nss == 1) { 671 nss++; 672 rateval |= MT_TX_RATE_STBC; 673 } 674 675 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 676 FIELD_PREP(MT_TX_RATE_MODE, mode) | 677 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 678 679 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 680 681 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 682 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 683 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 684 685 val = MT_TXD6_FIXED_BW | 686 FIELD_PREP(MT_TXD6_BW, bw) | 687 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 688 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 689 690 /* for HE_SU/HE_EXT_SU PPDU 691 * - 1x, 2x, 4x LTF + 0.8us GI 692 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 693 * for HE_MU PPDU 694 * - 2x, 4x LTF + 0.8us GI 695 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 696 * for HE_TB PPDU 697 * - 1x, 2x LTF + 1.6us GI 698 * - 4x LTF + 3.2us GI 699 */ 700 if (mode >= MT_PHY_TYPE_HE_SU) 701 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 702 703 if (td->tx_rate_ldpc || bw > 0) 704 val |= MT_TXD6_LDPC; 705 706 txwi[6] |= cpu_to_le32(val); 707 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 708 phy->test.spe_idx)); 709 #endif 710 } 711 712 static void 713 mt7915_mac_write_txwi_8023(struct mt7915_dev *dev, __le32 *txwi, 714 struct sk_buff *skb, struct mt76_wcid *wcid) 715 { 716 717 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 718 u8 fc_type, fc_stype; 719 bool wmm = false; 720 u32 val; 721 722 if (wcid->sta) { 723 struct ieee80211_sta *sta; 724 725 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 726 wmm = sta->wme; 727 } 728 729 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 730 FIELD_PREP(MT_TXD1_TID, tid); 731 732 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN) 733 val |= MT_TXD1_ETH_802_3; 734 735 txwi[1] |= cpu_to_le32(val); 736 737 fc_type = IEEE80211_FTYPE_DATA >> 2; 738 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 739 740 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 741 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 742 743 txwi[2] |= cpu_to_le32(val); 744 745 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 746 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 747 txwi[7] |= cpu_to_le32(val); 748 } 749 750 static void 751 mt7915_mac_write_txwi_80211(struct mt7915_dev *dev, __le32 *txwi, 752 struct sk_buff *skb, struct ieee80211_key_conf *key) 753 { 754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 755 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 756 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 757 bool multicast = is_multicast_ether_addr(hdr->addr1); 758 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 759 __le16 fc = hdr->frame_control; 760 u8 fc_type, fc_stype; 761 u32 val; 762 763 if (ieee80211_is_action(fc) && 764 mgmt->u.action.category == WLAN_CATEGORY_BACK && 765 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 766 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 767 768 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA); 769 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK; 770 } else if (ieee80211_is_back_req(hdr->frame_control)) { 771 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr; 772 u16 control = le16_to_cpu(bar->control); 773 774 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control); 775 } 776 777 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 778 FIELD_PREP(MT_TXD1_HDR_INFO, 779 ieee80211_get_hdrlen_from_skb(skb) / 2) | 780 FIELD_PREP(MT_TXD1_TID, tid); 781 txwi[1] |= cpu_to_le32(val); 782 783 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 784 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 785 786 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 787 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 788 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 789 790 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) && 791 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 792 val |= MT_TXD2_BIP; 793 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 794 } 795 796 if (!ieee80211_is_data(fc) || multicast) 797 val |= MT_TXD2_FIX_RATE; 798 799 txwi[2] |= cpu_to_le32(val); 800 801 if (ieee80211_is_beacon(fc)) { 802 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 803 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 804 } 805 806 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 807 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 808 809 if (ieee80211_is_back_req(hdr->frame_control)) { 810 struct ieee80211_bar *bar; 811 812 bar = (struct ieee80211_bar *)skb->data; 813 seqno = le16_to_cpu(bar->start_seq_num); 814 } 815 816 val = MT_TXD3_SN_VALID | 817 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 818 txwi[3] |= cpu_to_le32(val); 819 } 820 821 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 822 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 823 txwi[7] |= cpu_to_le32(val); 824 } 825 826 void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, 827 struct sk_buff *skb, struct mt76_wcid *wcid, 828 struct ieee80211_key_conf *key, bool beacon) 829 { 830 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 831 struct ieee80211_vif *vif = info->control.vif; 832 struct mt76_phy *mphy = &dev->mphy; 833 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY; 834 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 835 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 836 u16 tx_count = 15; 837 u32 val; 838 839 if (vif) { 840 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 841 842 omac_idx = mvif->omac_idx; 843 wmm_idx = mvif->wmm_idx; 844 } 845 846 if (ext_phy && dev->mt76.phy2) 847 mphy = dev->mt76.phy2; 848 849 if (beacon) { 850 p_fmt = MT_TX_TYPE_FW; 851 q_idx = MT_LMAC_BCN0; 852 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 853 p_fmt = MT_TX_TYPE_CT; 854 q_idx = MT_LMAC_ALTX0; 855 } else { 856 p_fmt = MT_TX_TYPE_CT; 857 q_idx = wmm_idx * MT7915_MAX_WMM_SETS + 858 mt7915_lmac_mapping(dev, skb_get_queue_mapping(skb)); 859 } 860 861 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 862 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 863 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 864 txwi[0] = cpu_to_le32(val); 865 866 val = MT_TXD1_LONG_FORMAT | 867 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 868 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 869 870 if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) 871 val |= MT_TXD1_TGID; 872 873 txwi[1] = cpu_to_le32(val); 874 875 txwi[2] = 0; 876 877 val = MT_TXD3_SW_POWER_MGMT | 878 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 879 if (key) 880 val |= MT_TXD3_PROTECT_FRAME; 881 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 882 val |= MT_TXD3_NO_ACK; 883 884 txwi[3] = cpu_to_le32(val); 885 txwi[4] = 0; 886 txwi[5] = 0; 887 txwi[6] = 0; 888 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0; 889 890 if (is_8023) 891 mt7915_mac_write_txwi_8023(dev, txwi, skb, wcid); 892 else 893 mt7915_mac_write_txwi_80211(dev, txwi, skb, key); 894 895 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) { 896 u16 rate; 897 898 /* hardware won't add HTC for mgmt/ctrl frame */ 899 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); 900 901 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 902 rate = MT7915_5G_RATE_DEFAULT; 903 else 904 rate = MT7915_2G_RATE_DEFAULT; 905 906 val = MT_TXD6_FIXED_BW | 907 FIELD_PREP(MT_TXD6_TX_RATE, rate); 908 txwi[6] |= cpu_to_le32(val); 909 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 910 } 911 912 if (mt76_testmode_enabled(mphy)) 913 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 914 } 915 916 static void 917 mt7915_set_tx_blocked(struct mt7915_dev *dev, bool blocked) 918 { 919 struct mt76_phy *mphy = &dev->mphy, *mphy2 = dev->mt76.phy2; 920 struct mt76_queue *q, *q2 = NULL; 921 922 q = mphy->q_tx[0]; 923 if (blocked == q->blocked) 924 return; 925 926 q->blocked = blocked; 927 if (mphy2) { 928 q2 = mphy2->q_tx[0]; 929 q2->blocked = blocked; 930 } 931 932 if (!blocked) 933 mt76_worker_schedule(&dev->mt76.tx_worker); 934 } 935 936 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 937 enum mt76_txq_id qid, struct mt76_wcid *wcid, 938 struct ieee80211_sta *sta, 939 struct mt76_tx_info *tx_info) 940 { 941 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 942 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 943 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 944 struct ieee80211_key_conf *key = info->control.hw_key; 945 struct ieee80211_vif *vif = info->control.vif; 946 struct mt76_tx_cb *cb = mt76_tx_skb_cb(tx_info->skb); 947 struct mt76_txwi_cache *t; 948 struct mt7915_txp *txp; 949 int id, i, nbuf = tx_info->nbuf - 1; 950 u8 *txwi = (u8 *)txwi_ptr; 951 952 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 953 return -EINVAL; 954 955 if (!wcid) 956 wcid = &dev->mt76.global_wcid; 957 958 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key, 959 false); 960 961 cb->wcid = wcid->idx; 962 963 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE); 964 for (i = 0; i < nbuf; i++) { 965 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 966 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 967 } 968 txp->nbuf = nbuf; 969 970 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 971 972 if (!key) 973 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 974 975 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 976 ieee80211_is_mgmt(hdr->frame_control)) 977 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 978 979 if (vif) { 980 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 981 982 txp->bss_idx = mvif->idx; 983 } 984 985 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 986 t->skb = tx_info->skb; 987 988 spin_lock_bh(&dev->token_lock); 989 id = idr_alloc(&dev->token, t, 0, MT7915_TOKEN_SIZE, GFP_ATOMIC); 990 if (id >= 0) 991 dev->token_count++; 992 993 if (dev->token_count >= MT7915_TOKEN_SIZE - MT7915_TOKEN_FREE_THR) 994 mt7915_set_tx_blocked(dev, true); 995 spin_unlock_bh(&dev->token_lock); 996 997 if (id < 0) 998 return id; 999 1000 txp->token = cpu_to_le16(id); 1001 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 1002 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 1003 else 1004 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 1005 tx_info->skb = DMA_DUMMY_DATA; 1006 1007 /* pass partial skb header to fw */ 1008 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1009 tx_info->buf[1].skip_unmap = true; 1010 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1011 1012 return 0; 1013 } 1014 1015 static void 1016 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1017 { 1018 struct mt7915_sta *msta; 1019 u16 fc, tid; 1020 u32 val; 1021 1022 if (!sta || !sta->ht_cap.ht_supported) 1023 return; 1024 1025 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1])); 1026 if (tid >= 6) /* skip VO queue */ 1027 return; 1028 1029 val = le32_to_cpu(txwi[2]); 1030 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1031 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1032 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1033 return; 1034 1035 msta = (struct mt7915_sta *)sta->drv_priv; 1036 if (!test_and_set_bit(tid, &msta->ampdu_state)) 1037 ieee80211_start_tx_ba_session(sta, tid, 0); 1038 } 1039 1040 static void 1041 mt7915_tx_complete_status(struct mt76_dev *mdev, struct sk_buff *skb, 1042 struct ieee80211_sta *sta, u8 stat, 1043 struct list_head *free_list) 1044 { 1045 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1046 struct ieee80211_tx_status status = { 1047 .sta = sta, 1048 .info = info, 1049 .skb = skb, 1050 .free_list = free_list, 1051 }; 1052 struct ieee80211_hw *hw; 1053 1054 if (sta) { 1055 struct mt7915_sta *msta; 1056 1057 msta = (struct mt7915_sta *)sta->drv_priv; 1058 status.rate = &msta->stats.tx_rate; 1059 } 1060 1061 #ifdef CONFIG_NL80211_TESTMODE 1062 if (mt76_is_testmode_skb(mdev, skb, &hw)) { 1063 struct mt7915_phy *phy = mt7915_hw_phy(hw); 1064 struct ieee80211_vif *vif = phy->monitor_vif; 1065 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 1066 1067 mt76_tx_complete_skb(mdev, mvif->sta.wcid.idx, skb); 1068 return; 1069 } 1070 #endif 1071 1072 hw = mt76_tx_status_get_hw(mdev, skb); 1073 1074 if (info->flags & IEEE80211_TX_CTL_AMPDU) 1075 info->flags |= IEEE80211_TX_STAT_AMPDU; 1076 1077 if (stat) 1078 ieee80211_tx_info_clear_status(info); 1079 1080 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 1081 info->flags |= IEEE80211_TX_STAT_ACK; 1082 1083 info->status.tx_time = 0; 1084 ieee80211_tx_status_ext(hw, &status); 1085 } 1086 1087 void mt7915_txp_skb_unmap(struct mt76_dev *dev, 1088 struct mt76_txwi_cache *t) 1089 { 1090 struct mt7915_txp *txp; 1091 int i; 1092 1093 txp = mt7915_txwi_to_txp(dev, t); 1094 for (i = 1; i < txp->nbuf; i++) 1095 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), 1096 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); 1097 } 1098 1099 void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb) 1100 { 1101 struct mt7915_tx_free *free = (struct mt7915_tx_free *)skb->data; 1102 struct mt76_dev *mdev = &dev->mt76; 1103 struct mt76_phy *mphy_ext = mdev->phy2; 1104 struct mt76_txwi_cache *txwi; 1105 struct ieee80211_sta *sta = NULL; 1106 LIST_HEAD(free_list); 1107 struct sk_buff *tmp; 1108 u8 i, count; 1109 bool wake = false; 1110 1111 /* clean DMA queues and unmap buffers first */ 1112 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1113 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1114 if (mphy_ext) { 1115 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 1116 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 1117 } 1118 1119 /* 1120 * TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE, 1121 * to the time ack is received or dropped by hw (air + hw queue time). 1122 * Should avoid accessing WTBL to get Tx airtime, and use it instead. 1123 */ 1124 count = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl)); 1125 for (i = 0; i < count; i++) { 1126 u32 msdu, info = le32_to_cpu(free->info[i]); 1127 u8 stat; 1128 1129 /* 1130 * 1'b1: new wcid pair. 1131 * 1'b0: msdu_id with the same 'wcid pair' as above. 1132 */ 1133 if (info & MT_TX_FREE_PAIR) { 1134 struct mt7915_sta *msta; 1135 struct mt7915_phy *phy; 1136 struct mt76_wcid *wcid; 1137 u16 idx; 1138 1139 count++; 1140 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 1141 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1142 sta = wcid_to_sta(wcid); 1143 if (!sta) 1144 continue; 1145 1146 msta = container_of(wcid, struct mt7915_sta, wcid); 1147 phy = msta->vif->phy; 1148 spin_lock_bh(&dev->sta_poll_lock); 1149 if (list_empty(&msta->stats_list)) 1150 list_add_tail(&msta->stats_list, &phy->stats_list); 1151 if (list_empty(&msta->poll_list)) 1152 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1153 spin_unlock_bh(&dev->sta_poll_lock); 1154 continue; 1155 } 1156 1157 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 1158 stat = FIELD_GET(MT_TX_FREE_STATUS, info); 1159 1160 spin_lock_bh(&dev->token_lock); 1161 txwi = idr_remove(&dev->token, msdu); 1162 if (txwi) 1163 dev->token_count--; 1164 if (dev->token_count < MT7915_TOKEN_SIZE - MT7915_TOKEN_FREE_THR && 1165 dev->mphy.q_tx[0]->blocked) 1166 wake = true; 1167 spin_unlock_bh(&dev->token_lock); 1168 1169 if (!txwi) 1170 continue; 1171 1172 mt7915_txp_skb_unmap(mdev, txwi); 1173 if (txwi->skb) { 1174 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(txwi->skb); 1175 void *txwi_ptr = mt76_get_txwi_ptr(mdev, txwi); 1176 1177 if (likely(txwi->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1178 mt7915_tx_check_aggr(sta, txwi_ptr); 1179 1180 if (sta && !info->tx_time_est) { 1181 struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv; 1182 int pending; 1183 1184 pending = atomic_dec_return(&wcid->non_aql_packets); 1185 if (pending < 0) 1186 atomic_cmpxchg(&wcid->non_aql_packets, pending, 0); 1187 } 1188 1189 mt7915_tx_complete_status(mdev, txwi->skb, sta, stat, &free_list); 1190 txwi->skb = NULL; 1191 } 1192 1193 mt76_put_txwi(mdev, txwi); 1194 } 1195 1196 mt7915_mac_sta_poll(dev); 1197 1198 if (wake) { 1199 spin_lock_bh(&dev->token_lock); 1200 mt7915_set_tx_blocked(dev, false); 1201 spin_unlock_bh(&dev->token_lock); 1202 } 1203 1204 mt76_worker_schedule(&dev->mt76.tx_worker); 1205 1206 napi_consume_skb(skb, 1); 1207 1208 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1209 skb_list_del_init(skb); 1210 napi_consume_skb(skb, 1); 1211 } 1212 } 1213 1214 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 1215 { 1216 struct mt7915_dev *dev; 1217 1218 if (!e->txwi) { 1219 dev_kfree_skb_any(e->skb); 1220 return; 1221 } 1222 1223 dev = container_of(mdev, struct mt7915_dev, mt76); 1224 1225 /* error path */ 1226 if (e->skb == DMA_DUMMY_DATA) { 1227 struct mt76_txwi_cache *t; 1228 struct mt7915_txp *txp; 1229 1230 txp = mt7915_txwi_to_txp(mdev, e->txwi); 1231 1232 spin_lock_bh(&dev->token_lock); 1233 t = idr_remove(&dev->token, le16_to_cpu(txp->token)); 1234 spin_unlock_bh(&dev->token_lock); 1235 e->skb = t ? t->skb : NULL; 1236 } 1237 1238 if (e->skb) { 1239 struct mt76_tx_cb *cb = mt76_tx_skb_cb(e->skb); 1240 struct mt76_wcid *wcid; 1241 1242 wcid = rcu_dereference(dev->mt76.wcid[cb->wcid]); 1243 1244 mt7915_tx_complete_status(mdev, e->skb, wcid_to_sta(wcid), 0, 1245 NULL); 1246 } 1247 } 1248 1249 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1250 { 1251 struct mt7915_dev *dev = phy->dev; 1252 bool ext_phy = phy != &dev->phy; 1253 u32 reg = MT_WF_PHY_RX_CTRL1(ext_phy); 1254 1255 mt7915_l2_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1256 mt7915_l2_set(dev, reg, BIT(11) | BIT(9)); 1257 } 1258 1259 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1260 { 1261 struct mt7915_dev *dev = phy->dev; 1262 bool ext_phy = phy != &dev->phy; 1263 int i; 1264 1265 for (i = 0; i < 4; i++) { 1266 mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 1267 mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i)); 1268 } 1269 1270 if (ext_phy) { 1271 dev->mt76.phy2->survey_time = ktime_get_boottime(); 1272 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2; 1273 } else { 1274 dev->mt76.phy.survey_time = ktime_get_boottime(); 1275 i = 0; 1276 } 1277 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2); 1278 1279 /* reset airtime counters */ 1280 mt76_rr(dev, MT_MIB_SDR9(ext_phy)); 1281 mt76_rr(dev, MT_MIB_SDR36(ext_phy)); 1282 mt76_rr(dev, MT_MIB_SDR37(ext_phy)); 1283 1284 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(ext_phy), 1285 MT_WF_RMAC_MIB_RXTIME_CLR); 1286 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(ext_phy), 1287 MT_WF_RMAC_MIB_RXTIME_CLR); 1288 } 1289 1290 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1291 { 1292 s16 coverage_class = phy->coverage_class; 1293 struct mt7915_dev *dev = phy->dev; 1294 bool ext_phy = phy != &dev->phy; 1295 u32 val, reg_offset; 1296 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1297 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1298 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1299 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1300 int sifs, offset; 1301 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 1302 1303 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1304 return; 1305 1306 if (is_5ghz) 1307 sifs = 16; 1308 else 1309 sifs = 10; 1310 1311 if (ext_phy) { 1312 coverage_class = max_t(s16, dev->phy.coverage_class, 1313 coverage_class); 1314 } else { 1315 struct mt7915_phy *phy_ext = mt7915_ext_phy(dev); 1316 1317 if (phy_ext) 1318 coverage_class = max_t(s16, phy_ext->coverage_class, 1319 coverage_class); 1320 } 1321 mt76_set(dev, MT_ARB_SCR(ext_phy), 1322 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1323 udelay(1); 1324 1325 offset = 3 * coverage_class; 1326 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1327 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1328 1329 mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset); 1330 mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset); 1331 mt76_wr(dev, MT_TMAC_ICR0(ext_phy), 1332 FIELD_PREP(MT_IFS_EIFS, 360) | 1333 FIELD_PREP(MT_IFS_RIFS, 2) | 1334 FIELD_PREP(MT_IFS_SIFS, sifs) | 1335 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1336 1337 if (phy->slottime < 20 || is_5ghz) 1338 val = MT7915_CFEND_RATE_DEFAULT; 1339 else 1340 val = MT7915_CFEND_RATE_11B; 1341 1342 mt76_rmw_field(dev, MT_AGG_ACR0(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 1343 mt76_clear(dev, MT_ARB_SCR(ext_phy), 1344 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1345 } 1346 1347 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy) 1348 { 1349 mt7915_l2_set(dev, MT_WF_PHY_RXTD12(ext_phy), 1350 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1351 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1352 1353 mt7915_l2_set(dev, MT_WF_PHY_RX_CTRL1(ext_phy), 1354 FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1355 } 1356 1357 static u8 1358 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1359 { 1360 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1361 struct mt7915_dev *dev = phy->dev; 1362 u32 val, sum = 0, n = 0; 1363 int nss, i; 1364 1365 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1366 u32 reg = MT_WF_IRPI(nss + (idx << dev->dbdc_support)); 1367 1368 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1369 val = mt7915_l2_rr(dev, reg); 1370 sum += val * nf_power[i]; 1371 n += val; 1372 } 1373 } 1374 1375 if (!n) 1376 return 0; 1377 1378 return sum / n; 1379 } 1380 1381 static void 1382 mt7915_phy_update_channel(struct mt76_phy *mphy, int idx) 1383 { 1384 struct mt7915_dev *dev = container_of(mphy->dev, struct mt7915_dev, mt76); 1385 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv; 1386 struct mt76_channel_state *state; 1387 u64 busy_time, tx_time, rx_time, obss_time; 1388 int nf; 1389 1390 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1391 MT_MIB_SDR9_BUSY_MASK); 1392 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1393 MT_MIB_SDR36_TXTIME_MASK); 1394 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1395 MT_MIB_SDR37_RXTIME_MASK); 1396 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx), 1397 MT_MIB_OBSSTIME_MASK); 1398 1399 nf = mt7915_phy_get_nf(phy, idx); 1400 if (!phy->noise) 1401 phy->noise = nf << 4; 1402 else if (nf) 1403 phy->noise += nf - (phy->noise >> 4); 1404 1405 state = mphy->chan_state; 1406 state->cc_busy += busy_time; 1407 state->cc_tx += tx_time; 1408 state->cc_rx += rx_time + obss_time; 1409 state->cc_bss_rx += rx_time; 1410 state->noise = -(phy->noise >> 4); 1411 } 1412 1413 void mt7915_update_channel(struct mt76_dev *mdev) 1414 { 1415 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1416 1417 mt7915_phy_update_channel(&mdev->phy, 0); 1418 if (mdev->phy2) 1419 mt7915_phy_update_channel(mdev->phy2, 1); 1420 1421 /* reset obss airtime */ 1422 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR); 1423 if (mdev->phy2) 1424 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(1), 1425 MT_WF_RMAC_MIB_RXTIME_CLR); 1426 } 1427 1428 static bool 1429 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1430 { 1431 bool ret; 1432 1433 ret = wait_event_timeout(dev->reset_wait, 1434 (READ_ONCE(dev->reset_state) & state), 1435 MT7915_RESET_TIMEOUT); 1436 1437 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1438 return ret; 1439 } 1440 1441 static void 1442 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1443 { 1444 struct ieee80211_hw *hw = priv; 1445 1446 switch (vif->type) { 1447 case NL80211_IFTYPE_MESH_POINT: 1448 case NL80211_IFTYPE_ADHOC: 1449 case NL80211_IFTYPE_AP: 1450 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); 1451 break; 1452 default: 1453 break; 1454 } 1455 } 1456 1457 static void 1458 mt7915_update_beacons(struct mt7915_dev *dev) 1459 { 1460 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1461 IEEE80211_IFACE_ITER_RESUME_ALL, 1462 mt7915_update_vif_beacon, dev->mt76.hw); 1463 1464 if (!dev->mt76.phy2) 1465 return; 1466 1467 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw, 1468 IEEE80211_IFACE_ITER_RESUME_ALL, 1469 mt7915_update_vif_beacon, dev->mt76.phy2->hw); 1470 } 1471 1472 static void 1473 mt7915_dma_reset(struct mt7915_phy *phy) 1474 { 1475 struct mt7915_dev *dev = phy->dev; 1476 struct mt76_phy *mphy_ext = dev->mt76.phy2; 1477 u32 hif1_ofs = MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE; 1478 int i; 1479 1480 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 1481 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1482 mt76_clear(dev, MT_WFDMA1_GLO_CFG, 1483 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 1484 if (dev->hif2) { 1485 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1486 (MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1487 MT_WFDMA0_GLO_CFG_RX_DMA_EN)); 1488 mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 1489 (MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1490 MT_WFDMA1_GLO_CFG_RX_DMA_EN)); 1491 } 1492 usleep_range(1000, 2000); 1493 1494 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], true); 1495 for (i = 0; i < __MT_TXQ_MAX; i++) { 1496 mt76_queue_tx_cleanup(dev, phy->mt76->q_tx[i], true); 1497 if (mphy_ext) 1498 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true); 1499 } 1500 1501 mt76_for_each_q_rx(&dev->mt76, i) { 1502 mt76_queue_rx_reset(dev, i); 1503 } 1504 1505 /* re-init prefetch settings after reset */ 1506 mt7915_dma_prefetch(dev); 1507 1508 mt76_set(dev, MT_WFDMA0_GLO_CFG, 1509 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1510 mt76_set(dev, MT_WFDMA1_GLO_CFG, 1511 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 1512 if (dev->hif2) { 1513 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1514 (MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1515 MT_WFDMA0_GLO_CFG_RX_DMA_EN)); 1516 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 1517 (MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1518 MT_WFDMA1_GLO_CFG_RX_DMA_EN)); 1519 } 1520 } 1521 1522 void mt7915_tx_token_put(struct mt7915_dev *dev) 1523 { 1524 struct mt76_txwi_cache *txwi; 1525 int id; 1526 1527 spin_lock_bh(&dev->token_lock); 1528 idr_for_each_entry(&dev->token, txwi, id) { 1529 mt7915_txp_skb_unmap(&dev->mt76, txwi); 1530 if (txwi->skb) { 1531 struct ieee80211_hw *hw; 1532 1533 hw = mt76_tx_status_get_hw(&dev->mt76, txwi->skb); 1534 ieee80211_free_txskb(hw, txwi->skb); 1535 } 1536 mt76_put_txwi(&dev->mt76, txwi); 1537 dev->token_count--; 1538 } 1539 spin_unlock_bh(&dev->token_lock); 1540 idr_destroy(&dev->token); 1541 } 1542 1543 /* system error recovery */ 1544 void mt7915_mac_reset_work(struct work_struct *work) 1545 { 1546 struct mt7915_phy *phy2; 1547 struct mt76_phy *ext_phy; 1548 struct mt7915_dev *dev; 1549 1550 dev = container_of(work, struct mt7915_dev, reset_work); 1551 ext_phy = dev->mt76.phy2; 1552 phy2 = ext_phy ? ext_phy->priv : NULL; 1553 1554 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA)) 1555 return; 1556 1557 ieee80211_stop_queues(mt76_hw(dev)); 1558 if (ext_phy) 1559 ieee80211_stop_queues(ext_phy->hw); 1560 1561 set_bit(MT76_RESET, &dev->mphy.state); 1562 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1563 wake_up(&dev->mt76.mcu.wait); 1564 cancel_delayed_work_sync(&dev->mphy.mac_work); 1565 if (phy2) 1566 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1567 1568 /* lock/unlock all queues to ensure that no tx is pending */ 1569 mt76_txq_schedule_all(&dev->mphy); 1570 if (ext_phy) 1571 mt76_txq_schedule_all(ext_phy); 1572 1573 mt76_worker_disable(&dev->mt76.tx_worker); 1574 napi_disable(&dev->mt76.napi[0]); 1575 napi_disable(&dev->mt76.napi[1]); 1576 napi_disable(&dev->mt76.napi[2]); 1577 napi_disable(&dev->mt76.tx_napi); 1578 1579 mutex_lock(&dev->mt76.mutex); 1580 1581 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1582 1583 mt7915_tx_token_put(dev); 1584 idr_init(&dev->token); 1585 1586 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1587 mt7915_dma_reset(&dev->phy); 1588 1589 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1590 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1591 } 1592 1593 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1594 clear_bit(MT76_RESET, &dev->mphy.state); 1595 1596 mt76_worker_enable(&dev->mt76.tx_worker); 1597 napi_enable(&dev->mt76.tx_napi); 1598 napi_schedule(&dev->mt76.tx_napi); 1599 1600 napi_enable(&dev->mt76.napi[0]); 1601 napi_schedule(&dev->mt76.napi[0]); 1602 1603 napi_enable(&dev->mt76.napi[1]); 1604 napi_schedule(&dev->mt76.napi[1]); 1605 1606 napi_enable(&dev->mt76.napi[2]); 1607 napi_schedule(&dev->mt76.napi[2]); 1608 1609 ieee80211_wake_queues(mt76_hw(dev)); 1610 if (ext_phy) 1611 ieee80211_wake_queues(ext_phy->hw); 1612 1613 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1614 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1615 1616 mutex_unlock(&dev->mt76.mutex); 1617 1618 mt7915_update_beacons(dev); 1619 1620 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1621 MT7915_WATCHDOG_TIME); 1622 if (phy2) 1623 ieee80211_queue_delayed_work(ext_phy->hw, 1624 &phy2->mt76->mac_work, 1625 MT7915_WATCHDOG_TIME); 1626 } 1627 1628 static void 1629 mt7915_mac_update_mib_stats(struct mt7915_phy *phy) 1630 { 1631 struct mt7915_dev *dev = phy->dev; 1632 struct mib_stats *mib = &phy->mib; 1633 bool ext_phy = phy != &dev->phy; 1634 int i, aggr0, aggr1; 1635 1636 memset(mib, 0, sizeof(*mib)); 1637 1638 mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 1639 MT_MIB_SDR3_FCS_ERR_MASK); 1640 1641 aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 1642 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { 1643 u32 val, val2; 1644 1645 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); 1646 1647 val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1648 if (val2 > mib->ack_fail_cnt) 1649 mib->ack_fail_cnt = val2; 1650 1651 val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1652 if (val2 > mib->ba_miss_cnt) 1653 mib->ba_miss_cnt = val2; 1654 1655 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); 1656 val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1657 if (val2 > mib->rts_retries_cnt) { 1658 mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1659 mib->rts_retries_cnt = val2; 1660 } 1661 1662 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 1663 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i)); 1664 1665 dev->mt76.aggr_stats[aggr0++] += val & 0xffff; 1666 dev->mt76.aggr_stats[aggr0++] += val >> 16; 1667 dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff; 1668 dev->mt76.aggr_stats[aggr1++] += val2 >> 16; 1669 } 1670 } 1671 1672 static void 1673 mt7915_mac_sta_stats_work(struct mt7915_phy *phy) 1674 { 1675 struct mt7915_dev *dev = phy->dev; 1676 struct mt7915_sta *msta; 1677 LIST_HEAD(list); 1678 1679 spin_lock_bh(&dev->sta_poll_lock); 1680 list_splice_init(&phy->stats_list, &list); 1681 1682 while (!list_empty(&list)) { 1683 msta = list_first_entry(&list, struct mt7915_sta, stats_list); 1684 list_del_init(&msta->stats_list); 1685 spin_unlock_bh(&dev->sta_poll_lock); 1686 1687 /* use MT_TX_FREE_RATE to report Tx rate for further devices */ 1688 mt7915_mcu_get_tx_rate(dev, RATE_CTRL_RU_INFO, msta->wcid.idx); 1689 1690 spin_lock_bh(&dev->sta_poll_lock); 1691 } 1692 1693 spin_unlock_bh(&dev->sta_poll_lock); 1694 } 1695 1696 void mt7915_mac_sta_rc_work(struct work_struct *work) 1697 { 1698 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 1699 struct ieee80211_sta *sta; 1700 struct ieee80211_vif *vif; 1701 struct mt7915_sta *msta; 1702 u32 changed; 1703 LIST_HEAD(list); 1704 1705 spin_lock_bh(&dev->sta_poll_lock); 1706 list_splice_init(&dev->sta_rc_list, &list); 1707 1708 while (!list_empty(&list)) { 1709 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 1710 list_del_init(&msta->rc_list); 1711 changed = msta->stats.changed; 1712 msta->stats.changed = 0; 1713 spin_unlock_bh(&dev->sta_poll_lock); 1714 1715 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 1716 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1717 1718 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 1719 IEEE80211_RC_NSS_CHANGED | 1720 IEEE80211_RC_BW_CHANGED)) 1721 mt7915_mcu_add_rate_ctrl(dev, vif, sta); 1722 1723 if (changed & IEEE80211_RC_SMPS_CHANGED) 1724 mt7915_mcu_add_smps(dev, vif, sta); 1725 1726 spin_lock_bh(&dev->sta_poll_lock); 1727 } 1728 1729 spin_unlock_bh(&dev->sta_poll_lock); 1730 } 1731 1732 void mt7915_mac_work(struct work_struct *work) 1733 { 1734 struct mt7915_phy *phy; 1735 struct mt76_phy *mphy; 1736 1737 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 1738 mac_work.work); 1739 phy = mphy->priv; 1740 1741 mutex_lock(&mphy->dev->mutex); 1742 1743 mt76_update_survey(mphy->dev); 1744 if (++mphy->mac_work_count == 5) { 1745 mphy->mac_work_count = 0; 1746 1747 mt7915_mac_update_mib_stats(phy); 1748 } 1749 1750 if (++phy->sta_work_count == 10) { 1751 phy->sta_work_count = 0; 1752 mt7915_mac_sta_stats_work(phy); 1753 } 1754 1755 mutex_unlock(&mphy->dev->mutex); 1756 1757 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 1758 MT7915_WATCHDOG_TIME); 1759 } 1760 1761 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 1762 { 1763 struct mt7915_dev *dev = phy->dev; 1764 1765 if (phy->rdd_state & BIT(0)) 1766 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0); 1767 if (phy->rdd_state & BIT(1)) 1768 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0); 1769 } 1770 1771 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 1772 { 1773 int err; 1774 1775 err = mt7915_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0); 1776 if (err < 0) 1777 return err; 1778 1779 return mt7915_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, MT_RX_SEL0, 1); 1780 } 1781 1782 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 1783 { 1784 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 1785 struct mt7915_dev *dev = phy->dev; 1786 bool ext_phy = phy != &dev->phy; 1787 int err; 1788 1789 /* start CAC */ 1790 err = mt7915_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0); 1791 if (err < 0) 1792 return err; 1793 1794 err = mt7915_dfs_start_rdd(dev, ext_phy); 1795 if (err < 0) 1796 return err; 1797 1798 phy->rdd_state |= BIT(ext_phy); 1799 1800 if (chandef->width == NL80211_CHAN_WIDTH_160 || 1801 chandef->width == NL80211_CHAN_WIDTH_80P80) { 1802 err = mt7915_dfs_start_rdd(dev, 1); 1803 if (err < 0) 1804 return err; 1805 1806 phy->rdd_state |= BIT(1); 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int 1813 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 1814 { 1815 const struct mt7915_dfs_radar_spec *radar_specs; 1816 struct mt7915_dev *dev = phy->dev; 1817 int err, i; 1818 1819 switch (dev->mt76.region) { 1820 case NL80211_DFS_FCC: 1821 radar_specs = &fcc_radar_specs; 1822 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 1823 if (err < 0) 1824 return err; 1825 break; 1826 case NL80211_DFS_ETSI: 1827 radar_specs = &etsi_radar_specs; 1828 break; 1829 case NL80211_DFS_JP: 1830 radar_specs = &jp_radar_specs; 1831 break; 1832 default: 1833 return -EINVAL; 1834 } 1835 1836 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 1837 err = mt7915_mcu_set_radar_th(dev, i, 1838 &radar_specs->radar_pattern[i]); 1839 if (err < 0) 1840 return err; 1841 } 1842 1843 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 1844 } 1845 1846 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 1847 { 1848 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 1849 struct mt7915_dev *dev = phy->dev; 1850 bool ext_phy = phy != &dev->phy; 1851 int err; 1852 1853 if (dev->mt76.region == NL80211_DFS_UNSET) { 1854 phy->dfs_state = -1; 1855 if (phy->rdd_state) 1856 goto stop; 1857 1858 return 0; 1859 } 1860 1861 if (test_bit(MT76_SCANNING, &phy->mt76->state)) 1862 return 0; 1863 1864 if (phy->dfs_state == chandef->chan->dfs_state) 1865 return 0; 1866 1867 err = mt7915_dfs_init_radar_specs(phy); 1868 if (err < 0) { 1869 phy->dfs_state = -1; 1870 goto stop; 1871 } 1872 1873 phy->dfs_state = chandef->chan->dfs_state; 1874 1875 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) { 1876 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE) 1877 return mt7915_dfs_start_radar_detector(phy); 1878 1879 return mt7915_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy, 1880 MT_RX_SEL0, 0); 1881 } 1882 1883 stop: 1884 err = mt7915_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, 1885 MT_RX_SEL0, 0); 1886 if (err < 0) 1887 return err; 1888 1889 mt7915_dfs_stop_radar_detector(phy); 1890 return 0; 1891 } 1892