1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "coredump.h" 7 #include "mt7915.h" 8 #include "../dma.h" 9 #include "mac.h" 10 #include "mcu.h" 11 12 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 13 14 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 15 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 16 .radar_pattern = { 17 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 18 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 19 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 20 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 21 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 22 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 23 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 24 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 25 }, 26 }; 27 28 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 29 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 30 .radar_pattern = { 31 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 32 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 33 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 34 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 35 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 36 }, 37 }; 38 39 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 40 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 41 .radar_pattern = { 42 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 43 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 44 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 45 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 46 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 47 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 48 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 49 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 50 }, 51 }; 52 53 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 54 u16 idx, bool unicast) 55 { 56 struct mt7915_sta *sta; 57 struct mt76_wcid *wcid; 58 59 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 60 return NULL; 61 62 wcid = rcu_dereference(dev->mt76.wcid[idx]); 63 if (unicast || !wcid) 64 return wcid; 65 66 if (!wcid->sta) 67 return NULL; 68 69 sta = container_of(wcid, struct mt7915_sta, wcid); 70 if (!sta->vif) 71 return NULL; 72 73 return &sta->vif->sta.wcid; 74 } 75 76 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 77 { 78 } 79 80 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 81 { 82 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 83 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 84 85 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 86 0, 5000); 87 } 88 89 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 90 { 91 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 92 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 93 94 return MT_WTBL_LMAC_OFFS(wcid, dw); 95 } 96 97 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 98 { 99 static const u8 ac_to_tid[] = { 100 [IEEE80211_AC_BE] = 0, 101 [IEEE80211_AC_BK] = 1, 102 [IEEE80211_AC_VI] = 4, 103 [IEEE80211_AC_VO] = 6 104 }; 105 struct ieee80211_sta *sta; 106 struct mt7915_sta *msta; 107 struct rate_info *rate; 108 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 109 LIST_HEAD(sta_poll_list); 110 int i; 111 112 spin_lock_bh(&dev->sta_poll_lock); 113 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 114 spin_unlock_bh(&dev->sta_poll_lock); 115 116 rcu_read_lock(); 117 118 while (true) { 119 bool clear = false; 120 u32 addr, val; 121 u16 idx; 122 s8 rssi[4]; 123 u8 bw; 124 125 spin_lock_bh(&dev->sta_poll_lock); 126 if (list_empty(&sta_poll_list)) { 127 spin_unlock_bh(&dev->sta_poll_lock); 128 break; 129 } 130 msta = list_first_entry(&sta_poll_list, 131 struct mt7915_sta, poll_list); 132 list_del_init(&msta->poll_list); 133 spin_unlock_bh(&dev->sta_poll_lock); 134 135 idx = msta->wcid.idx; 136 137 /* refresh peer's airtime reporting */ 138 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 139 140 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 141 u32 tx_last = msta->airtime_ac[i]; 142 u32 rx_last = msta->airtime_ac[i + 4]; 143 144 msta->airtime_ac[i] = mt76_rr(dev, addr); 145 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 146 147 tx_time[i] = msta->airtime_ac[i] - tx_last; 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 queue = mt76_connac_lmac_mapping(i); 169 u32 tx_cur = tx_time[queue]; 170 u32 rx_cur = rx_time[queue]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 217 /* get signal strength of resp frames (CTS/BA/ACK) */ 218 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 219 val = mt76_rr(dev, addr); 220 221 rssi[0] = to_rssi(GENMASK(7, 0), val); 222 rssi[1] = to_rssi(GENMASK(15, 8), val); 223 rssi[2] = to_rssi(GENMASK(23, 16), val); 224 rssi[3] = to_rssi(GENMASK(31, 14), val); 225 226 msta->ack_signal = 227 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 228 229 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 230 } 231 232 rcu_read_unlock(); 233 } 234 235 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 236 struct ieee80211_vif *vif, bool enable) 237 { 238 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 239 u32 addr; 240 241 addr = mt7915_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 242 if (enable) 243 mt76_set(dev, addr, BIT(5)); 244 else 245 mt76_clear(dev, addr, BIT(5)); 246 } 247 248 static void 249 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 250 struct mt7915_sta *msta, struct sk_buff *skb, 251 u32 info) 252 { 253 struct ieee80211_vif *vif; 254 struct wireless_dev *wdev; 255 256 if (!msta || !msta->vif) 257 return; 258 259 if (!mt76_queue_is_wed_rx(q)) 260 return; 261 262 if (!(info & MT_DMA_INFO_PPE_VLD)) 263 return; 264 265 vif = container_of((void *)msta->vif, struct ieee80211_vif, 266 drv_priv); 267 wdev = ieee80211_vif_to_wdev(vif); 268 skb->dev = wdev->netdev; 269 270 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 271 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 272 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 273 } 274 275 static int 276 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 277 enum mt76_rxq_id q, u32 *info) 278 { 279 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 280 struct mt76_phy *mphy = &dev->mt76.phy; 281 struct mt7915_phy *phy = &dev->phy; 282 struct ieee80211_supported_band *sband; 283 __le32 *rxd = (__le32 *)skb->data; 284 __le32 *rxv = NULL; 285 u32 rxd0 = le32_to_cpu(rxd[0]); 286 u32 rxd1 = le32_to_cpu(rxd[1]); 287 u32 rxd2 = le32_to_cpu(rxd[2]); 288 u32 rxd3 = le32_to_cpu(rxd[3]); 289 u32 rxd4 = le32_to_cpu(rxd[4]); 290 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 291 bool unicast, insert_ccmp_hdr = false; 292 u8 remove_pad, amsdu_info; 293 u8 mode = 0, qos_ctl = 0; 294 struct mt7915_sta *msta = NULL; 295 u32 csum_status = *(u32 *)skb->cb; 296 bool hdr_trans; 297 u16 hdr_gap; 298 u16 seq_ctrl = 0; 299 __le16 fc = 0; 300 int idx; 301 302 memset(status, 0, sizeof(*status)); 303 304 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 305 mphy = dev->mt76.phys[MT_BAND1]; 306 if (!mphy) 307 return -EINVAL; 308 309 phy = mphy->priv; 310 status->phy_idx = 1; 311 } 312 313 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 314 return -EINVAL; 315 316 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 317 return -EINVAL; 318 319 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 320 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 321 return -EINVAL; 322 323 /* ICV error or CCMP/BIP/WPI MIC error */ 324 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 325 status->flag |= RX_FLAG_ONLY_MONITOR; 326 327 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 328 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 329 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 330 331 if (status->wcid) { 332 msta = container_of(status->wcid, struct mt7915_sta, wcid); 333 spin_lock_bh(&dev->sta_poll_lock); 334 if (list_empty(&msta->poll_list)) 335 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 336 spin_unlock_bh(&dev->sta_poll_lock); 337 } 338 339 status->freq = mphy->chandef.chan->center_freq; 340 status->band = mphy->chandef.chan->band; 341 if (status->band == NL80211_BAND_5GHZ) 342 sband = &mphy->sband_5g.sband; 343 else if (status->band == NL80211_BAND_6GHZ) 344 sband = &mphy->sband_6g.sband; 345 else 346 sband = &mphy->sband_2g.sband; 347 348 if (!sband->channels) 349 return -EINVAL; 350 351 if ((rxd0 & csum_mask) == csum_mask && 352 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 353 skb->ip_summed = CHECKSUM_UNNECESSARY; 354 355 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 356 status->flag |= RX_FLAG_FAILED_FCS_CRC; 357 358 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 359 status->flag |= RX_FLAG_MMIC_ERROR; 360 361 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 362 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 363 status->flag |= RX_FLAG_DECRYPTED; 364 status->flag |= RX_FLAG_IV_STRIPPED; 365 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 366 } 367 368 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 369 370 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 371 return -EINVAL; 372 373 rxd += 6; 374 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 375 u32 v0 = le32_to_cpu(rxd[0]); 376 u32 v2 = le32_to_cpu(rxd[2]); 377 378 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 379 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 380 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 381 382 rxd += 4; 383 if ((u8 *)rxd - skb->data >= skb->len) 384 return -EINVAL; 385 } 386 387 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 388 u8 *data = (u8 *)rxd; 389 390 if (status->flag & RX_FLAG_DECRYPTED) { 391 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 392 case MT_CIPHER_AES_CCMP: 393 case MT_CIPHER_CCMP_CCX: 394 case MT_CIPHER_CCMP_256: 395 insert_ccmp_hdr = 396 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 397 fallthrough; 398 case MT_CIPHER_TKIP: 399 case MT_CIPHER_TKIP_NO_MIC: 400 case MT_CIPHER_GCMP: 401 case MT_CIPHER_GCMP_256: 402 status->iv[0] = data[5]; 403 status->iv[1] = data[4]; 404 status->iv[2] = data[3]; 405 status->iv[3] = data[2]; 406 status->iv[4] = data[1]; 407 status->iv[5] = data[0]; 408 break; 409 default: 410 break; 411 } 412 } 413 rxd += 4; 414 if ((u8 *)rxd - skb->data >= skb->len) 415 return -EINVAL; 416 } 417 418 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 419 status->timestamp = le32_to_cpu(rxd[0]); 420 status->flag |= RX_FLAG_MACTIME_START; 421 422 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 423 status->flag |= RX_FLAG_AMPDU_DETAILS; 424 425 /* all subframes of an A-MPDU have the same timestamp */ 426 if (phy->rx_ampdu_ts != status->timestamp) { 427 if (!++phy->ampdu_ref) 428 phy->ampdu_ref++; 429 } 430 phy->rx_ampdu_ts = status->timestamp; 431 432 status->ampdu_ref = phy->ampdu_ref; 433 } 434 435 rxd += 2; 436 if ((u8 *)rxd - skb->data >= skb->len) 437 return -EINVAL; 438 } 439 440 /* RXD Group 3 - P-RXV */ 441 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 442 u32 v0, v1; 443 int ret; 444 445 rxv = rxd; 446 rxd += 2; 447 if ((u8 *)rxd - skb->data >= skb->len) 448 return -EINVAL; 449 450 v0 = le32_to_cpu(rxv[0]); 451 v1 = le32_to_cpu(rxv[1]); 452 453 if (v0 & MT_PRXV_HT_AD_CODE) 454 status->enc_flags |= RX_ENC_FLAG_LDPC; 455 456 status->chains = mphy->antenna_mask; 457 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 458 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 459 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 460 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 461 462 /* RXD Group 5 - C-RXV */ 463 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 464 rxd += 18; 465 if ((u8 *)rxd - skb->data >= skb->len) 466 return -EINVAL; 467 } 468 469 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 470 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 471 sband, rxv, &mode); 472 if (ret < 0) 473 return ret; 474 } 475 } 476 477 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 478 status->amsdu = !!amsdu_info; 479 if (status->amsdu) { 480 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 481 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 482 } 483 484 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 485 if (hdr_trans && ieee80211_has_morefrags(fc)) { 486 struct ieee80211_vif *vif; 487 int err; 488 489 if (!msta || !msta->vif) 490 return -EINVAL; 491 492 vif = container_of((void *)msta->vif, struct ieee80211_vif, 493 drv_priv); 494 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 495 if (err) 496 return err; 497 498 hdr_trans = false; 499 } else { 500 int pad_start = 0; 501 502 skb_pull(skb, hdr_gap); 503 if (!hdr_trans && status->amsdu) { 504 pad_start = ieee80211_get_hdrlen_from_skb(skb); 505 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 506 /* 507 * When header translation failure is indicated, 508 * the hardware will insert an extra 2-byte field 509 * containing the data length after the protocol 510 * type field. This happens either when the LLC-SNAP 511 * pattern did not match, or if a VLAN header was 512 * detected. 513 */ 514 pad_start = 12; 515 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 516 pad_start += 4; 517 else 518 pad_start = 0; 519 } 520 521 if (pad_start) { 522 memmove(skb->data + 2, skb->data, pad_start); 523 skb_pull(skb, 2); 524 } 525 } 526 527 if (!hdr_trans) { 528 struct ieee80211_hdr *hdr; 529 530 if (insert_ccmp_hdr) { 531 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 532 533 mt76_insert_ccmp_hdr(skb, key_id); 534 } 535 536 hdr = mt76_skb_get_hdr(skb); 537 fc = hdr->frame_control; 538 if (ieee80211_is_data_qos(fc)) { 539 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 540 qos_ctl = *ieee80211_get_qos_ctl(hdr); 541 } 542 } else { 543 status->flag |= RX_FLAG_8023; 544 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 545 *info); 546 } 547 548 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 549 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 550 551 if (!status->wcid || !ieee80211_is_data_qos(fc)) 552 return 0; 553 554 status->aggr = unicast && 555 !ieee80211_is_qos_nullfunc(fc); 556 status->qos_ctl = qos_ctl; 557 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 558 559 return 0; 560 } 561 562 static void 563 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 564 { 565 #ifdef CONFIG_NL80211_TESTMODE 566 struct mt7915_phy *phy = &dev->phy; 567 __le32 *rxd = (__le32 *)skb->data; 568 __le32 *rxv_hdr = rxd + 2; 569 __le32 *rxv = rxd + 4; 570 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 571 u8 band_idx; 572 s32 foe; 573 u8 snr; 574 int i; 575 576 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 577 if (band_idx && !phy->mt76->band_idx) { 578 phy = mt7915_ext_phy(dev); 579 if (!phy) 580 goto out; 581 } 582 583 rcpi = le32_to_cpu(rxv[6]); 584 ib_rssi = le32_to_cpu(rxv[7]); 585 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 586 587 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 588 if (i == 3) 589 wb_rssi = le32_to_cpu(rxv[9]); 590 591 phy->test.last_rcpi[i] = rcpi & 0xff; 592 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 593 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 594 } 595 596 v20 = le32_to_cpu(rxv[20]); 597 v21 = le32_to_cpu(rxv[21]); 598 599 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 600 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 601 602 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 603 604 phy->test.last_freq_offset = foe; 605 phy->test.last_snr = snr; 606 out: 607 #endif 608 dev_kfree_skb(skb); 609 } 610 611 static void 612 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 613 struct sk_buff *skb) 614 { 615 #ifdef CONFIG_NL80211_TESTMODE 616 struct mt76_testmode_data *td = &phy->mt76->test; 617 const struct ieee80211_rate *r; 618 u8 bw, mode, nss = td->tx_rate_nss; 619 u8 rate_idx = td->tx_rate_idx; 620 u16 rateval = 0; 621 u32 val; 622 bool cck = false; 623 int band; 624 625 if (skb != phy->mt76->test.tx_skb) 626 return; 627 628 switch (td->tx_rate_mode) { 629 case MT76_TM_TX_MODE_HT: 630 nss = 1 + (rate_idx >> 3); 631 mode = MT_PHY_TYPE_HT; 632 break; 633 case MT76_TM_TX_MODE_VHT: 634 mode = MT_PHY_TYPE_VHT; 635 break; 636 case MT76_TM_TX_MODE_HE_SU: 637 mode = MT_PHY_TYPE_HE_SU; 638 break; 639 case MT76_TM_TX_MODE_HE_EXT_SU: 640 mode = MT_PHY_TYPE_HE_EXT_SU; 641 break; 642 case MT76_TM_TX_MODE_HE_TB: 643 mode = MT_PHY_TYPE_HE_TB; 644 break; 645 case MT76_TM_TX_MODE_HE_MU: 646 mode = MT_PHY_TYPE_HE_MU; 647 break; 648 case MT76_TM_TX_MODE_CCK: 649 cck = true; 650 fallthrough; 651 case MT76_TM_TX_MODE_OFDM: 652 band = phy->mt76->chandef.chan->band; 653 if (band == NL80211_BAND_2GHZ && !cck) 654 rate_idx += 4; 655 656 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 657 val = cck ? r->hw_value_short : r->hw_value; 658 659 mode = val >> 8; 660 rate_idx = val & 0xff; 661 break; 662 default: 663 mode = MT_PHY_TYPE_OFDM; 664 break; 665 } 666 667 switch (phy->mt76->chandef.width) { 668 case NL80211_CHAN_WIDTH_40: 669 bw = 1; 670 break; 671 case NL80211_CHAN_WIDTH_80: 672 bw = 2; 673 break; 674 case NL80211_CHAN_WIDTH_80P80: 675 case NL80211_CHAN_WIDTH_160: 676 bw = 3; 677 break; 678 default: 679 bw = 0; 680 break; 681 } 682 683 if (td->tx_rate_stbc && nss == 1) { 684 nss++; 685 rateval |= MT_TX_RATE_STBC; 686 } 687 688 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 689 FIELD_PREP(MT_TX_RATE_MODE, mode) | 690 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 691 692 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 693 694 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 695 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 696 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 697 698 val = MT_TXD6_FIXED_BW | 699 FIELD_PREP(MT_TXD6_BW, bw) | 700 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 701 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 702 703 /* for HE_SU/HE_EXT_SU PPDU 704 * - 1x, 2x, 4x LTF + 0.8us GI 705 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 706 * for HE_MU PPDU 707 * - 2x, 4x LTF + 0.8us GI 708 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 709 * for HE_TB PPDU 710 * - 1x, 2x LTF + 1.6us GI 711 * - 4x LTF + 3.2us GI 712 */ 713 if (mode >= MT_PHY_TYPE_HE_SU) 714 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 715 716 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 717 val |= MT_TXD6_LDPC; 718 719 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 720 txwi[6] |= cpu_to_le32(val); 721 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 722 phy->test.spe_idx)); 723 #endif 724 } 725 726 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 727 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 728 struct ieee80211_key_conf *key, 729 enum mt76_txq_id qid, u32 changed) 730 { 731 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 732 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 733 struct mt76_phy *mphy = &dev->phy; 734 735 if (phy_idx && dev->phys[MT_BAND1]) 736 mphy = dev->phys[MT_BAND1]; 737 738 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 739 740 if (mt76_testmode_enabled(mphy)) 741 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 742 } 743 744 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 745 enum mt76_txq_id qid, struct mt76_wcid *wcid, 746 struct ieee80211_sta *sta, 747 struct mt76_tx_info *tx_info) 748 { 749 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 750 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 751 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 752 struct ieee80211_key_conf *key = info->control.hw_key; 753 struct ieee80211_vif *vif = info->control.vif; 754 struct mt76_connac_fw_txp *txp; 755 struct mt76_txwi_cache *t; 756 int id, i, nbuf = tx_info->nbuf - 1; 757 u8 *txwi = (u8 *)txwi_ptr; 758 int pid; 759 760 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 761 return -EINVAL; 762 763 if (!wcid) 764 wcid = &dev->mt76.global_wcid; 765 766 if (sta) { 767 struct mt7915_sta *msta; 768 769 msta = (struct mt7915_sta *)sta->drv_priv; 770 771 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 772 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 773 msta->jiffies = jiffies; 774 } 775 } 776 777 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 778 t->skb = tx_info->skb; 779 780 id = mt76_token_consume(mdev, &t); 781 if (id < 0) 782 return id; 783 784 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 785 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 786 qid, 0); 787 788 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 789 for (i = 0; i < nbuf; i++) { 790 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 791 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 792 } 793 txp->nbuf = nbuf; 794 795 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 796 797 if (!key) 798 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 799 800 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 801 ieee80211_is_mgmt(hdr->frame_control)) 802 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 803 804 if (vif) { 805 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 806 807 txp->bss_idx = mvif->mt76.idx; 808 } 809 810 txp->token = cpu_to_le16(id); 811 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 812 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 813 else 814 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 815 tx_info->skb = DMA_DUMMY_DATA; 816 817 /* pass partial skb header to fw */ 818 tx_info->buf[1].len = MT_CT_PARSE_LEN; 819 tx_info->buf[1].skip_unmap = true; 820 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 821 822 return 0; 823 } 824 825 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 826 { 827 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 828 __le32 *txwi = ptr; 829 u32 val; 830 831 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 832 833 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 834 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 835 txwi[0] = cpu_to_le32(val); 836 837 val = MT_TXD1_LONG_FORMAT | 838 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 839 txwi[1] = cpu_to_le32(val); 840 841 txp->token = cpu_to_le16(token_id); 842 txp->nbuf = 1; 843 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 844 845 return MT_TXD_SIZE + sizeof(*txp); 846 } 847 848 static void 849 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 850 { 851 struct mt7915_sta *msta; 852 u16 fc, tid; 853 u32 val; 854 855 if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he)) 856 return; 857 858 tid = le32_get_bits(txwi[1], MT_TXD1_TID); 859 if (tid >= 6) /* skip VO queue */ 860 return; 861 862 val = le32_to_cpu(txwi[2]); 863 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 864 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 865 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 866 return; 867 868 msta = (struct mt7915_sta *)sta->drv_priv; 869 if (!test_and_set_bit(tid, &msta->ampdu_state)) 870 ieee80211_start_tx_ba_session(sta, tid, 0); 871 } 872 873 static void 874 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t, 875 struct ieee80211_sta *sta, struct list_head *free_list) 876 { 877 struct mt76_dev *mdev = &dev->mt76; 878 struct mt7915_sta *msta; 879 struct mt76_wcid *wcid; 880 __le32 *txwi; 881 u16 wcid_idx; 882 883 mt76_connac_txp_skb_unmap(mdev, t); 884 if (!t->skb) 885 goto out; 886 887 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 888 if (sta) { 889 wcid = (struct mt76_wcid *)sta->drv_priv; 890 wcid_idx = wcid->idx; 891 } else { 892 wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); 893 wcid = rcu_dereference(dev->mt76.wcid[wcid_idx]); 894 895 if (wcid && wcid->sta) { 896 msta = container_of(wcid, struct mt7915_sta, wcid); 897 sta = container_of((void *)msta, struct ieee80211_sta, 898 drv_priv); 899 spin_lock_bh(&dev->sta_poll_lock); 900 if (list_empty(&msta->poll_list)) 901 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 902 spin_unlock_bh(&dev->sta_poll_lock); 903 } 904 } 905 906 if (sta && likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 907 mt7915_tx_check_aggr(sta, txwi); 908 909 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 910 911 out: 912 t->skb = NULL; 913 mt76_put_txwi(mdev, t); 914 } 915 916 static void 917 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 918 { 919 struct mt76_dev *mdev = &dev->mt76; 920 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 921 922 /* clean DMA queues and unmap buffers first */ 923 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 924 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 925 if (mphy_ext) { 926 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 927 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 928 } 929 } 930 931 static void 932 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 933 struct list_head *free_list, bool wake) 934 { 935 struct sk_buff *skb, *tmp; 936 937 mt7915_mac_sta_poll(dev); 938 939 if (wake) 940 mt76_set_tx_blocked(&dev->mt76, false); 941 942 mt76_worker_schedule(&dev->mt76.tx_worker); 943 944 list_for_each_entry_safe(skb, tmp, free_list, list) { 945 skb_list_del_init(skb); 946 napi_consume_skb(skb, 1); 947 } 948 } 949 950 static void 951 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 952 { 953 struct mt76_connac_tx_free *free = data; 954 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 955 struct mt76_dev *mdev = &dev->mt76; 956 struct mt76_txwi_cache *txwi; 957 struct ieee80211_sta *sta = NULL; 958 LIST_HEAD(free_list); 959 void *end = data + len; 960 bool v3, wake = false; 961 u16 total, count = 0; 962 u32 txd = le32_to_cpu(free->txd); 963 __le32 *cur_info; 964 965 mt7915_mac_tx_free_prepare(dev); 966 967 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 968 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 969 970 for (cur_info = tx_info; count < total; cur_info++) { 971 u32 msdu, info; 972 u8 i; 973 974 if (WARN_ON_ONCE((void *)cur_info >= end)) 975 return; 976 977 /* 978 * 1'b1: new wcid pair. 979 * 1'b0: msdu_id with the same 'wcid pair' as above. 980 */ 981 info = le32_to_cpu(*cur_info); 982 if (info & MT_TX_FREE_PAIR) { 983 struct mt7915_sta *msta; 984 struct mt76_wcid *wcid; 985 u16 idx; 986 987 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 988 wcid = rcu_dereference(dev->mt76.wcid[idx]); 989 sta = wcid_to_sta(wcid); 990 if (!sta) 991 continue; 992 993 msta = container_of(wcid, struct mt7915_sta, wcid); 994 spin_lock_bh(&dev->sta_poll_lock); 995 if (list_empty(&msta->poll_list)) 996 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 997 spin_unlock_bh(&dev->sta_poll_lock); 998 continue; 999 } 1000 1001 if (v3 && (info & MT_TX_FREE_MPDU_HEADER)) 1002 continue; 1003 1004 for (i = 0; i < 1 + v3; i++) { 1005 if (v3) { 1006 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 1007 if (msdu == MT_TX_FREE_MSDU_ID_V3) 1008 continue; 1009 } else { 1010 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 1011 } 1012 count++; 1013 txwi = mt76_token_release(mdev, msdu, &wake); 1014 if (!txwi) 1015 continue; 1016 1017 mt7915_txwi_free(dev, txwi, sta, &free_list); 1018 } 1019 } 1020 1021 mt7915_mac_tx_free_done(dev, &free_list, wake); 1022 } 1023 1024 static void 1025 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 1026 { 1027 struct mt76_connac_tx_free *free = data; 1028 __le16 *info = (__le16 *)(data + sizeof(*free)); 1029 struct mt76_dev *mdev = &dev->mt76; 1030 void *end = data + len; 1031 LIST_HEAD(free_list); 1032 bool wake = false; 1033 u8 i, count; 1034 1035 mt7915_mac_tx_free_prepare(dev); 1036 1037 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 1038 if (WARN_ON_ONCE((void *)&info[count] > end)) 1039 return; 1040 1041 for (i = 0; i < count; i++) { 1042 struct mt76_txwi_cache *txwi; 1043 u16 msdu = le16_to_cpu(info[i]); 1044 1045 txwi = mt76_token_release(mdev, msdu, &wake); 1046 if (!txwi) 1047 continue; 1048 1049 mt7915_txwi_free(dev, txwi, NULL, &free_list); 1050 } 1051 1052 mt7915_mac_tx_free_done(dev, &free_list, wake); 1053 } 1054 1055 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1056 { 1057 struct mt7915_sta *msta = NULL; 1058 struct mt76_wcid *wcid; 1059 __le32 *txs_data = data; 1060 u16 wcidx; 1061 u8 pid; 1062 1063 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1064 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1065 1066 if (pid < MT_PACKET_ID_WED) 1067 return; 1068 1069 if (wcidx >= mt7915_wtbl_size(dev)) 1070 return; 1071 1072 rcu_read_lock(); 1073 1074 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1075 if (!wcid) 1076 goto out; 1077 1078 msta = container_of(wcid, struct mt7915_sta, wcid); 1079 1080 if (pid == MT_PACKET_ID_WED) 1081 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1082 else 1083 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1084 1085 if (!wcid->sta) 1086 goto out; 1087 1088 spin_lock_bh(&dev->sta_poll_lock); 1089 if (list_empty(&msta->poll_list)) 1090 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1091 spin_unlock_bh(&dev->sta_poll_lock); 1092 1093 out: 1094 rcu_read_unlock(); 1095 } 1096 1097 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1098 { 1099 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1100 __le32 *rxd = (__le32 *)data; 1101 __le32 *end = (__le32 *)&rxd[len / 4]; 1102 enum rx_pkt_type type; 1103 1104 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1105 1106 switch (type) { 1107 case PKT_TYPE_TXRX_NOTIFY: 1108 mt7915_mac_tx_free(dev, data, len); 1109 return false; 1110 case PKT_TYPE_TXRX_NOTIFY_V0: 1111 mt7915_mac_tx_free_v0(dev, data, len); 1112 return false; 1113 case PKT_TYPE_TXS: 1114 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1115 mt7915_mac_add_txs(dev, rxd); 1116 return false; 1117 case PKT_TYPE_RX_FW_MONITOR: 1118 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1119 return false; 1120 default: 1121 return true; 1122 } 1123 } 1124 1125 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1126 struct sk_buff *skb, u32 *info) 1127 { 1128 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1129 __le32 *rxd = (__le32 *)skb->data; 1130 __le32 *end = (__le32 *)&skb->data[skb->len]; 1131 enum rx_pkt_type type; 1132 1133 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1134 1135 switch (type) { 1136 case PKT_TYPE_TXRX_NOTIFY: 1137 mt7915_mac_tx_free(dev, skb->data, skb->len); 1138 napi_consume_skb(skb, 1); 1139 break; 1140 case PKT_TYPE_TXRX_NOTIFY_V0: 1141 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1142 napi_consume_skb(skb, 1); 1143 break; 1144 case PKT_TYPE_RX_EVENT: 1145 mt7915_mcu_rx_event(dev, skb); 1146 break; 1147 case PKT_TYPE_TXRXV: 1148 mt7915_mac_fill_rx_vector(dev, skb); 1149 break; 1150 case PKT_TYPE_TXS: 1151 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1152 mt7915_mac_add_txs(dev, rxd); 1153 dev_kfree_skb(skb); 1154 break; 1155 case PKT_TYPE_RX_FW_MONITOR: 1156 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1157 dev_kfree_skb(skb); 1158 break; 1159 case PKT_TYPE_NORMAL: 1160 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1161 mt76_rx(&dev->mt76, q, skb); 1162 return; 1163 } 1164 fallthrough; 1165 default: 1166 dev_kfree_skb(skb); 1167 break; 1168 } 1169 } 1170 1171 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1172 { 1173 struct mt7915_dev *dev = phy->dev; 1174 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1175 1176 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1177 mt76_set(dev, reg, BIT(11) | BIT(9)); 1178 } 1179 1180 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1181 { 1182 struct mt7915_dev *dev = phy->dev; 1183 int i; 1184 1185 for (i = 0; i < 4; i++) { 1186 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1187 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1188 } 1189 1190 phy->mt76->survey_time = ktime_get_boottime(); 1191 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1192 1193 /* reset airtime counters */ 1194 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1195 MT_WF_RMAC_MIB_RXTIME_CLR); 1196 1197 mt7915_mcu_get_chan_mib_info(phy, true); 1198 } 1199 1200 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1201 { 1202 s16 coverage_class = phy->coverage_class; 1203 struct mt7915_dev *dev = phy->dev; 1204 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1205 u32 val, reg_offset; 1206 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1207 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1208 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1209 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1210 u8 band = phy->mt76->band_idx; 1211 int eifs_ofdm = 360, sifs = 10, offset; 1212 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1213 1214 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1215 return; 1216 1217 if (ext_phy) 1218 coverage_class = max_t(s16, dev->phy.coverage_class, 1219 ext_phy->coverage_class); 1220 1221 mt76_set(dev, MT_ARB_SCR(band), 1222 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1223 udelay(1); 1224 1225 offset = 3 * coverage_class; 1226 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1227 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1228 1229 if (!is_mt7915(&dev->mt76)) { 1230 if (!a_band) { 1231 mt76_wr(dev, MT_TMAC_ICR1(band), 1232 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1233 eifs_ofdm = 78; 1234 } else { 1235 eifs_ofdm = 84; 1236 } 1237 } else if (a_band) { 1238 sifs = 16; 1239 } 1240 1241 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1242 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1243 mt76_wr(dev, MT_TMAC_ICR0(band), 1244 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1245 FIELD_PREP(MT_IFS_RIFS, 2) | 1246 FIELD_PREP(MT_IFS_SIFS, sifs) | 1247 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1248 1249 if (phy->slottime < 20 || a_band) 1250 val = MT7915_CFEND_RATE_DEFAULT; 1251 else 1252 val = MT7915_CFEND_RATE_11B; 1253 1254 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1255 mt76_clear(dev, MT_ARB_SCR(band), 1256 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1257 } 1258 1259 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1260 { 1261 u32 reg; 1262 1263 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1264 MT_WF_PHY_RXTD12_MT7916(band); 1265 mt76_set(dev, reg, 1266 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1267 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1268 1269 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1270 MT_WF_PHY_RX_CTRL1_MT7916(band); 1271 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1272 } 1273 1274 static u8 1275 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1276 { 1277 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1278 struct mt7915_dev *dev = phy->dev; 1279 u32 val, sum = 0, n = 0; 1280 int nss, i; 1281 1282 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1283 u32 reg = is_mt7915(&dev->mt76) ? 1284 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1285 MT_WF_IRPI_NSS_MT7916(idx, nss); 1286 1287 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1288 val = mt76_rr(dev, reg); 1289 sum += val * nf_power[i]; 1290 n += val; 1291 } 1292 } 1293 1294 if (!n) 1295 return 0; 1296 1297 return sum / n; 1298 } 1299 1300 void mt7915_update_channel(struct mt76_phy *mphy) 1301 { 1302 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv; 1303 struct mt76_channel_state *state = mphy->chan_state; 1304 int nf; 1305 1306 mt7915_mcu_get_chan_mib_info(phy, false); 1307 1308 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1309 if (!phy->noise) 1310 phy->noise = nf << 4; 1311 else if (nf) 1312 phy->noise += nf - (phy->noise >> 4); 1313 1314 state->noise = -(phy->noise >> 4); 1315 } 1316 1317 static bool 1318 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1319 { 1320 bool ret; 1321 1322 ret = wait_event_timeout(dev->reset_wait, 1323 (READ_ONCE(dev->recovery.state) & state), 1324 MT7915_RESET_TIMEOUT); 1325 1326 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1327 return ret; 1328 } 1329 1330 static void 1331 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1332 { 1333 struct ieee80211_hw *hw = priv; 1334 1335 switch (vif->type) { 1336 case NL80211_IFTYPE_MESH_POINT: 1337 case NL80211_IFTYPE_ADHOC: 1338 case NL80211_IFTYPE_AP: 1339 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1340 BSS_CHANGED_BEACON_ENABLED); 1341 break; 1342 default: 1343 break; 1344 } 1345 } 1346 1347 static void 1348 mt7915_update_beacons(struct mt7915_dev *dev) 1349 { 1350 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1351 1352 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1353 IEEE80211_IFACE_ITER_RESUME_ALL, 1354 mt7915_update_vif_beacon, dev->mt76.hw); 1355 1356 if (!mphy_ext) 1357 return; 1358 1359 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1360 IEEE80211_IFACE_ITER_RESUME_ALL, 1361 mt7915_update_vif_beacon, mphy_ext->hw); 1362 } 1363 1364 void mt7915_tx_token_put(struct mt7915_dev *dev) 1365 { 1366 struct mt76_txwi_cache *txwi; 1367 int id; 1368 1369 spin_lock_bh(&dev->mt76.token_lock); 1370 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1371 mt7915_txwi_free(dev, txwi, NULL, NULL); 1372 dev->mt76.token_count--; 1373 } 1374 spin_unlock_bh(&dev->mt76.token_lock); 1375 idr_destroy(&dev->mt76.token); 1376 } 1377 1378 static int 1379 mt7915_mac_restart(struct mt7915_dev *dev) 1380 { 1381 struct mt7915_phy *phy2; 1382 struct mt76_phy *ext_phy; 1383 struct mt76_dev *mdev = &dev->mt76; 1384 int i, ret; 1385 1386 ext_phy = dev->mt76.phys[MT_BAND1]; 1387 phy2 = ext_phy ? ext_phy->priv : NULL; 1388 1389 if (dev->hif2) { 1390 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1391 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1392 } 1393 1394 if (dev_is_pci(mdev->dev)) { 1395 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1396 if (dev->hif2) 1397 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1398 } 1399 1400 set_bit(MT76_RESET, &dev->mphy.state); 1401 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1402 wake_up(&dev->mt76.mcu.wait); 1403 if (ext_phy) { 1404 set_bit(MT76_RESET, &ext_phy->state); 1405 set_bit(MT76_MCU_RESET, &ext_phy->state); 1406 } 1407 1408 /* lock/unlock all queues to ensure that no tx is pending */ 1409 mt76_txq_schedule_all(&dev->mphy); 1410 if (ext_phy) 1411 mt76_txq_schedule_all(ext_phy); 1412 1413 /* disable all tx/rx napi */ 1414 mt76_worker_disable(&dev->mt76.tx_worker); 1415 mt76_for_each_q_rx(mdev, i) { 1416 if (mdev->q_rx[i].ndesc) 1417 napi_disable(&dev->mt76.napi[i]); 1418 } 1419 napi_disable(&dev->mt76.tx_napi); 1420 1421 /* token reinit */ 1422 mt7915_tx_token_put(dev); 1423 idr_init(&dev->mt76.token); 1424 1425 mt7915_dma_reset(dev, true); 1426 1427 local_bh_disable(); 1428 mt76_for_each_q_rx(mdev, i) { 1429 if (mdev->q_rx[i].ndesc) { 1430 napi_enable(&dev->mt76.napi[i]); 1431 napi_schedule(&dev->mt76.napi[i]); 1432 } 1433 } 1434 local_bh_enable(); 1435 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1436 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1437 1438 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1439 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1440 1441 if (dev->hif2) { 1442 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1443 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1444 } 1445 if (dev_is_pci(mdev->dev)) { 1446 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1447 if (dev->hif2) 1448 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1449 } 1450 1451 /* load firmware */ 1452 ret = mt7915_mcu_init_firmware(dev); 1453 if (ret) 1454 goto out; 1455 1456 /* set the necessary init items */ 1457 ret = mt7915_mcu_set_eeprom(dev); 1458 if (ret) 1459 goto out; 1460 1461 mt7915_mac_init(dev); 1462 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 1463 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 1464 ret = mt7915_txbf_init(dev); 1465 1466 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1467 ret = mt7915_run(dev->mphy.hw); 1468 if (ret) 1469 goto out; 1470 } 1471 1472 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) { 1473 ret = mt7915_run(ext_phy->hw); 1474 if (ret) 1475 goto out; 1476 } 1477 1478 out: 1479 /* reset done */ 1480 clear_bit(MT76_RESET, &dev->mphy.state); 1481 if (phy2) 1482 clear_bit(MT76_RESET, &phy2->mt76->state); 1483 1484 local_bh_disable(); 1485 napi_enable(&dev->mt76.tx_napi); 1486 napi_schedule(&dev->mt76.tx_napi); 1487 local_bh_enable(); 1488 1489 mt76_worker_enable(&dev->mt76.tx_worker); 1490 1491 return ret; 1492 } 1493 1494 static void 1495 mt7915_mac_full_reset(struct mt7915_dev *dev) 1496 { 1497 struct mt76_phy *ext_phy; 1498 int i; 1499 1500 ext_phy = dev->mt76.phys[MT_BAND1]; 1501 1502 dev->recovery.hw_full_reset = true; 1503 1504 wake_up(&dev->mt76.mcu.wait); 1505 ieee80211_stop_queues(mt76_hw(dev)); 1506 if (ext_phy) 1507 ieee80211_stop_queues(ext_phy->hw); 1508 1509 cancel_delayed_work_sync(&dev->mphy.mac_work); 1510 if (ext_phy) 1511 cancel_delayed_work_sync(&ext_phy->mac_work); 1512 1513 mutex_lock(&dev->mt76.mutex); 1514 for (i = 0; i < 10; i++) { 1515 if (!mt7915_mac_restart(dev)) 1516 break; 1517 } 1518 mutex_unlock(&dev->mt76.mutex); 1519 1520 if (i == 10) 1521 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1522 1523 ieee80211_restart_hw(mt76_hw(dev)); 1524 if (ext_phy) 1525 ieee80211_restart_hw(ext_phy->hw); 1526 1527 ieee80211_wake_queues(mt76_hw(dev)); 1528 if (ext_phy) 1529 ieee80211_wake_queues(ext_phy->hw); 1530 1531 dev->recovery.hw_full_reset = false; 1532 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1533 MT7915_WATCHDOG_TIME); 1534 if (ext_phy) 1535 ieee80211_queue_delayed_work(ext_phy->hw, 1536 &ext_phy->mac_work, 1537 MT7915_WATCHDOG_TIME); 1538 } 1539 1540 /* system error recovery */ 1541 void mt7915_mac_reset_work(struct work_struct *work) 1542 { 1543 struct mt7915_phy *phy2; 1544 struct mt76_phy *ext_phy; 1545 struct mt7915_dev *dev; 1546 int i; 1547 1548 dev = container_of(work, struct mt7915_dev, reset_work); 1549 ext_phy = dev->mt76.phys[MT_BAND1]; 1550 phy2 = ext_phy ? ext_phy->priv : NULL; 1551 1552 /* chip full reset */ 1553 if (dev->recovery.restart) { 1554 /* disable WA/WM WDT */ 1555 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1556 MT_MCU_CMD_WDT_MASK); 1557 1558 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1559 dev->recovery.wa_reset_count++; 1560 else 1561 dev->recovery.wm_reset_count++; 1562 1563 mt7915_mac_full_reset(dev); 1564 1565 /* enable mcu irq */ 1566 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1567 mt7915_irq_disable(dev, 0); 1568 1569 /* enable WA/WM WDT */ 1570 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1571 1572 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1573 dev->recovery.restart = false; 1574 return; 1575 } 1576 1577 /* chip partial reset */ 1578 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1579 return; 1580 1581 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 1582 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1583 if (!is_mt7986(&dev->mt76)) 1584 mt76_wr(dev, MT_INT_WED_MASK_CSR, 0); 1585 } 1586 1587 ieee80211_stop_queues(mt76_hw(dev)); 1588 if (ext_phy) 1589 ieee80211_stop_queues(ext_phy->hw); 1590 1591 set_bit(MT76_RESET, &dev->mphy.state); 1592 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1593 wake_up(&dev->mt76.mcu.wait); 1594 cancel_delayed_work_sync(&dev->mphy.mac_work); 1595 if (phy2) { 1596 set_bit(MT76_RESET, &phy2->mt76->state); 1597 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1598 } 1599 mt76_worker_disable(&dev->mt76.tx_worker); 1600 mt76_for_each_q_rx(&dev->mt76, i) 1601 napi_disable(&dev->mt76.napi[i]); 1602 napi_disable(&dev->mt76.tx_napi); 1603 1604 mutex_lock(&dev->mt76.mutex); 1605 1606 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1607 1608 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1609 mt7915_dma_reset(dev, false); 1610 1611 mt7915_tx_token_put(dev); 1612 idr_init(&dev->mt76.token); 1613 1614 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1615 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1616 } 1617 1618 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1619 clear_bit(MT76_RESET, &dev->mphy.state); 1620 if (phy2) 1621 clear_bit(MT76_RESET, &phy2->mt76->state); 1622 1623 local_bh_disable(); 1624 mt76_for_each_q_rx(&dev->mt76, i) { 1625 napi_enable(&dev->mt76.napi[i]); 1626 napi_schedule(&dev->mt76.napi[i]); 1627 } 1628 local_bh_enable(); 1629 1630 tasklet_schedule(&dev->irq_tasklet); 1631 1632 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1633 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1634 1635 mt76_worker_enable(&dev->mt76.tx_worker); 1636 1637 local_bh_disable(); 1638 napi_enable(&dev->mt76.tx_napi); 1639 napi_schedule(&dev->mt76.tx_napi); 1640 local_bh_enable(); 1641 1642 ieee80211_wake_queues(mt76_hw(dev)); 1643 if (ext_phy) 1644 ieee80211_wake_queues(ext_phy->hw); 1645 1646 mutex_unlock(&dev->mt76.mutex); 1647 1648 mt7915_update_beacons(dev); 1649 1650 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1651 MT7915_WATCHDOG_TIME); 1652 if (phy2) 1653 ieee80211_queue_delayed_work(ext_phy->hw, 1654 &phy2->mt76->mac_work, 1655 MT7915_WATCHDOG_TIME); 1656 } 1657 1658 /* firmware coredump */ 1659 void mt7915_mac_dump_work(struct work_struct *work) 1660 { 1661 const struct mt7915_mem_region *mem_region; 1662 struct mt7915_crash_data *crash_data; 1663 struct mt7915_dev *dev; 1664 struct mt7915_mem_hdr *hdr; 1665 size_t buf_len; 1666 int i; 1667 u32 num; 1668 u8 *buf; 1669 1670 dev = container_of(work, struct mt7915_dev, dump_work); 1671 1672 mutex_lock(&dev->dump_mutex); 1673 1674 crash_data = mt7915_coredump_new(dev); 1675 if (!crash_data) { 1676 mutex_unlock(&dev->dump_mutex); 1677 goto skip_coredump; 1678 } 1679 1680 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1681 if (!mem_region || !crash_data->memdump_buf_len) { 1682 mutex_unlock(&dev->dump_mutex); 1683 goto skip_memdump; 1684 } 1685 1686 buf = crash_data->memdump_buf; 1687 buf_len = crash_data->memdump_buf_len; 1688 1689 /* dumping memory content... */ 1690 memset(buf, 0, buf_len); 1691 for (i = 0; i < num; i++) { 1692 if (mem_region->len > buf_len) { 1693 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1694 mem_region->name, 1695 (unsigned long)mem_region->len); 1696 break; 1697 } 1698 1699 /* reserve space for the header */ 1700 hdr = (void *)buf; 1701 buf += sizeof(*hdr); 1702 buf_len -= sizeof(*hdr); 1703 1704 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1705 mem_region->len); 1706 1707 hdr->start = mem_region->start; 1708 hdr->len = mem_region->len; 1709 1710 if (!mem_region->len) 1711 /* note: the header remains, just with zero length */ 1712 break; 1713 1714 buf += mem_region->len; 1715 buf_len -= mem_region->len; 1716 1717 mem_region++; 1718 } 1719 1720 mutex_unlock(&dev->dump_mutex); 1721 1722 skip_memdump: 1723 mt7915_coredump_submit(dev); 1724 skip_coredump: 1725 queue_work(dev->mt76.wq, &dev->reset_work); 1726 } 1727 1728 void mt7915_reset(struct mt7915_dev *dev) 1729 { 1730 if (!dev->recovery.hw_init_done) 1731 return; 1732 1733 if (dev->recovery.hw_full_reset) 1734 return; 1735 1736 /* wm/wa exception: do full recovery */ 1737 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1738 dev->recovery.restart = true; 1739 dev_info(dev->mt76.dev, 1740 "%s indicated firmware crash, attempting recovery\n", 1741 wiphy_name(dev->mt76.hw->wiphy)); 1742 1743 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1744 queue_work(dev->mt76.wq, &dev->dump_work); 1745 return; 1746 } 1747 1748 queue_work(dev->mt76.wq, &dev->reset_work); 1749 wake_up(&dev->reset_wait); 1750 } 1751 1752 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1753 { 1754 struct mt7915_dev *dev = phy->dev; 1755 struct mib_stats *mib = &phy->mib; 1756 int i, aggr0 = 0, aggr1, cnt; 1757 u8 band = phy->mt76->band_idx; 1758 u32 val; 1759 1760 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1761 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1762 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1763 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1764 1765 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1766 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1767 1768 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1769 mib->rx_mpdu_cnt += cnt; 1770 1771 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1772 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1773 1774 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1775 mib->rx_vector_mismatch_cnt += 1776 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1777 1778 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1779 mib->rx_delimiter_fail_cnt += 1780 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1781 1782 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1783 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1784 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1785 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1786 1787 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1788 mib->rx_len_mismatch_cnt += 1789 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1790 1791 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1792 mib->tx_ampdu_cnt += cnt; 1793 1794 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1795 mib->tx_stop_q_empty_cnt += 1796 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1797 1798 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1799 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1800 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1801 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1802 1803 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1804 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1805 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1806 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1807 1808 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1809 mib->primary_cca_busy_time += 1810 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1811 1812 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1813 mib->secondary_cca_busy_time += 1814 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1815 1816 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1817 mib->primary_energy_detect_time += 1818 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1819 1820 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1821 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1822 1823 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1824 mib->ofdm_mdrdy_time += 1825 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1826 1827 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1828 mib->green_mdrdy_time += 1829 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1830 1831 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1832 mib->rx_ampdu_cnt += cnt; 1833 1834 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1835 mib->rx_ampdu_bytes_cnt += cnt; 1836 1837 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1838 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1839 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1840 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1841 1842 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1843 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1844 1845 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1846 mib->tx_rwp_fail_cnt += 1847 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1848 1849 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1850 mib->tx_rwp_need_cnt += 1851 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1852 1853 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1854 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1855 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1856 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1857 1858 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1859 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1860 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1861 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1862 1863 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1864 mib->rx_ba_cnt += cnt; 1865 1866 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1867 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1868 1869 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1870 mib->tx_mu_mpdu_cnt += cnt; 1871 1872 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1873 mib->tx_mu_acked_mpdu_cnt += cnt; 1874 1875 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1876 mib->tx_su_acked_mpdu_cnt += cnt; 1877 1878 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1879 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1880 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1881 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1882 1883 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1884 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1885 mib->tx_amsdu[i] += cnt; 1886 mib->tx_amsdu_cnt += cnt; 1887 } 1888 1889 if (is_mt7915(&dev->mt76)) { 1890 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1891 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1892 mib->ba_miss_cnt += 1893 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1894 mib->ack_fail_cnt += 1895 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1896 1897 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1898 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1899 mib->rts_retries_cnt += 1900 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1901 1902 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1903 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1904 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1905 1906 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1907 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1908 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1909 } 1910 1911 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1912 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1913 1914 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1915 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1916 1917 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1918 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1919 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1920 1921 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1922 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1923 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1924 1925 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1926 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1927 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1928 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1929 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1930 } else { 1931 for (i = 0; i < 2; i++) { 1932 /* rts count */ 1933 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1934 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1935 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1936 1937 /* rts retry count */ 1938 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1939 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1940 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1941 1942 /* ba miss count */ 1943 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1944 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1945 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1946 1947 /* ack fail count */ 1948 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1949 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1950 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1951 } 1952 1953 for (i = 0; i < 8; i++) { 1954 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1955 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1956 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1957 } 1958 1959 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1960 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1961 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1962 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1963 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1964 1965 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1966 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1967 1968 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1969 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1970 1971 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1972 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1973 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1974 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1975 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1976 1977 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1978 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1979 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1980 } 1981 } 1982 1983 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1984 { 1985 struct mt7915_dev *dev = phy->dev; 1986 u32 trb; 1987 1988 if (!phy->omac_mask) 1989 return; 1990 1991 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1992 * stopping Rx, so check status periodically to see if TRB hardware 1993 * requires minimal recovery. 1994 */ 1995 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1996 1997 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1998 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1999 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 2000 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 2001 trb == phy->trb_ts) 2002 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 2003 phy->mt76->band_idx); 2004 2005 phy->trb_ts = trb; 2006 } 2007 2008 void mt7915_mac_sta_rc_work(struct work_struct *work) 2009 { 2010 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 2011 struct ieee80211_sta *sta; 2012 struct ieee80211_vif *vif; 2013 struct mt7915_sta *msta; 2014 u32 changed; 2015 LIST_HEAD(list); 2016 2017 spin_lock_bh(&dev->sta_poll_lock); 2018 list_splice_init(&dev->sta_rc_list, &list); 2019 2020 while (!list_empty(&list)) { 2021 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 2022 list_del_init(&msta->rc_list); 2023 changed = msta->changed; 2024 msta->changed = 0; 2025 spin_unlock_bh(&dev->sta_poll_lock); 2026 2027 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2028 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2029 2030 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2031 IEEE80211_RC_NSS_CHANGED | 2032 IEEE80211_RC_BW_CHANGED)) 2033 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 2034 2035 if (changed & IEEE80211_RC_SMPS_CHANGED) 2036 mt7915_mcu_add_smps(dev, vif, sta); 2037 2038 spin_lock_bh(&dev->sta_poll_lock); 2039 } 2040 2041 spin_unlock_bh(&dev->sta_poll_lock); 2042 } 2043 2044 void mt7915_mac_work(struct work_struct *work) 2045 { 2046 struct mt7915_phy *phy; 2047 struct mt76_phy *mphy; 2048 2049 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2050 mac_work.work); 2051 phy = mphy->priv; 2052 2053 mutex_lock(&mphy->dev->mutex); 2054 2055 mt76_update_survey(mphy); 2056 if (++mphy->mac_work_count == 5) { 2057 mphy->mac_work_count = 0; 2058 2059 mt7915_mac_update_stats(phy); 2060 mt7915_mac_severe_check(phy); 2061 } 2062 2063 mutex_unlock(&mphy->dev->mutex); 2064 2065 mt76_tx_status_check(mphy->dev, false); 2066 2067 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2068 MT7915_WATCHDOG_TIME); 2069 } 2070 2071 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2072 { 2073 struct mt7915_dev *dev = phy->dev; 2074 2075 if (phy->rdd_state & BIT(0)) 2076 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2077 MT_RX_SEL0, 0); 2078 if (phy->rdd_state & BIT(1)) 2079 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2080 MT_RX_SEL0, 0); 2081 } 2082 2083 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 2084 { 2085 int err, region; 2086 2087 switch (dev->mt76.region) { 2088 case NL80211_DFS_ETSI: 2089 region = 0; 2090 break; 2091 case NL80211_DFS_JP: 2092 region = 2; 2093 break; 2094 case NL80211_DFS_FCC: 2095 default: 2096 region = 1; 2097 break; 2098 } 2099 2100 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2101 MT_RX_SEL0, region); 2102 if (err < 0) 2103 return err; 2104 2105 if (is_mt7915(&dev->mt76)) { 2106 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, chain, 2107 0, dev->dbdc_support ? 2 : 0); 2108 if (err < 0) 2109 return err; 2110 } 2111 2112 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2113 MT_RX_SEL0, 1); 2114 } 2115 2116 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2117 { 2118 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2119 struct mt7915_dev *dev = phy->dev; 2120 int err; 2121 2122 /* start CAC */ 2123 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, 2124 phy->mt76->band_idx, MT_RX_SEL0, 0); 2125 if (err < 0) 2126 return err; 2127 2128 err = mt7915_dfs_start_rdd(dev, phy->mt76->band_idx); 2129 if (err < 0) 2130 return err; 2131 2132 phy->rdd_state |= BIT(phy->mt76->band_idx); 2133 2134 if (!is_mt7915(&dev->mt76)) 2135 return 0; 2136 2137 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2138 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2139 err = mt7915_dfs_start_rdd(dev, 1); 2140 if (err < 0) 2141 return err; 2142 2143 phy->rdd_state |= BIT(1); 2144 } 2145 2146 return 0; 2147 } 2148 2149 static int 2150 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2151 { 2152 const struct mt7915_dfs_radar_spec *radar_specs; 2153 struct mt7915_dev *dev = phy->dev; 2154 int err, i; 2155 2156 switch (dev->mt76.region) { 2157 case NL80211_DFS_FCC: 2158 radar_specs = &fcc_radar_specs; 2159 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2160 if (err < 0) 2161 return err; 2162 break; 2163 case NL80211_DFS_ETSI: 2164 radar_specs = &etsi_radar_specs; 2165 break; 2166 case NL80211_DFS_JP: 2167 radar_specs = &jp_radar_specs; 2168 break; 2169 default: 2170 return -EINVAL; 2171 } 2172 2173 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2174 err = mt7915_mcu_set_radar_th(dev, i, 2175 &radar_specs->radar_pattern[i]); 2176 if (err < 0) 2177 return err; 2178 } 2179 2180 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2181 } 2182 2183 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2184 { 2185 struct mt7915_dev *dev = phy->dev; 2186 enum mt76_dfs_state dfs_state, prev_state; 2187 int err; 2188 2189 prev_state = phy->mt76->dfs_state; 2190 dfs_state = mt76_phy_dfs_state(phy->mt76); 2191 2192 if (prev_state == dfs_state) 2193 return 0; 2194 2195 if (prev_state == MT_DFS_STATE_UNKNOWN) 2196 mt7915_dfs_stop_radar_detector(phy); 2197 2198 if (dfs_state == MT_DFS_STATE_DISABLED) 2199 goto stop; 2200 2201 if (prev_state <= MT_DFS_STATE_DISABLED) { 2202 err = mt7915_dfs_init_radar_specs(phy); 2203 if (err < 0) 2204 return err; 2205 2206 err = mt7915_dfs_start_radar_detector(phy); 2207 if (err < 0) 2208 return err; 2209 2210 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2211 } 2212 2213 if (dfs_state == MT_DFS_STATE_CAC) 2214 return 0; 2215 2216 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2217 phy->mt76->band_idx, MT_RX_SEL0, 0); 2218 if (err < 0) { 2219 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2220 return err; 2221 } 2222 2223 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2224 return 0; 2225 2226 stop: 2227 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, 2228 phy->mt76->band_idx, MT_RX_SEL0, 0); 2229 if (err < 0) 2230 return err; 2231 2232 if (is_mt7915(&dev->mt76)) { 2233 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2234 phy->mt76->band_idx, 0, 2235 dev->dbdc_support ? 2 : 0); 2236 if (err < 0) 2237 return err; 2238 } 2239 2240 mt7915_dfs_stop_radar_detector(phy); 2241 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2242 2243 return 0; 2244 } 2245 2246 static int 2247 mt7915_mac_twt_duration_align(int duration) 2248 { 2249 return duration << 8; 2250 } 2251 2252 static u64 2253 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2254 struct mt7915_twt_flow *flow) 2255 { 2256 struct mt7915_twt_flow *iter, *iter_next; 2257 u32 duration = flow->duration << 8; 2258 u64 start_tsf; 2259 2260 iter = list_first_entry_or_null(&dev->twt_list, 2261 struct mt7915_twt_flow, list); 2262 if (!iter || !iter->sched || iter->start_tsf > duration) { 2263 /* add flow as first entry in the list */ 2264 list_add(&flow->list, &dev->twt_list); 2265 return 0; 2266 } 2267 2268 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2269 start_tsf = iter->start_tsf + 2270 mt7915_mac_twt_duration_align(iter->duration); 2271 if (list_is_last(&iter->list, &dev->twt_list)) 2272 break; 2273 2274 if (!iter_next->sched || 2275 iter_next->start_tsf > start_tsf + duration) { 2276 list_add(&flow->list, &iter->list); 2277 goto out; 2278 } 2279 } 2280 2281 /* add flow as last entry in the list */ 2282 list_add_tail(&flow->list, &dev->twt_list); 2283 out: 2284 return start_tsf; 2285 } 2286 2287 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2288 { 2289 struct ieee80211_twt_params *twt_agrt; 2290 u64 interval, duration; 2291 u16 mantissa; 2292 u8 exp; 2293 2294 /* only individual agreement supported */ 2295 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2296 return -EOPNOTSUPP; 2297 2298 /* only 256us unit supported */ 2299 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2300 return -EOPNOTSUPP; 2301 2302 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2303 2304 /* explicit agreement not supported */ 2305 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2306 return -EOPNOTSUPP; 2307 2308 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2309 le16_to_cpu(twt_agrt->req_type)); 2310 mantissa = le16_to_cpu(twt_agrt->mantissa); 2311 duration = twt_agrt->min_twt_dur << 8; 2312 2313 interval = (u64)mantissa << exp; 2314 if (interval < duration) 2315 return -EOPNOTSUPP; 2316 2317 return 0; 2318 } 2319 2320 static bool 2321 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2322 struct ieee80211_twt_params *twt_agrt) 2323 { 2324 u16 type = le16_to_cpu(twt_agrt->req_type); 2325 u8 exp; 2326 int i; 2327 2328 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2329 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2330 struct mt7915_twt_flow *f; 2331 2332 if (!(msta->twt.flowid_mask & BIT(i))) 2333 continue; 2334 2335 f = &msta->twt.flow[i]; 2336 if (f->duration == twt_agrt->min_twt_dur && 2337 f->mantissa == twt_agrt->mantissa && 2338 f->exp == exp && 2339 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2340 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2341 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2342 return true; 2343 } 2344 2345 return false; 2346 } 2347 2348 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2349 struct ieee80211_sta *sta, 2350 struct ieee80211_twt_setup *twt) 2351 { 2352 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2353 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2354 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2355 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2356 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2357 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2358 struct mt7915_twt_flow *flow; 2359 int flowid, table_id; 2360 u8 exp; 2361 2362 if (mt7915_mac_check_twt_req(twt)) 2363 goto out; 2364 2365 mutex_lock(&dev->mt76.mutex); 2366 2367 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2368 goto unlock; 2369 2370 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2371 goto unlock; 2372 2373 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2374 setup_cmd = TWT_SETUP_CMD_DICTATE; 2375 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2376 goto unlock; 2377 } 2378 2379 flowid = ffs(~msta->twt.flowid_mask) - 1; 2380 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2381 twt_agrt->req_type |= le16_encode_bits(flowid, 2382 IEEE80211_TWT_REQTYPE_FLOWID); 2383 2384 table_id = ffs(~dev->twt.table_mask) - 1; 2385 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2386 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2387 2388 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2389 goto unlock; 2390 2391 flow = &msta->twt.flow[flowid]; 2392 memset(flow, 0, sizeof(*flow)); 2393 INIT_LIST_HEAD(&flow->list); 2394 flow->wcid = msta->wcid.idx; 2395 flow->table_id = table_id; 2396 flow->id = flowid; 2397 flow->duration = twt_agrt->min_twt_dur; 2398 flow->mantissa = twt_agrt->mantissa; 2399 flow->exp = exp; 2400 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2401 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2402 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2403 2404 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2405 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2406 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2407 u64 flow_tsf, curr_tsf; 2408 u32 rem; 2409 2410 flow->sched = true; 2411 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2412 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2413 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2414 flow_tsf = curr_tsf + interval - rem; 2415 twt_agrt->twt = cpu_to_le64(flow_tsf); 2416 } else { 2417 list_add_tail(&flow->list, &dev->twt_list); 2418 } 2419 flow->tsf = le64_to_cpu(twt_agrt->twt); 2420 2421 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2422 goto unlock; 2423 2424 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2425 dev->twt.table_mask |= BIT(table_id); 2426 msta->twt.flowid_mask |= BIT(flowid); 2427 dev->twt.n_agrt++; 2428 2429 unlock: 2430 mutex_unlock(&dev->mt76.mutex); 2431 out: 2432 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2433 twt_agrt->req_type |= 2434 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2435 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2436 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2437 } 2438 2439 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2440 struct mt7915_sta *msta, 2441 u8 flowid) 2442 { 2443 struct mt7915_twt_flow *flow; 2444 2445 lockdep_assert_held(&dev->mt76.mutex); 2446 2447 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2448 return; 2449 2450 if (!(msta->twt.flowid_mask & BIT(flowid))) 2451 return; 2452 2453 flow = &msta->twt.flow[flowid]; 2454 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2455 MCU_TWT_AGRT_DELETE)) 2456 return; 2457 2458 list_del_init(&flow->list); 2459 msta->twt.flowid_mask &= ~BIT(flowid); 2460 dev->twt.table_mask &= ~BIT(flow->table_id); 2461 dev->twt.n_agrt--; 2462 } 2463