1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #include "mt7915.h" 7 #include "../dma.h" 8 #include "mac.h" 9 #include "mcu.h" 10 11 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 12 13 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) 14 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ 15 IEEE80211_RADIOTAP_HE_##f) 16 17 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 18 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 19 .radar_pattern = { 20 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 21 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 22 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 23 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 24 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 25 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 26 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 27 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 28 }, 29 }; 30 31 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 32 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 33 .radar_pattern = { 34 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 35 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 36 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 37 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 38 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 39 }, 40 }; 41 42 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 43 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 44 .radar_pattern = { 45 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 46 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 47 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 48 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 49 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 50 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 51 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 52 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 53 }, 54 }; 55 56 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 57 u16 idx, bool unicast) 58 { 59 struct mt7915_sta *sta; 60 struct mt76_wcid *wcid; 61 62 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 63 return NULL; 64 65 wcid = rcu_dereference(dev->mt76.wcid[idx]); 66 if (unicast || !wcid) 67 return wcid; 68 69 if (!wcid->sta) 70 return NULL; 71 72 sta = container_of(wcid, struct mt7915_sta, wcid); 73 if (!sta->vif) 74 return NULL; 75 76 return &sta->vif->sta.wcid; 77 } 78 79 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 80 { 81 } 82 83 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 84 { 85 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 86 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 87 88 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 89 0, 5000); 90 } 91 92 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 93 { 94 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 95 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 96 97 return MT_WTBL_LMAC_OFFS(wcid, dw); 98 } 99 100 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 101 { 102 static const u8 ac_to_tid[] = { 103 [IEEE80211_AC_BE] = 0, 104 [IEEE80211_AC_BK] = 1, 105 [IEEE80211_AC_VI] = 4, 106 [IEEE80211_AC_VO] = 6 107 }; 108 struct ieee80211_sta *sta; 109 struct mt7915_sta *msta; 110 struct rate_info *rate; 111 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 112 LIST_HEAD(sta_poll_list); 113 int i; 114 115 spin_lock_bh(&dev->sta_poll_lock); 116 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 117 spin_unlock_bh(&dev->sta_poll_lock); 118 119 rcu_read_lock(); 120 121 while (true) { 122 bool clear = false; 123 u32 addr, val; 124 u16 idx; 125 u8 bw; 126 127 spin_lock_bh(&dev->sta_poll_lock); 128 if (list_empty(&sta_poll_list)) { 129 spin_unlock_bh(&dev->sta_poll_lock); 130 break; 131 } 132 msta = list_first_entry(&sta_poll_list, 133 struct mt7915_sta, poll_list); 134 list_del_init(&msta->poll_list); 135 spin_unlock_bh(&dev->sta_poll_lock); 136 137 idx = msta->wcid.idx; 138 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 139 140 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 141 u32 tx_last = msta->airtime_ac[i]; 142 u32 rx_last = msta->airtime_ac[i + 4]; 143 144 msta->airtime_ac[i] = mt76_rr(dev, addr); 145 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 146 147 tx_time[i] = msta->airtime_ac[i] - tx_last; 148 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 149 150 if ((tx_last | rx_last) & BIT(30)) 151 clear = true; 152 153 addr += 8; 154 } 155 156 if (clear) { 157 mt7915_mac_wtbl_update(dev, idx, 158 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 159 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 160 } 161 162 if (!msta->wcid.sta) 163 continue; 164 165 sta = container_of((void *)msta, struct ieee80211_sta, 166 drv_priv); 167 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 168 u8 q = mt7915_lmac_mapping(dev, i); 169 u32 tx_cur = tx_time[q]; 170 u32 rx_cur = rx_time[q]; 171 u8 tid = ac_to_tid[i]; 172 173 if (!tx_cur && !rx_cur) 174 continue; 175 176 ieee80211_sta_register_airtime(sta, tid, tx_cur, 177 rx_cur); 178 } 179 180 /* 181 * We don't support reading GI info from txs packets. 182 * For accurate tx status reporting and AQL improvement, 183 * we need to make sure that flags match so polling GI 184 * from per-sta counters directly. 185 */ 186 rate = &msta->wcid.rate; 187 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 188 val = mt76_rr(dev, addr); 189 190 switch (rate->bw) { 191 case RATE_INFO_BW_160: 192 bw = IEEE80211_STA_RX_BW_160; 193 break; 194 case RATE_INFO_BW_80: 195 bw = IEEE80211_STA_RX_BW_80; 196 break; 197 case RATE_INFO_BW_40: 198 bw = IEEE80211_STA_RX_BW_40; 199 break; 200 default: 201 bw = IEEE80211_STA_RX_BW_20; 202 break; 203 } 204 205 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 206 u8 offs = 24 + 2 * bw; 207 208 rate->he_gi = (val & (0x3 << offs)) >> offs; 209 } else if (rate->flags & 210 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 211 if (val & BIT(12 + bw)) 212 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 213 else 214 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 215 } 216 } 217 218 rcu_read_unlock(); 219 } 220 221 static void 222 mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, 223 struct ieee80211_radiotap_he *he, 224 __le32 *rxv) 225 { 226 u32 ru_h, ru_l; 227 u8 ru, offs = 0; 228 229 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0])); 230 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1])); 231 ru = (u8)(ru_l | ru_h << 4); 232 233 status->bw = RATE_INFO_BW_HE_RU; 234 235 switch (ru) { 236 case 0 ... 36: 237 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; 238 offs = ru; 239 break; 240 case 37 ... 52: 241 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; 242 offs = ru - 37; 243 break; 244 case 53 ... 60: 245 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; 246 offs = ru - 53; 247 break; 248 case 61 ... 64: 249 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; 250 offs = ru - 61; 251 break; 252 case 65 ... 66: 253 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; 254 offs = ru - 65; 255 break; 256 case 67: 257 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; 258 break; 259 case 68: 260 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 261 break; 262 } 263 264 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); 265 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | 266 le16_encode_bits(offs, 267 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); 268 } 269 270 static void 271 mt7915_mac_decode_he_mu_radiotap(struct sk_buff *skb, 272 struct mt76_rx_status *status, 273 __le32 *rxv) 274 { 275 static const struct ieee80211_radiotap_he_mu mu_known = { 276 .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | 277 HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | 278 HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | 279 HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN), 280 .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN), 281 }; 282 struct ieee80211_radiotap_he_mu *he_mu = NULL; 283 284 he_mu = skb_push(skb, sizeof(mu_known)); 285 memcpy(he_mu, &mu_known, sizeof(mu_known)); 286 287 #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) 288 289 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); 290 if (status->he_dcm) 291 he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); 292 293 he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | 294 MU_PREP(FLAGS2_SIG_B_SYMS_USERS, 295 le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); 296 297 he_mu->ru_ch1[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU0); 298 299 if (status->bw >= RATE_INFO_BW_40) { 300 he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); 301 he_mu->ru_ch2[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU1); 302 } 303 304 if (status->bw >= RATE_INFO_BW_80) { 305 he_mu->ru_ch1[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU2); 306 he_mu->ru_ch2[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU3); 307 } 308 } 309 310 static void 311 mt7915_mac_decode_he_radiotap(struct sk_buff *skb, 312 struct mt76_rx_status *status, 313 __le32 *rxv, u32 phy) 314 { 315 static const struct ieee80211_radiotap_he known = { 316 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | 317 HE_BITS(DATA1_DATA_DCM_KNOWN) | 318 HE_BITS(DATA1_STBC_KNOWN) | 319 HE_BITS(DATA1_CODING_KNOWN) | 320 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | 321 HE_BITS(DATA1_DOPPLER_KNOWN) | 322 HE_BITS(DATA1_SPTL_REUSE_KNOWN) | 323 HE_BITS(DATA1_BSS_COLOR_KNOWN), 324 .data2 = HE_BITS(DATA2_GI_KNOWN) | 325 HE_BITS(DATA2_TXBF_KNOWN) | 326 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | 327 HE_BITS(DATA2_TXOP_KNOWN), 328 }; 329 struct ieee80211_radiotap_he *he = NULL; 330 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; 331 332 he = skb_push(skb, sizeof(known)); 333 memcpy(he, &known, sizeof(known)); 334 335 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | 336 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); 337 he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); 338 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | 339 le16_encode_bits(ltf_size, 340 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); 341 if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) 342 he->data5 |= HE_BITS(DATA5_TXBF); 343 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | 344 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); 345 346 switch (phy) { 347 case MT_PHY_TYPE_HE_SU: 348 he->data1 |= HE_BITS(DATA1_FORMAT_SU) | 349 HE_BITS(DATA1_UL_DL_KNOWN) | 350 HE_BITS(DATA1_BEAM_CHANGE_KNOWN); 351 352 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | 353 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 354 break; 355 case MT_PHY_TYPE_HE_EXT_SU: 356 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | 357 HE_BITS(DATA1_UL_DL_KNOWN); 358 359 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 360 break; 361 case MT_PHY_TYPE_HE_MU: 362 he->data1 |= HE_BITS(DATA1_FORMAT_MU) | 363 HE_BITS(DATA1_UL_DL_KNOWN); 364 365 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); 366 he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); 367 368 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 369 break; 370 case MT_PHY_TYPE_HE_TB: 371 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | 372 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | 373 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | 374 HE_BITS(DATA1_SPTL_REUSE4_KNOWN); 375 376 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | 377 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | 378 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); 379 380 mt7915_mac_decode_he_radiotap_ru(status, he, rxv); 381 break; 382 default: 383 break; 384 } 385 } 386 387 static int 388 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) 389 { 390 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 391 struct mt76_phy *mphy = &dev->mt76.phy; 392 struct mt7915_phy *phy = &dev->phy; 393 struct ieee80211_supported_band *sband; 394 struct ieee80211_hdr *hdr; 395 __le32 *rxd = (__le32 *)skb->data; 396 __le32 *rxv = NULL; 397 u32 mode = 0; 398 u32 rxd0 = le32_to_cpu(rxd[0]); 399 u32 rxd1 = le32_to_cpu(rxd[1]); 400 u32 rxd2 = le32_to_cpu(rxd[2]); 401 u32 rxd3 = le32_to_cpu(rxd[3]); 402 u32 rxd4 = le32_to_cpu(rxd[4]); 403 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 404 bool unicast, insert_ccmp_hdr = false; 405 u8 remove_pad, amsdu_info; 406 bool hdr_trans; 407 u16 seq_ctrl = 0; 408 u8 qos_ctl = 0; 409 __le16 fc = 0; 410 int i, idx; 411 412 memset(status, 0, sizeof(*status)); 413 414 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) { 415 mphy = dev->mt76.phy2; 416 if (!mphy) 417 return -EINVAL; 418 419 phy = mphy->priv; 420 status->ext_phy = true; 421 } 422 423 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 424 return -EINVAL; 425 426 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 427 return -EINVAL; 428 429 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 430 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 431 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 432 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 433 434 if (status->wcid) { 435 struct mt7915_sta *msta; 436 437 msta = container_of(status->wcid, struct mt7915_sta, wcid); 438 spin_lock_bh(&dev->sta_poll_lock); 439 if (list_empty(&msta->poll_list)) 440 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 441 spin_unlock_bh(&dev->sta_poll_lock); 442 } 443 444 status->freq = mphy->chandef.chan->center_freq; 445 status->band = mphy->chandef.chan->band; 446 if (status->band == NL80211_BAND_5GHZ) 447 sband = &mphy->sband_5g.sband; 448 else 449 sband = &mphy->sband_2g.sband; 450 451 if (!sband->channels) 452 return -EINVAL; 453 454 if ((rxd0 & csum_mask) == csum_mask) 455 skb->ip_summed = CHECKSUM_UNNECESSARY; 456 457 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 458 status->flag |= RX_FLAG_FAILED_FCS_CRC; 459 460 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 461 status->flag |= RX_FLAG_MMIC_ERROR; 462 463 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 464 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 465 status->flag |= RX_FLAG_DECRYPTED; 466 status->flag |= RX_FLAG_IV_STRIPPED; 467 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 468 } 469 470 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 471 472 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 473 return -EINVAL; 474 475 rxd += 6; 476 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 477 u32 v0 = le32_to_cpu(rxd[0]); 478 u32 v2 = le32_to_cpu(rxd[2]); 479 480 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 481 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 482 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 483 484 rxd += 4; 485 if ((u8 *)rxd - skb->data >= skb->len) 486 return -EINVAL; 487 } 488 489 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 490 u8 *data = (u8 *)rxd; 491 492 if (status->flag & RX_FLAG_DECRYPTED) { 493 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 494 case MT_CIPHER_AES_CCMP: 495 case MT_CIPHER_CCMP_CCX: 496 case MT_CIPHER_CCMP_256: 497 insert_ccmp_hdr = 498 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 499 fallthrough; 500 case MT_CIPHER_TKIP: 501 case MT_CIPHER_TKIP_NO_MIC: 502 case MT_CIPHER_GCMP: 503 case MT_CIPHER_GCMP_256: 504 status->iv[0] = data[5]; 505 status->iv[1] = data[4]; 506 status->iv[2] = data[3]; 507 status->iv[3] = data[2]; 508 status->iv[4] = data[1]; 509 status->iv[5] = data[0]; 510 break; 511 default: 512 break; 513 } 514 } 515 rxd += 4; 516 if ((u8 *)rxd - skb->data >= skb->len) 517 return -EINVAL; 518 } 519 520 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 521 status->timestamp = le32_to_cpu(rxd[0]); 522 status->flag |= RX_FLAG_MACTIME_START; 523 524 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 525 status->flag |= RX_FLAG_AMPDU_DETAILS; 526 527 /* all subframes of an A-MPDU have the same timestamp */ 528 if (phy->rx_ampdu_ts != status->timestamp) { 529 if (!++phy->ampdu_ref) 530 phy->ampdu_ref++; 531 } 532 phy->rx_ampdu_ts = status->timestamp; 533 534 status->ampdu_ref = phy->ampdu_ref; 535 } 536 537 rxd += 2; 538 if ((u8 *)rxd - skb->data >= skb->len) 539 return -EINVAL; 540 } 541 542 /* RXD Group 3 - P-RXV */ 543 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 544 u32 v0, v1, v2; 545 546 rxv = rxd; 547 rxd += 2; 548 if ((u8 *)rxd - skb->data >= skb->len) 549 return -EINVAL; 550 551 v0 = le32_to_cpu(rxv[0]); 552 v1 = le32_to_cpu(rxv[1]); 553 v2 = le32_to_cpu(rxv[2]); 554 555 if (v0 & MT_PRXV_HT_AD_CODE) 556 status->enc_flags |= RX_ENC_FLAG_LDPC; 557 558 status->chains = mphy->antenna_mask; 559 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 560 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 561 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 562 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 563 status->signal = status->chain_signal[0]; 564 565 for (i = 1; i < hweight8(mphy->antenna_mask); i++) { 566 if (!(status->chains & BIT(i))) 567 continue; 568 569 status->signal = max(status->signal, 570 status->chain_signal[i]); 571 } 572 573 /* RXD Group 5 - C-RXV */ 574 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 575 u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2); 576 u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2); 577 bool cck = false; 578 579 rxd += 18; 580 if ((u8 *)rxd - skb->data >= skb->len) 581 return -EINVAL; 582 583 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); 584 mode = FIELD_GET(MT_CRXV_TX_MODE, v2); 585 586 switch (mode) { 587 case MT_PHY_TYPE_CCK: 588 cck = true; 589 fallthrough; 590 case MT_PHY_TYPE_OFDM: 591 i = mt76_get_rate(&dev->mt76, sband, i, cck); 592 break; 593 case MT_PHY_TYPE_HT_GF: 594 case MT_PHY_TYPE_HT: 595 status->encoding = RX_ENC_HT; 596 if (i > 31) 597 return -EINVAL; 598 break; 599 case MT_PHY_TYPE_VHT: 600 status->nss = 601 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 602 status->encoding = RX_ENC_VHT; 603 if (i > 9) 604 return -EINVAL; 605 break; 606 case MT_PHY_TYPE_HE_MU: 607 status->flag |= RX_FLAG_RADIOTAP_HE_MU; 608 fallthrough; 609 case MT_PHY_TYPE_HE_SU: 610 case MT_PHY_TYPE_HE_EXT_SU: 611 case MT_PHY_TYPE_HE_TB: 612 status->nss = 613 FIELD_GET(MT_PRXV_NSTS, v0) + 1; 614 status->encoding = RX_ENC_HE; 615 status->flag |= RX_FLAG_RADIOTAP_HE; 616 i &= GENMASK(3, 0); 617 618 if (gi <= NL80211_RATE_INFO_HE_GI_3_2) 619 status->he_gi = gi; 620 621 status->he_dcm = !!(idx & MT_PRXV_TX_DCM); 622 break; 623 default: 624 return -EINVAL; 625 } 626 status->rate_idx = i; 627 628 switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) { 629 case IEEE80211_STA_RX_BW_20: 630 break; 631 case IEEE80211_STA_RX_BW_40: 632 if (mode & MT_PHY_TYPE_HE_EXT_SU && 633 (idx & MT_PRXV_TX_ER_SU_106T)) { 634 status->bw = RATE_INFO_BW_HE_RU; 635 status->he_ru = 636 NL80211_RATE_INFO_HE_RU_ALLOC_106; 637 } else { 638 status->bw = RATE_INFO_BW_40; 639 } 640 break; 641 case IEEE80211_STA_RX_BW_80: 642 status->bw = RATE_INFO_BW_80; 643 break; 644 case IEEE80211_STA_RX_BW_160: 645 status->bw = RATE_INFO_BW_160; 646 break; 647 default: 648 return -EINVAL; 649 } 650 651 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 652 if (mode < MT_PHY_TYPE_HE_SU && gi) 653 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 654 } 655 } 656 657 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 658 659 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 660 status->amsdu = !!amsdu_info; 661 if (status->amsdu) { 662 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 663 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 664 if (!hdr_trans) { 665 memmove(skb->data + 2, skb->data, 666 ieee80211_get_hdrlen_from_skb(skb)); 667 skb_pull(skb, 2); 668 } 669 } 670 671 if (insert_ccmp_hdr && !hdr_trans) { 672 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 673 674 mt76_insert_ccmp_hdr(skb, key_id); 675 } 676 677 if (!hdr_trans) { 678 hdr = mt76_skb_get_hdr(skb); 679 fc = hdr->frame_control; 680 if (ieee80211_is_data_qos(fc)) { 681 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 682 qos_ctl = *ieee80211_get_qos_ctl(hdr); 683 } 684 } else { 685 status->flag &= ~(RX_FLAG_RADIOTAP_HE | 686 RX_FLAG_RADIOTAP_HE_MU); 687 status->flag |= RX_FLAG_8023; 688 } 689 690 if (rxv && status->flag & RX_FLAG_RADIOTAP_HE) { 691 mt7915_mac_decode_he_radiotap(skb, status, rxv, mode); 692 if (status->flag & RX_FLAG_RADIOTAP_HE_MU) 693 mt7915_mac_decode_he_mu_radiotap(skb, status, rxv); 694 } 695 696 if (!status->wcid || !ieee80211_is_data_qos(fc)) 697 return 0; 698 699 status->aggr = unicast && 700 !ieee80211_is_qos_nullfunc(fc); 701 status->qos_ctl = qos_ctl; 702 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 703 704 return 0; 705 } 706 707 static void 708 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 709 { 710 #ifdef CONFIG_NL80211_TESTMODE 711 struct mt7915_phy *phy = &dev->phy; 712 __le32 *rxd = (__le32 *)skb->data; 713 __le32 *rxv_hdr = rxd + 2; 714 __le32 *rxv = rxd + 4; 715 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 716 bool ext_phy; 717 s32 foe; 718 u8 snr; 719 int i; 720 721 ext_phy = FIELD_GET(MT_RXV_HDR_BAND_IDX, le32_to_cpu(rxv_hdr[1])); 722 if (ext_phy) 723 phy = mt7915_ext_phy(dev); 724 725 rcpi = le32_to_cpu(rxv[6]); 726 ib_rssi = le32_to_cpu(rxv[7]); 727 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 728 729 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 730 if (i == 3) 731 wb_rssi = le32_to_cpu(rxv[9]); 732 733 phy->test.last_rcpi[i] = rcpi & 0xff; 734 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 735 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 736 } 737 738 v20 = le32_to_cpu(rxv[20]); 739 v21 = le32_to_cpu(rxv[21]); 740 741 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 742 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 743 744 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 745 746 phy->test.last_freq_offset = foe; 747 phy->test.last_snr = snr; 748 #endif 749 750 dev_kfree_skb(skb); 751 } 752 753 static void 754 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 755 struct sk_buff *skb) 756 { 757 #ifdef CONFIG_NL80211_TESTMODE 758 struct mt76_testmode_data *td = &phy->mt76->test; 759 const struct ieee80211_rate *r; 760 u8 bw, mode, nss = td->tx_rate_nss; 761 u8 rate_idx = td->tx_rate_idx; 762 u16 rateval = 0; 763 u32 val; 764 bool cck = false; 765 int band; 766 767 if (skb != phy->mt76->test.tx_skb) 768 return; 769 770 switch (td->tx_rate_mode) { 771 case MT76_TM_TX_MODE_HT: 772 nss = 1 + (rate_idx >> 3); 773 mode = MT_PHY_TYPE_HT; 774 break; 775 case MT76_TM_TX_MODE_VHT: 776 mode = MT_PHY_TYPE_VHT; 777 break; 778 case MT76_TM_TX_MODE_HE_SU: 779 mode = MT_PHY_TYPE_HE_SU; 780 break; 781 case MT76_TM_TX_MODE_HE_EXT_SU: 782 mode = MT_PHY_TYPE_HE_EXT_SU; 783 break; 784 case MT76_TM_TX_MODE_HE_TB: 785 mode = MT_PHY_TYPE_HE_TB; 786 break; 787 case MT76_TM_TX_MODE_HE_MU: 788 mode = MT_PHY_TYPE_HE_MU; 789 break; 790 case MT76_TM_TX_MODE_CCK: 791 cck = true; 792 fallthrough; 793 case MT76_TM_TX_MODE_OFDM: 794 band = phy->mt76->chandef.chan->band; 795 if (band == NL80211_BAND_2GHZ && !cck) 796 rate_idx += 4; 797 798 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 799 val = cck ? r->hw_value_short : r->hw_value; 800 801 mode = val >> 8; 802 rate_idx = val & 0xff; 803 break; 804 default: 805 mode = MT_PHY_TYPE_OFDM; 806 break; 807 } 808 809 switch (phy->mt76->chandef.width) { 810 case NL80211_CHAN_WIDTH_40: 811 bw = 1; 812 break; 813 case NL80211_CHAN_WIDTH_80: 814 bw = 2; 815 break; 816 case NL80211_CHAN_WIDTH_80P80: 817 case NL80211_CHAN_WIDTH_160: 818 bw = 3; 819 break; 820 default: 821 bw = 0; 822 break; 823 } 824 825 if (td->tx_rate_stbc && nss == 1) { 826 nss++; 827 rateval |= MT_TX_RATE_STBC; 828 } 829 830 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 831 FIELD_PREP(MT_TX_RATE_MODE, mode) | 832 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 833 834 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 835 836 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 837 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 838 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 839 840 val = MT_TXD6_FIXED_BW | 841 FIELD_PREP(MT_TXD6_BW, bw) | 842 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 843 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 844 845 /* for HE_SU/HE_EXT_SU PPDU 846 * - 1x, 2x, 4x LTF + 0.8us GI 847 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 848 * for HE_MU PPDU 849 * - 2x, 4x LTF + 0.8us GI 850 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 851 * for HE_TB PPDU 852 * - 1x, 2x LTF + 1.6us GI 853 * - 4x LTF + 3.2us GI 854 */ 855 if (mode >= MT_PHY_TYPE_HE_SU) 856 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 857 858 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 859 val |= MT_TXD6_LDPC; 860 861 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 862 txwi[6] |= cpu_to_le32(val); 863 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 864 phy->test.spe_idx)); 865 #endif 866 } 867 868 static void 869 mt7915_mac_write_txwi_8023(struct mt7915_dev *dev, __le32 *txwi, 870 struct sk_buff *skb, struct mt76_wcid *wcid) 871 { 872 873 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 874 u8 fc_type, fc_stype; 875 bool wmm = false; 876 u32 val; 877 878 if (wcid->sta) { 879 struct ieee80211_sta *sta; 880 881 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); 882 wmm = sta->wme; 883 } 884 885 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | 886 FIELD_PREP(MT_TXD1_TID, tid); 887 888 if (be16_to_cpu(skb->protocol) >= ETH_P_802_3_MIN) 889 val |= MT_TXD1_ETH_802_3; 890 891 txwi[1] |= cpu_to_le32(val); 892 893 fc_type = IEEE80211_FTYPE_DATA >> 2; 894 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; 895 896 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 897 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); 898 899 txwi[2] |= cpu_to_le32(val); 900 901 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 902 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 903 txwi[7] |= cpu_to_le32(val); 904 } 905 906 static void 907 mt7915_mac_write_txwi_80211(struct mt7915_dev *dev, __le32 *txwi, 908 struct sk_buff *skb, struct ieee80211_key_conf *key, 909 bool *mcast) 910 { 911 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 912 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 913 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 914 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 915 __le16 fc = hdr->frame_control; 916 u8 fc_type, fc_stype; 917 u32 val; 918 919 *mcast = is_multicast_ether_addr(hdr->addr1); 920 921 if (ieee80211_is_action(fc) && 922 mgmt->u.action.category == WLAN_CATEGORY_BACK && 923 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 924 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab); 925 926 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA); 927 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK; 928 } else if (ieee80211_is_back_req(hdr->frame_control)) { 929 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr; 930 u16 control = le16_to_cpu(bar->control); 931 932 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control); 933 } 934 935 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 936 FIELD_PREP(MT_TXD1_HDR_INFO, 937 ieee80211_get_hdrlen_from_skb(skb) / 2) | 938 FIELD_PREP(MT_TXD1_TID, tid); 939 txwi[1] |= cpu_to_le32(val); 940 941 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 942 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 943 944 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 945 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 946 FIELD_PREP(MT_TXD2_MULTICAST, *mcast); 947 948 if (key && *mcast && ieee80211_is_robust_mgmt_frame(skb) && 949 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 950 val |= MT_TXD2_BIP; 951 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); 952 } 953 954 if (!ieee80211_is_data(fc) || *mcast || 955 info->flags & IEEE80211_TX_CTL_USE_MINRATE) 956 val |= MT_TXD2_FIX_RATE; 957 958 txwi[2] |= cpu_to_le32(val); 959 960 if (ieee80211_is_beacon(fc)) { 961 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); 962 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); 963 } 964 965 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 966 u16 seqno = le16_to_cpu(hdr->seq_ctrl); 967 968 if (ieee80211_is_back_req(hdr->frame_control)) { 969 struct ieee80211_bar *bar; 970 971 bar = (struct ieee80211_bar *)skb->data; 972 seqno = le16_to_cpu(bar->start_seq_num); 973 } 974 975 val = MT_TXD3_SN_VALID | 976 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 977 txwi[3] |= cpu_to_le32(val); 978 } 979 980 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 981 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype); 982 txwi[7] |= cpu_to_le32(val); 983 } 984 985 static u16 986 mt7915_mac_tx_rate_val(struct mt76_phy *mphy, struct ieee80211_vif *vif, 987 bool beacon, bool mcast) 988 { 989 u8 mode = 0, band = mphy->chandef.chan->band; 990 int rateidx = 0, mcast_rate; 991 992 if (beacon) { 993 struct cfg80211_bitrate_mask *mask; 994 995 mask = &vif->bss_conf.beacon_tx_rate; 996 if (hweight16(mask->control[band].he_mcs[0]) == 1) { 997 rateidx = ffs(mask->control[band].he_mcs[0]) - 1; 998 mode = MT_PHY_TYPE_HE_SU; 999 goto out; 1000 } else if (hweight16(mask->control[band].vht_mcs[0]) == 1) { 1001 rateidx = ffs(mask->control[band].vht_mcs[0]) - 1; 1002 mode = MT_PHY_TYPE_VHT; 1003 goto out; 1004 } else if (hweight8(mask->control[band].ht_mcs[0]) == 1) { 1005 rateidx = ffs(mask->control[band].ht_mcs[0]) - 1; 1006 mode = MT_PHY_TYPE_HT; 1007 goto out; 1008 } else if (hweight32(mask->control[band].legacy) == 1) { 1009 rateidx = ffs(mask->control[band].legacy) - 1; 1010 goto legacy; 1011 } 1012 } 1013 1014 mcast_rate = vif->bss_conf.mcast_rate[band]; 1015 if (mcast && mcast_rate > 0) 1016 rateidx = mcast_rate - 1; 1017 else 1018 rateidx = ffs(vif->bss_conf.basic_rates) - 1; 1019 1020 legacy: 1021 rateidx = mt76_calculate_default_rate(mphy, rateidx); 1022 mode = rateidx >> 8; 1023 rateidx &= GENMASK(7, 0); 1024 1025 out: 1026 return FIELD_PREP(MT_TX_RATE_IDX, rateidx) | 1027 FIELD_PREP(MT_TX_RATE_MODE, mode); 1028 } 1029 1030 void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, 1031 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 1032 struct ieee80211_key_conf *key, bool beacon) 1033 { 1034 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1035 struct ieee80211_vif *vif = info->control.vif; 1036 struct mt76_phy *mphy = &dev->mphy; 1037 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY; 1038 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 1039 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1040 bool mcast = false; 1041 u16 tx_count = 15; 1042 u32 val; 1043 1044 if (vif) { 1045 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 1046 1047 omac_idx = mvif->omac_idx; 1048 wmm_idx = mvif->wmm_idx; 1049 } 1050 1051 if (ext_phy && dev->mt76.phy2) 1052 mphy = dev->mt76.phy2; 1053 1054 if (beacon) { 1055 p_fmt = MT_TX_TYPE_FW; 1056 q_idx = MT_LMAC_BCN0; 1057 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 1058 p_fmt = MT_TX_TYPE_CT; 1059 q_idx = MT_LMAC_ALTX0; 1060 } else { 1061 p_fmt = MT_TX_TYPE_CT; 1062 q_idx = wmm_idx * MT7915_MAX_WMM_SETS + 1063 mt7915_lmac_mapping(dev, skb_get_queue_mapping(skb)); 1064 } 1065 1066 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 1067 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | 1068 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 1069 txwi[0] = cpu_to_le32(val); 1070 1071 val = MT_TXD1_LONG_FORMAT | MT_TXD1_VTA | 1072 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 1073 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 1074 1075 if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) 1076 val |= MT_TXD1_TGID; 1077 1078 txwi[1] = cpu_to_le32(val); 1079 1080 txwi[2] = 0; 1081 1082 val = MT_TXD3_SW_POWER_MGMT | 1083 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 1084 if (key) 1085 val |= MT_TXD3_PROTECT_FRAME; 1086 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1087 val |= MT_TXD3_NO_ACK; 1088 1089 txwi[3] = cpu_to_le32(val); 1090 txwi[4] = 0; 1091 1092 val = FIELD_PREP(MT_TXD5_PID, pid); 1093 if (pid >= MT_PACKET_ID_FIRST) 1094 val |= MT_TXD5_TX_STATUS_HOST; 1095 txwi[5] = cpu_to_le32(val); 1096 1097 txwi[6] = 0; 1098 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0; 1099 1100 if (is_8023) 1101 mt7915_mac_write_txwi_8023(dev, txwi, skb, wcid); 1102 else 1103 mt7915_mac_write_txwi_80211(dev, txwi, skb, key, &mcast); 1104 1105 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) { 1106 u16 rate = mt7915_mac_tx_rate_val(mphy, vif, beacon, mcast); 1107 1108 /* hardware won't add HTC for mgmt/ctrl frame */ 1109 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); 1110 1111 val = MT_TXD6_FIXED_BW | 1112 FIELD_PREP(MT_TXD6_TX_RATE, rate); 1113 txwi[6] |= cpu_to_le32(val); 1114 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 1115 } 1116 1117 if (mt76_testmode_enabled(mphy)) 1118 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 1119 } 1120 1121 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1122 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1123 struct ieee80211_sta *sta, 1124 struct mt76_tx_info *tx_info) 1125 { 1126 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 1127 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1128 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1129 struct ieee80211_key_conf *key = info->control.hw_key; 1130 struct ieee80211_vif *vif = info->control.vif; 1131 struct mt76_txwi_cache *t; 1132 struct mt7915_txp *txp; 1133 int id, i, nbuf = tx_info->nbuf - 1; 1134 u8 *txwi = (u8 *)txwi_ptr; 1135 int pid; 1136 1137 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 1138 return -EINVAL; 1139 1140 if (!wcid) 1141 wcid = &dev->mt76.global_wcid; 1142 1143 if (sta) { 1144 struct mt7915_sta *msta; 1145 1146 msta = (struct mt7915_sta *)sta->drv_priv; 1147 1148 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 1149 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 1150 msta->jiffies = jiffies; 1151 } 1152 } 1153 1154 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 1155 t->skb = tx_info->skb; 1156 1157 id = mt76_token_consume(mdev, &t); 1158 if (id < 0) 1159 return id; 1160 1161 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1162 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, pid, key, 1163 false); 1164 1165 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE); 1166 for (i = 0; i < nbuf; i++) { 1167 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1168 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 1169 } 1170 txp->nbuf = nbuf; 1171 1172 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 1173 1174 if (!key) 1175 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1176 1177 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 1178 ieee80211_is_mgmt(hdr->frame_control)) 1179 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1180 1181 if (vif) { 1182 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 1183 1184 txp->bss_idx = mvif->idx; 1185 } 1186 1187 txp->token = cpu_to_le16(id); 1188 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 1189 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 1190 else 1191 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 1192 tx_info->skb = DMA_DUMMY_DATA; 1193 1194 /* pass partial skb header to fw */ 1195 tx_info->buf[1].len = MT_CT_PARSE_LEN; 1196 tx_info->buf[1].skip_unmap = true; 1197 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 1198 1199 return 0; 1200 } 1201 1202 static void 1203 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) 1204 { 1205 struct mt7915_sta *msta; 1206 u16 fc, tid; 1207 u32 val; 1208 1209 if (!sta || !sta->ht_cap.ht_supported) 1210 return; 1211 1212 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1])); 1213 if (tid >= 6) /* skip VO queue */ 1214 return; 1215 1216 val = le32_to_cpu(txwi[2]); 1217 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | 1218 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; 1219 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) 1220 return; 1221 1222 msta = (struct mt7915_sta *)sta->drv_priv; 1223 if (!test_and_set_bit(tid, &msta->ampdu_state)) 1224 ieee80211_start_tx_ba_session(sta, tid, 0); 1225 } 1226 1227 static void 1228 mt7915_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1229 { 1230 struct mt7915_txp *txp; 1231 int i; 1232 1233 txp = mt7915_txwi_to_txp(dev, t); 1234 for (i = 0; i < txp->nbuf; i++) 1235 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), 1236 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); 1237 } 1238 1239 static void 1240 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t, 1241 struct ieee80211_sta *sta, struct list_head *free_list) 1242 { 1243 struct mt76_dev *mdev = &dev->mt76; 1244 struct mt76_wcid *wcid; 1245 __le32 *txwi; 1246 u16 wcid_idx; 1247 1248 mt7915_txp_skb_unmap(mdev, t); 1249 if (!t->skb) 1250 goto out; 1251 1252 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1253 if (sta) { 1254 wcid = (struct mt76_wcid *)sta->drv_priv; 1255 wcid_idx = wcid->idx; 1256 1257 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1258 mt7915_tx_check_aggr(sta, txwi); 1259 } else { 1260 wcid_idx = FIELD_GET(MT_TXD1_WLAN_IDX, le32_to_cpu(txwi[1])); 1261 } 1262 1263 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); 1264 1265 out: 1266 t->skb = NULL; 1267 mt76_put_txwi(mdev, t); 1268 } 1269 1270 static void 1271 mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb) 1272 { 1273 struct mt7915_tx_free *free = (struct mt7915_tx_free *)skb->data; 1274 struct mt76_dev *mdev = &dev->mt76; 1275 struct mt76_phy *mphy_ext = mdev->phy2; 1276 struct mt76_txwi_cache *txwi; 1277 struct ieee80211_sta *sta = NULL; 1278 LIST_HEAD(free_list); 1279 struct sk_buff *tmp; 1280 u8 i, count; 1281 bool wake = false; 1282 1283 /* clean DMA queues and unmap buffers first */ 1284 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1285 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1286 if (mphy_ext) { 1287 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 1288 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 1289 } 1290 1291 /* 1292 * TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE, 1293 * to the time ack is received or dropped by hw (air + hw queue time). 1294 * Should avoid accessing WTBL to get Tx airtime, and use it instead. 1295 */ 1296 count = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl)); 1297 for (i = 0; i < count; i++) { 1298 u32 msdu, info = le32_to_cpu(free->info[i]); 1299 1300 /* 1301 * 1'b1: new wcid pair. 1302 * 1'b0: msdu_id with the same 'wcid pair' as above. 1303 */ 1304 if (info & MT_TX_FREE_PAIR) { 1305 struct mt7915_sta *msta; 1306 struct mt76_wcid *wcid; 1307 u16 idx; 1308 1309 count++; 1310 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 1311 wcid = rcu_dereference(dev->mt76.wcid[idx]); 1312 sta = wcid_to_sta(wcid); 1313 if (!sta) 1314 continue; 1315 1316 msta = container_of(wcid, struct mt7915_sta, wcid); 1317 spin_lock_bh(&dev->sta_poll_lock); 1318 if (list_empty(&msta->poll_list)) 1319 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1320 spin_unlock_bh(&dev->sta_poll_lock); 1321 continue; 1322 } 1323 1324 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 1325 txwi = mt76_token_release(mdev, msdu, &wake); 1326 if (!txwi) 1327 continue; 1328 1329 mt7915_txwi_free(dev, txwi, sta, &free_list); 1330 } 1331 1332 mt7915_mac_sta_poll(dev); 1333 1334 if (wake) 1335 mt76_set_tx_blocked(&dev->mt76, false); 1336 1337 mt76_worker_schedule(&dev->mt76.tx_worker); 1338 1339 napi_consume_skb(skb, 1); 1340 1341 list_for_each_entry_safe(skb, tmp, &free_list, list) { 1342 skb_list_del_init(skb); 1343 napi_consume_skb(skb, 1); 1344 } 1345 } 1346 1347 static bool 1348 mt7915_mac_add_txs_skb(struct mt7915_dev *dev, struct mt76_wcid *wcid, int pid, 1349 __le32 *txs_data, struct mt76_sta_stats *stats) 1350 { 1351 struct ieee80211_supported_band *sband; 1352 struct mt76_dev *mdev = &dev->mt76; 1353 struct mt76_phy *mphy; 1354 struct ieee80211_tx_info *info; 1355 struct sk_buff_head list; 1356 struct rate_info rate = {}; 1357 struct sk_buff *skb; 1358 bool cck = false; 1359 u32 txrate, txs, mode; 1360 1361 mt76_tx_status_lock(mdev, &list); 1362 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); 1363 if (!skb) 1364 goto out_no_skb; 1365 1366 txs = le32_to_cpu(txs_data[0]); 1367 1368 info = IEEE80211_SKB_CB(skb); 1369 if (!(txs & MT_TXS0_ACK_ERROR_MASK)) 1370 info->flags |= IEEE80211_TX_STAT_ACK; 1371 1372 info->status.ampdu_len = 1; 1373 info->status.ampdu_ack_len = !!(info->flags & 1374 IEEE80211_TX_STAT_ACK); 1375 1376 info->status.rates[0].idx = -1; 1377 1378 txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1379 1380 rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); 1381 rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; 1382 1383 if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) 1384 stats->tx_nss[rate.nss - 1]++; 1385 if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) 1386 stats->tx_mcs[rate.mcs]++; 1387 1388 mode = FIELD_GET(MT_TX_RATE_MODE, txrate); 1389 switch (mode) { 1390 case MT_PHY_TYPE_CCK: 1391 cck = true; 1392 fallthrough; 1393 case MT_PHY_TYPE_OFDM: 1394 mphy = &dev->mphy; 1395 if (wcid->ext_phy && dev->mt76.phy2) 1396 mphy = dev->mt76.phy2; 1397 1398 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1399 sband = &mphy->sband_5g.sband; 1400 else 1401 sband = &mphy->sband_2g.sband; 1402 1403 rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); 1404 rate.legacy = sband->bitrates[rate.mcs].bitrate; 1405 break; 1406 case MT_PHY_TYPE_HT: 1407 case MT_PHY_TYPE_HT_GF: 1408 rate.mcs += (rate.nss - 1) * 8; 1409 if (rate.mcs > 31) 1410 goto out; 1411 1412 rate.flags = RATE_INFO_FLAGS_MCS; 1413 if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) 1414 rate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1415 break; 1416 case MT_PHY_TYPE_VHT: 1417 if (rate.mcs > 9) 1418 goto out; 1419 1420 rate.flags = RATE_INFO_FLAGS_VHT_MCS; 1421 break; 1422 case MT_PHY_TYPE_HE_SU: 1423 case MT_PHY_TYPE_HE_EXT_SU: 1424 case MT_PHY_TYPE_HE_TB: 1425 case MT_PHY_TYPE_HE_MU: 1426 if (rate.mcs > 11) 1427 goto out; 1428 1429 rate.he_gi = wcid->rate.he_gi; 1430 rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); 1431 rate.flags = RATE_INFO_FLAGS_HE_MCS; 1432 break; 1433 default: 1434 goto out; 1435 } 1436 1437 stats->tx_mode[mode]++; 1438 1439 switch (FIELD_GET(MT_TXS0_BW, txs)) { 1440 case IEEE80211_STA_RX_BW_160: 1441 rate.bw = RATE_INFO_BW_160; 1442 stats->tx_bw[3]++; 1443 break; 1444 case IEEE80211_STA_RX_BW_80: 1445 rate.bw = RATE_INFO_BW_80; 1446 stats->tx_bw[2]++; 1447 break; 1448 case IEEE80211_STA_RX_BW_40: 1449 rate.bw = RATE_INFO_BW_40; 1450 stats->tx_bw[1]++; 1451 break; 1452 default: 1453 rate.bw = RATE_INFO_BW_20; 1454 stats->tx_bw[0]++; 1455 break; 1456 } 1457 wcid->rate = rate; 1458 1459 out: 1460 mt76_tx_status_skb_done(mdev, skb, &list); 1461 1462 out_no_skb: 1463 mt76_tx_status_unlock(mdev, &list); 1464 1465 return !!skb; 1466 } 1467 1468 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1469 { 1470 struct mt7915_sta *msta = NULL; 1471 struct mt76_wcid *wcid; 1472 __le32 *txs_data = data; 1473 u16 wcidx; 1474 u32 txs; 1475 u8 pid; 1476 1477 txs = le32_to_cpu(txs_data[0]); 1478 if (FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1) 1479 return; 1480 1481 txs = le32_to_cpu(txs_data[2]); 1482 wcidx = FIELD_GET(MT_TXS2_WCID, txs); 1483 1484 txs = le32_to_cpu(txs_data[3]); 1485 pid = FIELD_GET(MT_TXS3_PID, txs); 1486 1487 if (pid < MT_PACKET_ID_FIRST) 1488 return; 1489 1490 if (wcidx >= MT7915_WTBL_SIZE) 1491 return; 1492 1493 rcu_read_lock(); 1494 1495 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1496 if (!wcid) 1497 goto out; 1498 1499 msta = container_of(wcid, struct mt7915_sta, wcid); 1500 1501 mt7915_mac_add_txs_skb(dev, wcid, pid, txs_data, &msta->stats); 1502 1503 if (!wcid->sta) 1504 goto out; 1505 1506 spin_lock_bh(&dev->sta_poll_lock); 1507 if (list_empty(&msta->poll_list)) 1508 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1509 spin_unlock_bh(&dev->sta_poll_lock); 1510 1511 out: 1512 rcu_read_unlock(); 1513 } 1514 1515 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1516 struct sk_buff *skb) 1517 { 1518 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1519 __le32 *rxd = (__le32 *)skb->data; 1520 __le32 *end = (__le32 *)&skb->data[skb->len]; 1521 enum rx_pkt_type type; 1522 1523 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1524 1525 switch (type) { 1526 case PKT_TYPE_TXRX_NOTIFY: 1527 mt7915_mac_tx_free(dev, skb); 1528 break; 1529 case PKT_TYPE_RX_EVENT: 1530 mt7915_mcu_rx_event(dev, skb); 1531 break; 1532 case PKT_TYPE_TXRXV: 1533 mt7915_mac_fill_rx_vector(dev, skb); 1534 break; 1535 case PKT_TYPE_TXS: 1536 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1537 mt7915_mac_add_txs(dev, rxd); 1538 dev_kfree_skb(skb); 1539 break; 1540 case PKT_TYPE_NORMAL: 1541 if (!mt7915_mac_fill_rx(dev, skb)) { 1542 mt76_rx(&dev->mt76, q, skb); 1543 return; 1544 } 1545 fallthrough; 1546 default: 1547 dev_kfree_skb(skb); 1548 break; 1549 } 1550 } 1551 1552 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 1553 { 1554 if (!e->txwi) { 1555 dev_kfree_skb_any(e->skb); 1556 return; 1557 } 1558 1559 /* error path */ 1560 if (e->skb == DMA_DUMMY_DATA) { 1561 struct mt76_txwi_cache *t; 1562 struct mt7915_txp *txp; 1563 1564 txp = mt7915_txwi_to_txp(mdev, e->txwi); 1565 t = mt76_token_put(mdev, le16_to_cpu(txp->token)); 1566 e->skb = t ? t->skb : NULL; 1567 } 1568 1569 if (e->skb) 1570 mt76_tx_complete_skb(mdev, e->wcid, e->skb); 1571 } 1572 1573 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1574 { 1575 struct mt7915_dev *dev = phy->dev; 1576 bool ext_phy = phy != &dev->phy; 1577 u32 reg = MT_WF_PHY_RX_CTRL1(ext_phy); 1578 1579 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1580 mt76_set(dev, reg, BIT(11) | BIT(9)); 1581 } 1582 1583 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1584 { 1585 struct mt7915_dev *dev = phy->dev; 1586 bool ext_phy = phy != &dev->phy; 1587 int i; 1588 1589 for (i = 0; i < 4; i++) { 1590 mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 1591 mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i)); 1592 } 1593 1594 if (ext_phy) { 1595 dev->mt76.phy2->survey_time = ktime_get_boottime(); 1596 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2; 1597 } else { 1598 dev->mt76.phy.survey_time = ktime_get_boottime(); 1599 i = 0; 1600 } 1601 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2); 1602 1603 /* reset airtime counters */ 1604 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(ext_phy), 1605 MT_WF_RMAC_MIB_RXTIME_CLR); 1606 1607 mt7915_mcu_get_chan_mib_info(phy, true); 1608 } 1609 1610 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1611 { 1612 s16 coverage_class = phy->coverage_class; 1613 struct mt7915_dev *dev = phy->dev; 1614 bool ext_phy = phy != &dev->phy; 1615 u32 val, reg_offset; 1616 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1617 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1618 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1619 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1620 int offset; 1621 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 1622 1623 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1624 return; 1625 1626 if (ext_phy) { 1627 coverage_class = max_t(s16, dev->phy.coverage_class, 1628 coverage_class); 1629 } else { 1630 struct mt7915_phy *phy_ext = mt7915_ext_phy(dev); 1631 1632 if (phy_ext) 1633 coverage_class = max_t(s16, phy_ext->coverage_class, 1634 coverage_class); 1635 } 1636 mt76_set(dev, MT_ARB_SCR(ext_phy), 1637 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1638 udelay(1); 1639 1640 offset = 3 * coverage_class; 1641 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1642 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1643 1644 mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset); 1645 mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset); 1646 mt76_wr(dev, MT_TMAC_ICR0(ext_phy), 1647 FIELD_PREP(MT_IFS_EIFS_OFDM, is_5ghz ? 84 : 78) | 1648 FIELD_PREP(MT_IFS_RIFS, 2) | 1649 FIELD_PREP(MT_IFS_SIFS, 10) | 1650 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1651 1652 mt76_wr(dev, MT_TMAC_ICR1(ext_phy), 1653 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1654 1655 if (phy->slottime < 20 || is_5ghz) 1656 val = MT7915_CFEND_RATE_DEFAULT; 1657 else 1658 val = MT7915_CFEND_RATE_11B; 1659 1660 mt76_rmw_field(dev, MT_AGG_ACR0(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 1661 mt76_clear(dev, MT_ARB_SCR(ext_phy), 1662 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1663 } 1664 1665 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy) 1666 { 1667 mt76_set(dev, MT_WF_PHY_RXTD12(ext_phy), 1668 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1669 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1670 1671 mt76_set(dev, MT_WF_PHY_RX_CTRL1(ext_phy), 1672 FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1673 } 1674 1675 static u8 1676 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1677 { 1678 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1679 struct mt7915_dev *dev = phy->dev; 1680 u32 val, sum = 0, n = 0; 1681 int nss, i; 1682 1683 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1684 u32 reg = MT_WF_IRPI(nss + (idx << dev->dbdc_support)); 1685 1686 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1687 val = mt76_rr(dev, reg); 1688 sum += val * nf_power[i]; 1689 n += val; 1690 } 1691 } 1692 1693 if (!n) 1694 return 0; 1695 1696 return sum / n; 1697 } 1698 1699 void mt7915_update_channel(struct mt76_phy *mphy) 1700 { 1701 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv; 1702 struct mt76_channel_state *state = mphy->chan_state; 1703 bool ext_phy = phy != &phy->dev->phy; 1704 int nf; 1705 1706 mt7915_mcu_get_chan_mib_info(phy, false); 1707 1708 nf = mt7915_phy_get_nf(phy, ext_phy); 1709 if (!phy->noise) 1710 phy->noise = nf << 4; 1711 else if (nf) 1712 phy->noise += nf - (phy->noise >> 4); 1713 1714 state->noise = -(phy->noise >> 4); 1715 } 1716 1717 static bool 1718 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1719 { 1720 bool ret; 1721 1722 ret = wait_event_timeout(dev->reset_wait, 1723 (READ_ONCE(dev->reset_state) & state), 1724 MT7915_RESET_TIMEOUT); 1725 1726 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1727 return ret; 1728 } 1729 1730 static void 1731 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1732 { 1733 struct ieee80211_hw *hw = priv; 1734 1735 switch (vif->type) { 1736 case NL80211_IFTYPE_MESH_POINT: 1737 case NL80211_IFTYPE_ADHOC: 1738 case NL80211_IFTYPE_AP: 1739 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); 1740 break; 1741 default: 1742 break; 1743 } 1744 } 1745 1746 static void 1747 mt7915_update_beacons(struct mt7915_dev *dev) 1748 { 1749 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1750 IEEE80211_IFACE_ITER_RESUME_ALL, 1751 mt7915_update_vif_beacon, dev->mt76.hw); 1752 1753 if (!dev->mt76.phy2) 1754 return; 1755 1756 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw, 1757 IEEE80211_IFACE_ITER_RESUME_ALL, 1758 mt7915_update_vif_beacon, dev->mt76.phy2->hw); 1759 } 1760 1761 static void 1762 mt7915_dma_reset(struct mt7915_dev *dev) 1763 { 1764 struct mt76_phy *mphy_ext = dev->mt76.phy2; 1765 u32 hif1_ofs = MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE; 1766 int i; 1767 1768 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 1769 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1770 mt76_clear(dev, MT_WFDMA1_GLO_CFG, 1771 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 1772 if (dev->hif2) { 1773 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1774 (MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1775 MT_WFDMA0_GLO_CFG_RX_DMA_EN)); 1776 mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 1777 (MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1778 MT_WFDMA1_GLO_CFG_RX_DMA_EN)); 1779 } 1780 1781 usleep_range(1000, 2000); 1782 1783 for (i = 0; i < __MT_TXQ_MAX; i++) { 1784 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 1785 if (mphy_ext) 1786 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true); 1787 } 1788 1789 for (i = 0; i < __MT_MCUQ_MAX; i++) 1790 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); 1791 1792 mt76_for_each_q_rx(&dev->mt76, i) 1793 mt76_queue_rx_reset(dev, i); 1794 1795 mt76_tx_status_check(&dev->mt76, true); 1796 1797 /* re-init prefetch settings after reset */ 1798 mt7915_dma_prefetch(dev); 1799 1800 mt76_set(dev, MT_WFDMA0_GLO_CFG, 1801 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 1802 mt76_set(dev, MT_WFDMA1_GLO_CFG, 1803 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN | 1804 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 1805 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 1806 if (dev->hif2) { 1807 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 1808 (MT_WFDMA0_GLO_CFG_TX_DMA_EN | 1809 MT_WFDMA0_GLO_CFG_RX_DMA_EN)); 1810 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 1811 (MT_WFDMA1_GLO_CFG_TX_DMA_EN | 1812 MT_WFDMA1_GLO_CFG_RX_DMA_EN | 1813 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 1814 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO)); 1815 } 1816 } 1817 1818 void mt7915_tx_token_put(struct mt7915_dev *dev) 1819 { 1820 struct mt76_txwi_cache *txwi; 1821 int id; 1822 1823 spin_lock_bh(&dev->mt76.token_lock); 1824 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1825 mt7915_txwi_free(dev, txwi, NULL, NULL); 1826 dev->mt76.token_count--; 1827 } 1828 spin_unlock_bh(&dev->mt76.token_lock); 1829 idr_destroy(&dev->mt76.token); 1830 } 1831 1832 /* system error recovery */ 1833 void mt7915_mac_reset_work(struct work_struct *work) 1834 { 1835 struct mt7915_phy *phy2; 1836 struct mt76_phy *ext_phy; 1837 struct mt7915_dev *dev; 1838 1839 dev = container_of(work, struct mt7915_dev, reset_work); 1840 ext_phy = dev->mt76.phy2; 1841 phy2 = ext_phy ? ext_phy->priv : NULL; 1842 1843 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA)) 1844 return; 1845 1846 ieee80211_stop_queues(mt76_hw(dev)); 1847 if (ext_phy) 1848 ieee80211_stop_queues(ext_phy->hw); 1849 1850 set_bit(MT76_RESET, &dev->mphy.state); 1851 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1852 wake_up(&dev->mt76.mcu.wait); 1853 cancel_delayed_work_sync(&dev->mphy.mac_work); 1854 if (phy2) { 1855 set_bit(MT76_RESET, &phy2->mt76->state); 1856 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1857 } 1858 mt76_worker_disable(&dev->mt76.tx_worker); 1859 napi_disable(&dev->mt76.napi[0]); 1860 napi_disable(&dev->mt76.napi[1]); 1861 napi_disable(&dev->mt76.napi[2]); 1862 napi_disable(&dev->mt76.tx_napi); 1863 1864 mutex_lock(&dev->mt76.mutex); 1865 1866 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1867 1868 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1869 mt7915_dma_reset(dev); 1870 1871 mt7915_tx_token_put(dev); 1872 idr_init(&dev->mt76.token); 1873 1874 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1875 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1876 } 1877 1878 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1879 clear_bit(MT76_RESET, &dev->mphy.state); 1880 if (phy2) 1881 clear_bit(MT76_RESET, &phy2->mt76->state); 1882 1883 local_bh_disable(); 1884 napi_enable(&dev->mt76.napi[0]); 1885 napi_schedule(&dev->mt76.napi[0]); 1886 1887 napi_enable(&dev->mt76.napi[1]); 1888 napi_schedule(&dev->mt76.napi[1]); 1889 1890 napi_enable(&dev->mt76.napi[2]); 1891 napi_schedule(&dev->mt76.napi[2]); 1892 local_bh_enable(); 1893 1894 tasklet_schedule(&dev->irq_tasklet); 1895 1896 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1897 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1898 1899 mt76_worker_enable(&dev->mt76.tx_worker); 1900 1901 napi_enable(&dev->mt76.tx_napi); 1902 napi_schedule(&dev->mt76.tx_napi); 1903 1904 ieee80211_wake_queues(mt76_hw(dev)); 1905 if (ext_phy) 1906 ieee80211_wake_queues(ext_phy->hw); 1907 1908 mutex_unlock(&dev->mt76.mutex); 1909 1910 mt7915_update_beacons(dev); 1911 1912 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1913 MT7915_WATCHDOG_TIME); 1914 if (phy2) 1915 ieee80211_queue_delayed_work(ext_phy->hw, 1916 &phy2->mt76->mac_work, 1917 MT7915_WATCHDOG_TIME); 1918 } 1919 1920 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1921 { 1922 struct mt7915_dev *dev = phy->dev; 1923 struct mib_stats *mib = &phy->mib; 1924 bool ext_phy = phy != &dev->phy; 1925 int i, aggr0, aggr1, cnt; 1926 1927 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 1928 MT_MIB_SDR3_FCS_ERR_MASK); 1929 1930 cnt = mt76_rr(dev, MT_MIB_SDR4(ext_phy)); 1931 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1932 1933 cnt = mt76_rr(dev, MT_MIB_SDR5(ext_phy)); 1934 mib->rx_mpdu_cnt += cnt; 1935 1936 cnt = mt76_rr(dev, MT_MIB_SDR6(ext_phy)); 1937 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1938 1939 cnt = mt76_rr(dev, MT_MIB_SDR7(ext_phy)); 1940 mib->rx_vector_mismatch_cnt += FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1941 1942 cnt = mt76_rr(dev, MT_MIB_SDR8(ext_phy)); 1943 mib->rx_delimiter_fail_cnt += FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1944 1945 cnt = mt76_rr(dev, MT_MIB_SDR11(ext_phy)); 1946 mib->rx_len_mismatch_cnt += FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1947 1948 cnt = mt76_rr(dev, MT_MIB_SDR12(ext_phy)); 1949 mib->tx_ampdu_cnt += cnt; 1950 1951 cnt = mt76_rr(dev, MT_MIB_SDR13(ext_phy)); 1952 mib->tx_stop_q_empty_cnt += FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1953 1954 cnt = mt76_rr(dev, MT_MIB_SDR14(ext_phy)); 1955 mib->tx_mpdu_attempts_cnt += FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt); 1956 1957 cnt = mt76_rr(dev, MT_MIB_SDR15(ext_phy)); 1958 mib->tx_mpdu_success_cnt += FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt); 1959 1960 cnt = mt76_rr(dev, MT_MIB_SDR22(ext_phy)); 1961 mib->rx_ampdu_cnt += cnt; 1962 1963 cnt = mt76_rr(dev, MT_MIB_SDR23(ext_phy)); 1964 mib->rx_ampdu_bytes_cnt += cnt; 1965 1966 cnt = mt76_rr(dev, MT_MIB_SDR24(ext_phy)); 1967 mib->rx_ampdu_valid_subframe_cnt += FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt); 1968 1969 cnt = mt76_rr(dev, MT_MIB_SDR25(ext_phy)); 1970 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1971 1972 cnt = mt76_rr(dev, MT_MIB_SDR27(ext_phy)); 1973 mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1974 1975 cnt = mt76_rr(dev, MT_MIB_SDR28(ext_phy)); 1976 mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1977 1978 cnt = mt76_rr(dev, MT_MIB_SDR29(ext_phy)); 1979 mib->rx_pfdrop_cnt += FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt); 1980 1981 cnt = mt76_rr(dev, MT_MIB_SDR30(ext_phy)); 1982 mib->rx_vec_queue_overflow_drop_cnt += 1983 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt); 1984 1985 cnt = mt76_rr(dev, MT_MIB_SDR31(ext_phy)); 1986 mib->rx_ba_cnt += cnt; 1987 1988 cnt = mt76_rr(dev, MT_MIB_SDR32(ext_phy)); 1989 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK, cnt); 1990 1991 cnt = mt76_rr(dev, MT_MIB_SDR33(ext_phy)); 1992 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT_MASK, cnt); 1993 1994 cnt = mt76_rr(dev, MT_MIB_SDR34(ext_phy)); 1995 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1996 1997 cnt = mt76_rr(dev, MT_MIB_DR8(ext_phy)); 1998 mib->tx_mu_mpdu_cnt += cnt; 1999 2000 cnt = mt76_rr(dev, MT_MIB_DR9(ext_phy)); 2001 mib->tx_mu_acked_mpdu_cnt += cnt; 2002 2003 cnt = mt76_rr(dev, MT_MIB_DR11(ext_phy)); 2004 mib->tx_su_acked_mpdu_cnt += cnt; 2005 2006 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(ext_phy)); 2007 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 2008 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 2009 2010 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(ext_phy)); 2011 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 2012 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 2013 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 2014 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 2015 2016 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(ext_phy)); 2017 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); 2018 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); 2019 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); 2020 2021 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(ext_phy)); 2022 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 2023 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 2024 2025 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 2026 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 2027 mib->tx_amsdu[i] += cnt; 2028 mib->tx_amsdu_cnt += cnt; 2029 } 2030 2031 aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 2032 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) { 2033 u32 val; 2034 2035 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); 2036 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 2037 mib->ack_fail_cnt += 2038 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 2039 2040 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); 2041 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 2042 mib->rts_retries_cnt += 2043 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 2044 2045 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 2046 dev->mt76.aggr_stats[aggr0++] += val & 0xffff; 2047 dev->mt76.aggr_stats[aggr0++] += val >> 16; 2048 2049 val = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i)); 2050 dev->mt76.aggr_stats[aggr1++] += val & 0xffff; 2051 dev->mt76.aggr_stats[aggr1++] += val >> 16; 2052 } 2053 } 2054 2055 void mt7915_mac_sta_rc_work(struct work_struct *work) 2056 { 2057 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 2058 struct ieee80211_sta *sta; 2059 struct ieee80211_vif *vif; 2060 struct mt7915_sta *msta; 2061 u32 changed; 2062 LIST_HEAD(list); 2063 2064 spin_lock_bh(&dev->sta_poll_lock); 2065 list_splice_init(&dev->sta_rc_list, &list); 2066 2067 while (!list_empty(&list)) { 2068 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 2069 list_del_init(&msta->rc_list); 2070 changed = msta->changed; 2071 msta->changed = 0; 2072 spin_unlock_bh(&dev->sta_poll_lock); 2073 2074 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2075 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2076 2077 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2078 IEEE80211_RC_NSS_CHANGED | 2079 IEEE80211_RC_BW_CHANGED)) 2080 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 2081 2082 if (changed & IEEE80211_RC_SMPS_CHANGED) 2083 mt7915_mcu_add_smps(dev, vif, sta); 2084 2085 spin_lock_bh(&dev->sta_poll_lock); 2086 } 2087 2088 spin_unlock_bh(&dev->sta_poll_lock); 2089 } 2090 2091 void mt7915_mac_work(struct work_struct *work) 2092 { 2093 struct mt7915_phy *phy; 2094 struct mt76_phy *mphy; 2095 2096 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2097 mac_work.work); 2098 phy = mphy->priv; 2099 2100 mutex_lock(&mphy->dev->mutex); 2101 2102 mt76_update_survey(mphy); 2103 if (++mphy->mac_work_count == 5) { 2104 mphy->mac_work_count = 0; 2105 2106 mt7915_mac_update_stats(phy); 2107 } 2108 2109 mutex_unlock(&mphy->dev->mutex); 2110 2111 mt76_tx_status_check(mphy->dev, false); 2112 2113 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2114 MT7915_WATCHDOG_TIME); 2115 } 2116 2117 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2118 { 2119 struct mt7915_dev *dev = phy->dev; 2120 2121 if (phy->rdd_state & BIT(0)) 2122 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0); 2123 if (phy->rdd_state & BIT(1)) 2124 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0); 2125 } 2126 2127 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 2128 { 2129 int err; 2130 2131 err = mt7915_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0); 2132 if (err < 0) 2133 return err; 2134 2135 return mt7915_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, MT_RX_SEL0, 1); 2136 } 2137 2138 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2139 { 2140 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2141 struct mt7915_dev *dev = phy->dev; 2142 bool ext_phy = phy != &dev->phy; 2143 int err; 2144 2145 /* start CAC */ 2146 err = mt7915_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0); 2147 if (err < 0) 2148 return err; 2149 2150 err = mt7915_dfs_start_rdd(dev, ext_phy); 2151 if (err < 0) 2152 return err; 2153 2154 phy->rdd_state |= BIT(ext_phy); 2155 2156 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2157 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2158 err = mt7915_dfs_start_rdd(dev, 1); 2159 if (err < 0) 2160 return err; 2161 2162 phy->rdd_state |= BIT(1); 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int 2169 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2170 { 2171 const struct mt7915_dfs_radar_spec *radar_specs; 2172 struct mt7915_dev *dev = phy->dev; 2173 int err, i; 2174 2175 switch (dev->mt76.region) { 2176 case NL80211_DFS_FCC: 2177 radar_specs = &fcc_radar_specs; 2178 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2179 if (err < 0) 2180 return err; 2181 break; 2182 case NL80211_DFS_ETSI: 2183 radar_specs = &etsi_radar_specs; 2184 break; 2185 case NL80211_DFS_JP: 2186 radar_specs = &jp_radar_specs; 2187 break; 2188 default: 2189 return -EINVAL; 2190 } 2191 2192 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2193 err = mt7915_mcu_set_radar_th(dev, i, 2194 &radar_specs->radar_pattern[i]); 2195 if (err < 0) 2196 return err; 2197 } 2198 2199 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2200 } 2201 2202 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2203 { 2204 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2205 struct mt7915_dev *dev = phy->dev; 2206 bool ext_phy = phy != &dev->phy; 2207 int err; 2208 2209 if (dev->mt76.region == NL80211_DFS_UNSET) { 2210 phy->dfs_state = -1; 2211 if (phy->rdd_state) 2212 goto stop; 2213 2214 return 0; 2215 } 2216 2217 if (test_bit(MT76_SCANNING, &phy->mt76->state)) 2218 return 0; 2219 2220 if (phy->dfs_state == chandef->chan->dfs_state) 2221 return 0; 2222 2223 err = mt7915_dfs_init_radar_specs(phy); 2224 if (err < 0) { 2225 phy->dfs_state = -1; 2226 goto stop; 2227 } 2228 2229 phy->dfs_state = chandef->chan->dfs_state; 2230 2231 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) { 2232 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE) 2233 return mt7915_dfs_start_radar_detector(phy); 2234 2235 return mt7915_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy, 2236 MT_RX_SEL0, 0); 2237 } 2238 2239 stop: 2240 err = mt7915_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, 2241 MT_RX_SEL0, 0); 2242 if (err < 0) 2243 return err; 2244 2245 mt7915_dfs_stop_radar_detector(phy); 2246 return 0; 2247 } 2248 2249 static int 2250 mt7915_mac_twt_duration_align(int duration) 2251 { 2252 return duration << 8; 2253 } 2254 2255 static u64 2256 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2257 struct mt7915_twt_flow *flow) 2258 { 2259 struct mt7915_twt_flow *iter, *iter_next; 2260 u32 duration = flow->duration << 8; 2261 u64 start_tsf; 2262 2263 iter = list_first_entry_or_null(&dev->twt_list, 2264 struct mt7915_twt_flow, list); 2265 if (!iter || !iter->sched || iter->start_tsf > duration) { 2266 /* add flow as first entry in the list */ 2267 list_add(&flow->list, &dev->twt_list); 2268 return 0; 2269 } 2270 2271 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2272 start_tsf = iter->start_tsf + 2273 mt7915_mac_twt_duration_align(iter->duration); 2274 if (list_is_last(&iter->list, &dev->twt_list)) 2275 break; 2276 2277 if (!iter_next->sched || 2278 iter_next->start_tsf > start_tsf + duration) { 2279 list_add(&flow->list, &iter->list); 2280 goto out; 2281 } 2282 } 2283 2284 /* add flow as last entry in the list */ 2285 list_add_tail(&flow->list, &dev->twt_list); 2286 out: 2287 return start_tsf; 2288 } 2289 2290 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2291 { 2292 struct ieee80211_twt_params *twt_agrt; 2293 u64 interval, duration; 2294 u16 mantissa; 2295 u8 exp; 2296 2297 /* only individual agreement supported */ 2298 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2299 return -EOPNOTSUPP; 2300 2301 /* only 256us unit supported */ 2302 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2303 return -EOPNOTSUPP; 2304 2305 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2306 2307 /* explicit agreement not supported */ 2308 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2309 return -EOPNOTSUPP; 2310 2311 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2312 le16_to_cpu(twt_agrt->req_type)); 2313 mantissa = le16_to_cpu(twt_agrt->mantissa); 2314 duration = twt_agrt->min_twt_dur << 8; 2315 2316 interval = (u64)mantissa << exp; 2317 if (interval < duration) 2318 return -EOPNOTSUPP; 2319 2320 return 0; 2321 } 2322 2323 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2324 struct ieee80211_sta *sta, 2325 struct ieee80211_twt_setup *twt) 2326 { 2327 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2328 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2329 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2330 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2331 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2332 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2333 struct mt7915_twt_flow *flow; 2334 int flowid, table_id; 2335 u8 exp; 2336 2337 if (mt7915_mac_check_twt_req(twt)) 2338 goto out; 2339 2340 mutex_lock(&dev->mt76.mutex); 2341 2342 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2343 goto unlock; 2344 2345 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2346 goto unlock; 2347 2348 flowid = ffs(~msta->twt.flowid_mask) - 1; 2349 le16p_replace_bits(&twt_agrt->req_type, flowid, 2350 IEEE80211_TWT_REQTYPE_FLOWID); 2351 2352 table_id = ffs(~dev->twt.table_mask) - 1; 2353 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2354 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2355 2356 flow = &msta->twt.flow[flowid]; 2357 memset(flow, 0, sizeof(*flow)); 2358 INIT_LIST_HEAD(&flow->list); 2359 flow->wcid = msta->wcid.idx; 2360 flow->table_id = table_id; 2361 flow->id = flowid; 2362 flow->duration = twt_agrt->min_twt_dur; 2363 flow->mantissa = twt_agrt->mantissa; 2364 flow->exp = exp; 2365 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2366 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2367 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2368 2369 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2370 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2371 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2372 u64 flow_tsf, curr_tsf; 2373 u32 rem; 2374 2375 flow->sched = true; 2376 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2377 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2378 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2379 flow_tsf = curr_tsf + interval - rem; 2380 twt_agrt->twt = cpu_to_le64(flow_tsf); 2381 } else { 2382 list_add_tail(&flow->list, &dev->twt_list); 2383 } 2384 flow->tsf = le64_to_cpu(twt_agrt->twt); 2385 2386 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2387 goto unlock; 2388 2389 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2390 dev->twt.table_mask |= BIT(table_id); 2391 msta->twt.flowid_mask |= BIT(flowid); 2392 dev->twt.n_agrt++; 2393 2394 unlock: 2395 mutex_unlock(&dev->mt76.mutex); 2396 out: 2397 le16p_replace_bits(&twt_agrt->req_type, setup_cmd, 2398 IEEE80211_TWT_REQTYPE_SETUP_CMD); 2399 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2400 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2401 } 2402 2403 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2404 struct mt7915_sta *msta, 2405 u8 flowid) 2406 { 2407 struct mt7915_twt_flow *flow; 2408 2409 lockdep_assert_held(&dev->mt76.mutex); 2410 2411 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2412 return; 2413 2414 if (!(msta->twt.flowid_mask & BIT(flowid))) 2415 return; 2416 2417 flow = &msta->twt.flow[flowid]; 2418 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2419 MCU_TWT_AGRT_DELETE)) 2420 return; 2421 2422 list_del_init(&flow->list); 2423 msta->twt.flowid_mask &= ~BIT(flowid); 2424 dev->twt.table_mask &= ~BIT(flow->table_id); 2425 dev->twt.n_agrt--; 2426 } 2427