1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/thermal.h> 8 #include "mt7915.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "coredump.h" 12 #include "eeprom.h" 13 14 static const struct ieee80211_iface_limit if_limits[] = { 15 { 16 .max = 1, 17 .types = BIT(NL80211_IFTYPE_ADHOC) 18 }, { 19 .max = 16, 20 .types = BIT(NL80211_IFTYPE_AP) 21 #ifdef CONFIG_MAC80211_MESH 22 | BIT(NL80211_IFTYPE_MESH_POINT) 23 #endif 24 }, { 25 .max = MT7915_MAX_INTERFACES, 26 .types = BIT(NL80211_IFTYPE_STATION) 27 } 28 }; 29 30 static const struct ieee80211_iface_combination if_comb[] = { 31 { 32 .limits = if_limits, 33 .n_limits = ARRAY_SIZE(if_limits), 34 .max_interfaces = MT7915_MAX_INTERFACES, 35 .num_different_channels = 1, 36 .beacon_int_infra_match = true, 37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 38 BIT(NL80211_CHAN_WIDTH_20) | 39 BIT(NL80211_CHAN_WIDTH_40) | 40 BIT(NL80211_CHAN_WIDTH_80) | 41 BIT(NL80211_CHAN_WIDTH_160), 42 } 43 }; 44 45 static ssize_t mt7915_thermal_temp_show(struct device *dev, 46 struct device_attribute *attr, 47 char *buf) 48 { 49 struct mt7915_phy *phy = dev_get_drvdata(dev); 50 int i = to_sensor_dev_attr(attr)->index; 51 int temperature; 52 53 switch (i) { 54 case 0: 55 temperature = mt7915_mcu_get_temperature(phy); 56 if (temperature < 0) 57 return temperature; 58 /* display in millidegree celcius */ 59 return sprintf(buf, "%u\n", temperature * 1000); 60 case 1: 61 case 2: 62 return sprintf(buf, "%u\n", 63 phy->throttle_temp[i - 1] * 1000); 64 case 3: 65 return sprintf(buf, "%hhu\n", phy->throttle_state); 66 default: 67 return -EINVAL; 68 } 69 } 70 71 static ssize_t mt7915_thermal_temp_store(struct device *dev, 72 struct device_attribute *attr, 73 const char *buf, size_t count) 74 { 75 struct mt7915_phy *phy = dev_get_drvdata(dev); 76 int ret, i = to_sensor_dev_attr(attr)->index; 77 long val; 78 79 ret = kstrtol(buf, 10, &val); 80 if (ret < 0) 81 return ret; 82 83 mutex_lock(&phy->dev->mt76.mutex); 84 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 85 86 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 87 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 88 (i - 1 == MT7915_MAX_TEMP_IDX && 89 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 90 dev_err(phy->dev->mt76.dev, 91 "temp1_max shall be greater than temp1_crit."); 92 mutex_unlock(&phy->dev->mt76.mutex); 93 return -EINVAL; 94 } 95 96 phy->throttle_temp[i - 1] = val; 97 mutex_unlock(&phy->dev->mt76.mutex); 98 99 ret = mt7915_mcu_set_thermal_protect(phy); 100 if (ret) 101 return ret; 102 103 return count; 104 } 105 106 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 107 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 108 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 109 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 110 111 static struct attribute *mt7915_hwmon_attrs[] = { 112 &sensor_dev_attr_temp1_input.dev_attr.attr, 113 &sensor_dev_attr_temp1_crit.dev_attr.attr, 114 &sensor_dev_attr_temp1_max.dev_attr.attr, 115 &sensor_dev_attr_throttle1.dev_attr.attr, 116 NULL, 117 }; 118 ATTRIBUTE_GROUPS(mt7915_hwmon); 119 120 static int 121 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 122 unsigned long *state) 123 { 124 *state = MT7915_CDEV_THROTTLE_MAX; 125 126 return 0; 127 } 128 129 static int 130 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 131 unsigned long *state) 132 { 133 struct mt7915_phy *phy = cdev->devdata; 134 135 *state = phy->cdev_state; 136 137 return 0; 138 } 139 140 static int 141 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 142 unsigned long state) 143 { 144 struct mt7915_phy *phy = cdev->devdata; 145 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 146 int ret; 147 148 if (state > MT7915_CDEV_THROTTLE_MAX) { 149 dev_err(phy->dev->mt76.dev, 150 "please specify a valid throttling state\n"); 151 return -EINVAL; 152 } 153 154 if (state == phy->cdev_state) 155 return 0; 156 157 /* 158 * cooling_device convention: 0 = no cooling, more = more cooling 159 * mcu convention: 1 = max cooling, more = less cooling 160 */ 161 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 162 if (ret) 163 return ret; 164 165 phy->cdev_state = state; 166 167 return 0; 168 } 169 170 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 171 .get_max_state = mt7915_thermal_get_max_throttle_state, 172 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 173 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 174 }; 175 176 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 177 { 178 struct wiphy *wiphy = phy->mt76->hw->wiphy; 179 180 if (!phy->cdev) 181 return; 182 183 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 184 thermal_cooling_device_unregister(phy->cdev); 185 } 186 187 static int mt7915_thermal_init(struct mt7915_phy *phy) 188 { 189 struct wiphy *wiphy = phy->mt76->hw->wiphy; 190 struct thermal_cooling_device *cdev; 191 struct device *hwmon; 192 const char *name; 193 194 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 195 wiphy_name(wiphy)); 196 197 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 198 if (!IS_ERR(cdev)) { 199 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 200 "cooling_device") < 0) 201 thermal_cooling_device_unregister(cdev); 202 else 203 phy->cdev = cdev; 204 } 205 206 /* initialize critical/maximum high temperature */ 207 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 208 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 209 210 if (!IS_REACHABLE(CONFIG_HWMON)) 211 return 0; 212 213 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 214 mt7915_hwmon_groups); 215 if (IS_ERR(hwmon)) 216 return PTR_ERR(hwmon); 217 218 return 0; 219 } 220 221 static void mt7915_led_set_config(struct led_classdev *led_cdev, 222 u8 delay_on, u8 delay_off) 223 { 224 struct mt7915_dev *dev; 225 struct mt76_phy *mphy; 226 u32 val; 227 228 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 229 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 230 231 /* set PWM mode */ 232 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 233 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 234 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 235 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 236 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 237 238 /* enable LED */ 239 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 240 241 /* control LED */ 242 val = MT_LED_CTRL_KICK; 243 if (dev->mphy.leds.al) 244 val |= MT_LED_CTRL_POLARITY; 245 if (mphy->band_idx) 246 val |= MT_LED_CTRL_BAND; 247 248 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 249 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 250 } 251 252 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 253 unsigned long *delay_on, 254 unsigned long *delay_off) 255 { 256 u16 delta_on = 0, delta_off = 0; 257 258 #define HW_TICK 10 259 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 260 261 if (*delay_on) 262 delta_on = TO_HW_TICK(*delay_on); 263 if (*delay_off) 264 delta_off = TO_HW_TICK(*delay_off); 265 266 mt7915_led_set_config(led_cdev, delta_on, delta_off); 267 268 return 0; 269 } 270 271 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 272 enum led_brightness brightness) 273 { 274 if (!brightness) 275 mt7915_led_set_config(led_cdev, 0, 0xff); 276 else 277 mt7915_led_set_config(led_cdev, 0xff, 0); 278 } 279 280 void mt7915_init_txpower(struct mt7915_dev *dev, 281 struct ieee80211_supported_band *sband) 282 { 283 int i, n_chains = hweight8(dev->mphy.antenna_mask); 284 int nss_delta = mt76_tx_power_nss_delta(n_chains); 285 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 286 struct mt76_power_limits limits; 287 288 for (i = 0; i < sband->n_channels; i++) { 289 struct ieee80211_channel *chan = &sband->channels[i]; 290 u32 target_power = 0; 291 int j; 292 293 for (j = 0; j < n_chains; j++) { 294 u32 val; 295 296 val = mt7915_eeprom_get_target_power(dev, chan, j); 297 target_power = max(target_power, val); 298 } 299 300 target_power += pwr_delta; 301 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 302 &limits, 303 target_power); 304 target_power += nss_delta; 305 target_power = DIV_ROUND_UP(target_power, 2); 306 chan->max_power = min_t(int, chan->max_reg_power, 307 target_power); 308 chan->orig_mpwr = target_power; 309 } 310 } 311 312 static void 313 mt7915_regd_notifier(struct wiphy *wiphy, 314 struct regulatory_request *request) 315 { 316 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 317 struct mt7915_dev *dev = mt7915_hw_dev(hw); 318 struct mt76_phy *mphy = hw->priv; 319 struct mt7915_phy *phy = mphy->priv; 320 321 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 322 dev->mt76.region = request->dfs_region; 323 324 if (dev->mt76.region == NL80211_DFS_UNSET) 325 mt7915_mcu_rdd_background_enable(phy, NULL); 326 327 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 328 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 329 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 330 331 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 332 mt7915_dfs_init_radar_detector(phy); 333 } 334 335 static void 336 mt7915_init_wiphy(struct mt7915_phy *phy) 337 { 338 struct mt76_phy *mphy = phy->mt76; 339 struct ieee80211_hw *hw = mphy->hw; 340 struct mt76_dev *mdev = &phy->dev->mt76; 341 struct wiphy *wiphy = hw->wiphy; 342 struct mt7915_dev *dev = phy->dev; 343 344 hw->queues = 4; 345 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 346 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 347 hw->netdev_features = NETIF_F_RXCSUM; 348 349 hw->radiotap_timestamp.units_pos = 350 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 351 352 phy->slottime = 9; 353 354 hw->sta_data_size = sizeof(struct mt7915_sta); 355 hw->vif_data_size = sizeof(struct mt7915_vif); 356 357 wiphy->iface_combinations = if_comb; 358 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 359 wiphy->reg_notifier = mt7915_regd_notifier; 360 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 361 wiphy->mbssid_max_interfaces = 16; 362 363 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 364 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 365 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 366 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 367 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 368 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 369 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 370 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 371 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 372 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 373 374 if (!is_mt7915(&dev->mt76)) 375 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 376 377 if (!mdev->dev->of_node || 378 !of_property_read_bool(mdev->dev->of_node, 379 "mediatek,disable-radar-background")) 380 wiphy_ext_feature_set(wiphy, 381 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 382 383 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 384 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 385 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 386 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 387 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 388 389 hw->max_tx_fragments = 4; 390 391 if (phy->mt76->cap.has_2ghz) { 392 phy->mt76->sband_2g.sband.ht_cap.cap |= 393 IEEE80211_HT_CAP_LDPC_CODING | 394 IEEE80211_HT_CAP_MAX_AMSDU; 395 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 396 IEEE80211_HT_MPDU_DENSITY_4; 397 } 398 399 if (phy->mt76->cap.has_5ghz) { 400 struct ieee80211_sta_vht_cap *vht_cap; 401 402 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 403 phy->mt76->sband_5g.sband.ht_cap.cap |= 404 IEEE80211_HT_CAP_LDPC_CODING | 405 IEEE80211_HT_CAP_MAX_AMSDU; 406 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 407 IEEE80211_HT_MPDU_DENSITY_4; 408 409 if (is_mt7915(&dev->mt76)) { 410 vht_cap->cap |= 411 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 412 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 413 414 if (!dev->dbdc_support) 415 vht_cap->cap |= 416 IEEE80211_VHT_CAP_SHORT_GI_160 | 417 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 418 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 419 } else { 420 vht_cap->cap |= 421 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 422 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 423 424 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 425 vht_cap->cap |= 426 IEEE80211_VHT_CAP_SHORT_GI_160 | 427 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 428 } 429 430 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 431 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 432 } 433 434 mt76_set_stream_caps(phy->mt76, true); 435 mt7915_set_stream_vht_txbf_caps(phy); 436 mt7915_set_stream_he_caps(phy); 437 438 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 439 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 440 441 /* init led callbacks */ 442 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 443 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 444 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 445 } 446 } 447 448 static void 449 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 450 { 451 u32 mask, set; 452 453 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 454 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 455 mt76_set(dev, MT_TMAC_CTCR0(band), 456 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 457 MT_TMAC_CTCR0_INS_DDLMT_EN); 458 459 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 460 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 461 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 462 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 463 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 464 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 465 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 466 467 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 468 MT_MDP_RCFR1_RX_DROPPED_UCAST | 469 MT_MDP_RCFR1_RX_DROPPED_MCAST; 470 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 471 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 472 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 473 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 474 475 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 476 477 /* mt7915: disable rx rate report by default due to hw issues */ 478 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 479 480 /* clear estimated value of EIFS for Rx duration & OBSS time */ 481 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 482 483 /* clear backoff time for Rx duration */ 484 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 485 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 486 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 487 MT_WF_RMAC_MIB_QOS01_BACKOFF); 488 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 489 MT_WF_RMAC_MIB_QOS23_BACKOFF); 490 491 /* clear backoff time and set software compensation for OBSS time */ 492 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 493 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 494 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 495 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 496 497 /* filter out non-resp frames and get instanstaeous signal reporting */ 498 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 499 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 500 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 501 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 502 } 503 504 static void 505 mt7915_init_led_mux(struct mt7915_dev *dev) 506 { 507 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 508 return; 509 510 if (dev->dbdc_support) { 511 switch (mt76_chip(&dev->mt76)) { 512 case 0x7915: 513 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 514 GENMASK(11, 8), 4); 515 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 516 GENMASK(11, 8), 4); 517 break; 518 case 0x7986: 519 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 520 GENMASK(7, 4), 1); 521 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 522 GENMASK(11, 8), 1); 523 break; 524 case 0x7916: 525 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 526 GENMASK(27, 24), 3); 527 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 528 GENMASK(31, 28), 3); 529 break; 530 default: 531 break; 532 } 533 } else if (dev->mphy.leds.pin) { 534 switch (mt76_chip(&dev->mt76)) { 535 case 0x7915: 536 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 537 GENMASK(11, 8), 4); 538 break; 539 case 0x7986: 540 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 541 GENMASK(11, 8), 1); 542 break; 543 case 0x7916: 544 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 545 GENMASK(31, 28), 3); 546 break; 547 default: 548 break; 549 } 550 } else { 551 switch (mt76_chip(&dev->mt76)) { 552 case 0x7915: 553 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 554 GENMASK(11, 8), 4); 555 break; 556 case 0x7986: 557 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 558 GENMASK(7, 4), 1); 559 break; 560 case 0x7916: 561 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 562 GENMASK(27, 24), 3); 563 break; 564 default: 565 break; 566 } 567 } 568 } 569 570 void mt7915_mac_init(struct mt7915_dev *dev) 571 { 572 int i; 573 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 574 575 /* config pse qid6 wfdma port selection */ 576 if (!is_mt7915(&dev->mt76) && dev->hif2) 577 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 578 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 579 580 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 581 582 if (!is_mt7915(&dev->mt76)) 583 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 584 585 /* enable hardware de-agg */ 586 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 587 588 for (i = 0; i < mt7915_wtbl_size(dev); i++) 589 mt7915_mac_wtbl_update(dev, i, 590 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 591 for (i = 0; i < 2; i++) 592 mt7915_mac_init_band(dev, i); 593 594 mt7915_init_led_mux(dev); 595 } 596 597 int mt7915_txbf_init(struct mt7915_dev *dev) 598 { 599 int ret; 600 601 if (dev->dbdc_support) { 602 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 603 if (ret) 604 return ret; 605 } 606 607 /* trigger sounding packets */ 608 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 609 if (ret) 610 return ret; 611 612 /* enable eBF */ 613 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 614 } 615 616 static struct mt7915_phy * 617 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 618 { 619 struct mt7915_phy *phy; 620 struct mt76_phy *mphy; 621 622 if (!dev->dbdc_support) 623 return NULL; 624 625 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 626 if (!mphy) 627 return ERR_PTR(-ENOMEM); 628 629 phy = mphy->priv; 630 phy->dev = dev; 631 phy->mt76 = mphy; 632 633 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 634 phy->mt76->band_idx = 1; 635 636 return phy; 637 } 638 639 static int 640 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 641 { 642 struct mt76_phy *mphy = phy->mt76; 643 int ret; 644 645 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 646 647 mt7915_eeprom_parse_hw_cap(dev, phy); 648 649 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 650 ETH_ALEN); 651 /* Make the secondary PHY MAC address local without overlapping with 652 * the usual MAC address allocation scheme on multiple virtual interfaces 653 */ 654 if (!is_valid_ether_addr(mphy->macaddr)) { 655 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 656 ETH_ALEN); 657 mphy->macaddr[0] |= 2; 658 mphy->macaddr[0] ^= BIT(7); 659 } 660 mt76_eeprom_override(mphy); 661 662 /* init wiphy according to mphy and phy */ 663 mt7915_init_wiphy(phy); 664 665 ret = mt76_register_phy(mphy, true, mt76_rates, 666 ARRAY_SIZE(mt76_rates)); 667 if (ret) 668 return ret; 669 670 ret = mt7915_thermal_init(phy); 671 if (ret) 672 goto unreg; 673 674 mt7915_init_debugfs(phy); 675 676 return 0; 677 678 unreg: 679 mt76_unregister_phy(mphy); 680 return ret; 681 } 682 683 static void mt7915_init_work(struct work_struct *work) 684 { 685 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 686 init_work); 687 688 mt7915_mcu_set_eeprom(dev); 689 mt7915_mac_init(dev); 690 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 691 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 692 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 693 mt7915_txbf_init(dev); 694 } 695 696 void mt7915_wfsys_reset(struct mt7915_dev *dev) 697 { 698 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 699 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 700 701 if (is_mt7915(&dev->mt76)) { 702 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 703 704 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 705 706 /* change to software control */ 707 val |= MT_TOP_PWR_SW_RST; 708 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 709 710 /* reset wfsys */ 711 val &= ~MT_TOP_PWR_SW_RST; 712 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 713 714 /* release wfsys then mcu re-executes romcode */ 715 val |= MT_TOP_PWR_SW_RST; 716 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 717 718 /* switch to hw control */ 719 val &= ~MT_TOP_PWR_SW_RST; 720 val |= MT_TOP_PWR_HW_CTRL; 721 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 722 723 /* check whether mcu resets to default */ 724 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 725 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 726 1000)) { 727 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 728 return; 729 } 730 731 /* wfsys reset won't clear host registers */ 732 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 733 734 msleep(100); 735 } else if (is_mt7986(&dev->mt76)) { 736 mt7986_wmac_disable(dev); 737 msleep(20); 738 739 mt7986_wmac_enable(dev); 740 msleep(20); 741 } else { 742 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 743 msleep(20); 744 745 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 746 msleep(20); 747 } 748 } 749 750 static bool mt7915_band_config(struct mt7915_dev *dev) 751 { 752 bool ret = true; 753 754 dev->phy.mt76->band_idx = 0; 755 756 if (is_mt7986(&dev->mt76)) { 757 u32 sku = mt7915_check_adie(dev, true); 758 759 /* 760 * for mt7986, dbdc support is determined by the number 761 * of adie chips and the main phy is bound to band1 when 762 * dbdc is disabled. 763 */ 764 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 765 dev->phy.mt76->band_idx = 1; 766 ret = false; 767 } 768 } else { 769 ret = is_mt7915(&dev->mt76) ? 770 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 771 } 772 773 return ret; 774 } 775 776 static int 777 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 778 { 779 int ret, idx; 780 781 mt76_wr(dev, MT_INT_MASK_CSR, 0); 782 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 783 784 INIT_WORK(&dev->init_work, mt7915_init_work); 785 786 ret = mt7915_dma_init(dev, phy2); 787 if (ret) 788 return ret; 789 790 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 791 792 ret = mt7915_mcu_init(dev); 793 if (ret) 794 return ret; 795 796 ret = mt7915_eeprom_init(dev); 797 if (ret < 0) 798 return ret; 799 800 if (dev->flash_mode) { 801 ret = mt7915_mcu_apply_group_cal(dev); 802 if (ret) 803 return ret; 804 } 805 806 /* Beacon and mgmt frames should occupy wcid 0 */ 807 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 808 if (idx) 809 return -ENOSPC; 810 811 dev->mt76.global_wcid.idx = idx; 812 dev->mt76.global_wcid.hw_key_idx = -1; 813 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 814 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 815 816 return 0; 817 } 818 819 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 820 { 821 int sts; 822 u32 *cap; 823 824 if (!phy->mt76->cap.has_5ghz) 825 return; 826 827 sts = hweight8(phy->mt76->chainmask); 828 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 829 830 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 831 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 832 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 833 sts - 1); 834 835 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 836 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 837 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 838 839 if (sts < 2) 840 return; 841 842 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 843 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 844 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 845 sts - 1); 846 } 847 848 static void 849 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 850 struct ieee80211_sta_he_cap *he_cap, int vif) 851 { 852 struct mt7915_dev *dev = phy->dev; 853 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 854 int sts = hweight8(phy->mt76->chainmask); 855 u8 c, sts_160 = sts; 856 857 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 858 if (is_mt7915(&dev->mt76)) { 859 if (!dev->dbdc_support) 860 sts_160 /= 2; 861 else 862 sts_160 = 0; 863 } 864 865 #ifdef CONFIG_MAC80211_MESH 866 if (vif == NL80211_IFTYPE_MESH_POINT) 867 return; 868 #endif 869 870 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 871 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 872 873 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 874 if (sts_160) 875 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 876 elem->phy_cap_info[5] &= ~c; 877 878 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 879 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 880 elem->phy_cap_info[6] &= ~c; 881 882 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 883 884 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 885 if (!is_mt7915(&dev->mt76)) 886 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 887 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 888 elem->phy_cap_info[2] |= c; 889 890 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 891 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 892 if (sts_160) 893 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 894 elem->phy_cap_info[4] |= c; 895 896 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 897 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 898 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 899 900 if (vif == NL80211_IFTYPE_STATION) 901 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 902 903 elem->phy_cap_info[6] |= c; 904 905 if (sts < 2) 906 return; 907 908 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 909 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 910 911 if (vif != NL80211_IFTYPE_AP) 912 return; 913 914 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 915 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 916 917 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 918 sts - 1); 919 if (sts_160) 920 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 921 sts_160 - 1); 922 elem->phy_cap_info[5] |= c; 923 924 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 925 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 926 elem->phy_cap_info[6] |= c; 927 928 if (!is_mt7915(&dev->mt76)) { 929 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 930 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 931 elem->phy_cap_info[7] |= c; 932 } 933 } 934 935 static int 936 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 937 struct ieee80211_sband_iftype_data *data) 938 { 939 struct mt7915_dev *dev = phy->dev; 940 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 941 u16 mcs_map = 0; 942 u16 mcs_map_160 = 0; 943 u8 nss_160; 944 945 if (!is_mt7915(&dev->mt76)) 946 nss_160 = nss; 947 else if (!dev->dbdc_support) 948 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 949 nss_160 = nss / 2; 950 else 951 /* Can't do 160MHz with mt7915 dbdc */ 952 nss_160 = 0; 953 954 for (i = 0; i < 8; i++) { 955 if (i < nss) 956 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 957 else 958 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 959 960 if (i < nss_160) 961 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 962 else 963 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 964 } 965 966 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 967 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 968 struct ieee80211_he_cap_elem *he_cap_elem = 969 &he_cap->he_cap_elem; 970 struct ieee80211_he_mcs_nss_supp *he_mcs = 971 &he_cap->he_mcs_nss_supp; 972 973 switch (i) { 974 case NL80211_IFTYPE_STATION: 975 case NL80211_IFTYPE_AP: 976 #ifdef CONFIG_MAC80211_MESH 977 case NL80211_IFTYPE_MESH_POINT: 978 #endif 979 break; 980 default: 981 continue; 982 } 983 984 data[idx].types_mask = BIT(i); 985 he_cap->has_he = true; 986 987 he_cap_elem->mac_cap_info[0] = 988 IEEE80211_HE_MAC_CAP0_HTC_HE; 989 he_cap_elem->mac_cap_info[3] = 990 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 991 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 992 he_cap_elem->mac_cap_info[4] = 993 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 994 995 if (band == NL80211_BAND_2GHZ) 996 he_cap_elem->phy_cap_info[0] = 997 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 998 else if (nss_160) 999 he_cap_elem->phy_cap_info[0] = 1000 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1001 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1002 else 1003 he_cap_elem->phy_cap_info[0] = 1004 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1005 1006 he_cap_elem->phy_cap_info[1] = 1007 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1008 he_cap_elem->phy_cap_info[2] = 1009 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1010 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1011 1012 switch (i) { 1013 case NL80211_IFTYPE_AP: 1014 he_cap_elem->mac_cap_info[0] |= 1015 IEEE80211_HE_MAC_CAP0_TWT_RES; 1016 he_cap_elem->mac_cap_info[2] |= 1017 IEEE80211_HE_MAC_CAP2_BSR; 1018 he_cap_elem->mac_cap_info[4] |= 1019 IEEE80211_HE_MAC_CAP4_BQR; 1020 he_cap_elem->mac_cap_info[5] |= 1021 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1022 he_cap_elem->phy_cap_info[3] |= 1023 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1024 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1025 he_cap_elem->phy_cap_info[6] |= 1026 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1027 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1028 he_cap_elem->phy_cap_info[9] |= 1029 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1030 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1031 break; 1032 case NL80211_IFTYPE_STATION: 1033 he_cap_elem->mac_cap_info[1] |= 1034 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1035 1036 if (band == NL80211_BAND_2GHZ) 1037 he_cap_elem->phy_cap_info[0] |= 1038 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1039 else 1040 he_cap_elem->phy_cap_info[0] |= 1041 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1042 1043 he_cap_elem->phy_cap_info[1] |= 1044 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1045 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1046 he_cap_elem->phy_cap_info[3] |= 1047 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1048 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1049 he_cap_elem->phy_cap_info[6] |= 1050 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1051 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1052 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1053 he_cap_elem->phy_cap_info[7] |= 1054 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1055 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1056 he_cap_elem->phy_cap_info[8] |= 1057 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1058 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1059 if (nss_160) 1060 he_cap_elem->phy_cap_info[8] |= 1061 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1062 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1063 he_cap_elem->phy_cap_info[9] |= 1064 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1065 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1066 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1067 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1068 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1069 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1070 break; 1071 } 1072 1073 memset(he_mcs, 0, sizeof(*he_mcs)); 1074 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1075 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1076 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1077 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1078 1079 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1080 1081 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1082 if (he_cap_elem->phy_cap_info[6] & 1083 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1084 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1085 } else { 1086 he_cap_elem->phy_cap_info[9] |= 1087 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1088 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1089 } 1090 1091 if (band == NL80211_BAND_6GHZ) { 1092 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1093 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1094 1095 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1096 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1097 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1098 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1099 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1100 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1101 1102 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1103 } 1104 1105 idx++; 1106 } 1107 1108 return idx; 1109 } 1110 1111 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1112 { 1113 struct ieee80211_sband_iftype_data *data; 1114 struct ieee80211_supported_band *band; 1115 int n; 1116 1117 if (phy->mt76->cap.has_2ghz) { 1118 data = phy->iftype[NL80211_BAND_2GHZ]; 1119 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1120 1121 band = &phy->mt76->sband_2g.sband; 1122 band->iftype_data = data; 1123 band->n_iftype_data = n; 1124 } 1125 1126 if (phy->mt76->cap.has_5ghz) { 1127 data = phy->iftype[NL80211_BAND_5GHZ]; 1128 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1129 1130 band = &phy->mt76->sband_5g.sband; 1131 band->iftype_data = data; 1132 band->n_iftype_data = n; 1133 } 1134 1135 if (phy->mt76->cap.has_6ghz) { 1136 data = phy->iftype[NL80211_BAND_6GHZ]; 1137 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1138 1139 band = &phy->mt76->sband_6g.sband; 1140 band->iftype_data = data; 1141 band->n_iftype_data = n; 1142 } 1143 } 1144 1145 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1146 { 1147 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1148 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1149 1150 if (!phy) 1151 return; 1152 1153 mt7915_unregister_thermal(phy); 1154 mt76_unregister_phy(mphy); 1155 ieee80211_free_hw(mphy->hw); 1156 } 1157 1158 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1159 { 1160 mt7915_mcu_exit(dev); 1161 mt7915_tx_token_put(dev); 1162 mt7915_dma_cleanup(dev); 1163 tasklet_disable(&dev->mt76.irq_tasklet); 1164 1165 if (is_mt7986(&dev->mt76)) 1166 mt7986_wmac_disable(dev); 1167 } 1168 1169 int mt7915_register_device(struct mt7915_dev *dev) 1170 { 1171 struct mt7915_phy *phy2; 1172 int ret; 1173 1174 dev->phy.dev = dev; 1175 dev->phy.mt76 = &dev->mt76.phy; 1176 dev->mt76.phy.priv = &dev->phy; 1177 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1178 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1179 INIT_LIST_HEAD(&dev->sta_rc_list); 1180 INIT_LIST_HEAD(&dev->sta_poll_list); 1181 INIT_LIST_HEAD(&dev->twt_list); 1182 spin_lock_init(&dev->sta_poll_lock); 1183 1184 init_waitqueue_head(&dev->reset_wait); 1185 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1186 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1187 mutex_init(&dev->dump_mutex); 1188 1189 dev->dbdc_support = mt7915_band_config(dev); 1190 1191 phy2 = mt7915_alloc_ext_phy(dev); 1192 if (IS_ERR(phy2)) 1193 return PTR_ERR(phy2); 1194 1195 ret = mt7915_init_hardware(dev, phy2); 1196 if (ret) 1197 goto free_phy2; 1198 1199 mt7915_init_wiphy(&dev->phy); 1200 1201 #ifdef CONFIG_NL80211_TESTMODE 1202 dev->mt76.test_ops = &mt7915_testmode_ops; 1203 #endif 1204 1205 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1206 ARRAY_SIZE(mt76_rates)); 1207 if (ret) 1208 goto stop_hw; 1209 1210 ret = mt7915_thermal_init(&dev->phy); 1211 if (ret) 1212 goto unreg_dev; 1213 1214 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1215 1216 if (phy2) { 1217 ret = mt7915_register_ext_phy(dev, phy2); 1218 if (ret) 1219 goto unreg_thermal; 1220 } 1221 1222 dev->recovery.hw_init_done = true; 1223 1224 ret = mt7915_init_debugfs(&dev->phy); 1225 if (ret) 1226 goto unreg_thermal; 1227 1228 ret = mt7915_coredump_register(dev); 1229 if (ret) 1230 goto unreg_thermal; 1231 1232 return 0; 1233 1234 unreg_thermal: 1235 mt7915_unregister_thermal(&dev->phy); 1236 unreg_dev: 1237 mt76_unregister_device(&dev->mt76); 1238 stop_hw: 1239 mt7915_stop_hardware(dev); 1240 free_phy2: 1241 if (phy2) 1242 ieee80211_free_hw(phy2->mt76->hw); 1243 return ret; 1244 } 1245 1246 void mt7915_unregister_device(struct mt7915_dev *dev) 1247 { 1248 mt7915_unregister_ext_phy(dev); 1249 mt7915_coredump_unregister(dev); 1250 mt7915_unregister_thermal(&dev->phy); 1251 mt76_unregister_device(&dev->mt76); 1252 mt7915_stop_hardware(dev); 1253 1254 mt76_free_device(&dev->mt76); 1255 } 1256