1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/thermal.h> 8 #include "mt7915.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "coredump.h" 12 #include "eeprom.h" 13 14 static const struct ieee80211_iface_limit if_limits[] = { 15 { 16 .max = 1, 17 .types = BIT(NL80211_IFTYPE_ADHOC) 18 }, { 19 .max = 16, 20 .types = BIT(NL80211_IFTYPE_AP) 21 #ifdef CONFIG_MAC80211_MESH 22 | BIT(NL80211_IFTYPE_MESH_POINT) 23 #endif 24 }, { 25 .max = MT7915_MAX_INTERFACES, 26 .types = BIT(NL80211_IFTYPE_STATION) 27 } 28 }; 29 30 static const struct ieee80211_iface_combination if_comb[] = { 31 { 32 .limits = if_limits, 33 .n_limits = ARRAY_SIZE(if_limits), 34 .max_interfaces = MT7915_MAX_INTERFACES, 35 .num_different_channels = 1, 36 .beacon_int_infra_match = true, 37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 38 BIT(NL80211_CHAN_WIDTH_20) | 39 BIT(NL80211_CHAN_WIDTH_40) | 40 BIT(NL80211_CHAN_WIDTH_80) | 41 BIT(NL80211_CHAN_WIDTH_160) | 42 BIT(NL80211_CHAN_WIDTH_80P80), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 temperature = mt7915_mcu_get_temperature(phy); 57 if (temperature < 0) 58 return temperature; 59 /* display in millidegree celcius */ 60 return sprintf(buf, "%u\n", temperature * 1000); 61 case 1: 62 case 2: 63 return sprintf(buf, "%u\n", 64 phy->throttle_temp[i - 1] * 1000); 65 case 3: 66 return sprintf(buf, "%hhu\n", phy->throttle_state); 67 default: 68 return -EINVAL; 69 } 70 } 71 72 static ssize_t mt7915_thermal_temp_store(struct device *dev, 73 struct device_attribute *attr, 74 const char *buf, size_t count) 75 { 76 struct mt7915_phy *phy = dev_get_drvdata(dev); 77 int ret, i = to_sensor_dev_attr(attr)->index; 78 long val; 79 80 ret = kstrtol(buf, 10, &val); 81 if (ret < 0) 82 return ret; 83 84 mutex_lock(&phy->dev->mt76.mutex); 85 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 86 phy->throttle_temp[i - 1] = val; 87 mutex_unlock(&phy->dev->mt76.mutex); 88 89 return count; 90 } 91 92 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 93 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 94 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 95 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 96 97 static struct attribute *mt7915_hwmon_attrs[] = { 98 &sensor_dev_attr_temp1_input.dev_attr.attr, 99 &sensor_dev_attr_temp1_crit.dev_attr.attr, 100 &sensor_dev_attr_temp1_max.dev_attr.attr, 101 &sensor_dev_attr_throttle1.dev_attr.attr, 102 NULL, 103 }; 104 ATTRIBUTE_GROUPS(mt7915_hwmon); 105 106 static int 107 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 108 unsigned long *state) 109 { 110 *state = MT7915_CDEV_THROTTLE_MAX; 111 112 return 0; 113 } 114 115 static int 116 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 117 unsigned long *state) 118 { 119 struct mt7915_phy *phy = cdev->devdata; 120 121 *state = phy->cdev_state; 122 123 return 0; 124 } 125 126 static int 127 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 128 unsigned long state) 129 { 130 struct mt7915_phy *phy = cdev->devdata; 131 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 132 int ret; 133 134 if (state > MT7915_CDEV_THROTTLE_MAX) 135 return -EINVAL; 136 137 if (phy->throttle_temp[0] > phy->throttle_temp[1]) 138 return 0; 139 140 if (state == phy->cdev_state) 141 return 0; 142 143 /* 144 * cooling_device convention: 0 = no cooling, more = more cooling 145 * mcu convention: 1 = max cooling, more = less cooling 146 */ 147 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 148 if (ret) 149 return ret; 150 151 phy->cdev_state = state; 152 153 return 0; 154 } 155 156 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 157 .get_max_state = mt7915_thermal_get_max_throttle_state, 158 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 159 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 160 }; 161 162 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 163 { 164 struct wiphy *wiphy = phy->mt76->hw->wiphy; 165 166 if (!phy->cdev) 167 return; 168 169 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 170 thermal_cooling_device_unregister(phy->cdev); 171 } 172 173 static int mt7915_thermal_init(struct mt7915_phy *phy) 174 { 175 struct wiphy *wiphy = phy->mt76->hw->wiphy; 176 struct thermal_cooling_device *cdev; 177 struct device *hwmon; 178 const char *name; 179 180 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 181 wiphy_name(wiphy)); 182 183 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 184 if (!IS_ERR(cdev)) { 185 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 186 "cooling_device") < 0) 187 thermal_cooling_device_unregister(cdev); 188 else 189 phy->cdev = cdev; 190 } 191 192 if (!IS_REACHABLE(CONFIG_HWMON)) 193 return 0; 194 195 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 196 mt7915_hwmon_groups); 197 if (IS_ERR(hwmon)) 198 return PTR_ERR(hwmon); 199 200 /* initialize critical/maximum high temperature */ 201 phy->throttle_temp[0] = 110; 202 phy->throttle_temp[1] = 120; 203 204 return mt7915_mcu_set_thermal_throttling(phy, 205 MT7915_THERMAL_THROTTLE_MAX); 206 } 207 208 static void mt7915_led_set_config(struct led_classdev *led_cdev, 209 u8 delay_on, u8 delay_off) 210 { 211 struct mt7915_dev *dev; 212 struct mt76_phy *mphy; 213 u32 val; 214 215 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 216 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 217 218 /* set PWM mode */ 219 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 220 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 221 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 222 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 223 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 224 225 /* enable LED */ 226 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 227 228 /* control LED */ 229 val = MT_LED_CTRL_KICK; 230 if (dev->mphy.leds.al) 231 val |= MT_LED_CTRL_POLARITY; 232 if (mphy->band_idx) 233 val |= MT_LED_CTRL_BAND; 234 235 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 236 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 237 } 238 239 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 240 unsigned long *delay_on, 241 unsigned long *delay_off) 242 { 243 u16 delta_on = 0, delta_off = 0; 244 245 #define HW_TICK 10 246 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 247 248 if (*delay_on) 249 delta_on = TO_HW_TICK(*delay_on); 250 if (*delay_off) 251 delta_off = TO_HW_TICK(*delay_off); 252 253 mt7915_led_set_config(led_cdev, delta_on, delta_off); 254 255 return 0; 256 } 257 258 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 259 enum led_brightness brightness) 260 { 261 if (!brightness) 262 mt7915_led_set_config(led_cdev, 0, 0xff); 263 else 264 mt7915_led_set_config(led_cdev, 0xff, 0); 265 } 266 267 void mt7915_init_txpower(struct mt7915_dev *dev, 268 struct ieee80211_supported_band *sband) 269 { 270 int i, n_chains = hweight8(dev->mphy.antenna_mask); 271 int nss_delta = mt76_tx_power_nss_delta(n_chains); 272 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 273 struct mt76_power_limits limits; 274 275 for (i = 0; i < sband->n_channels; i++) { 276 struct ieee80211_channel *chan = &sband->channels[i]; 277 u32 target_power = 0; 278 int j; 279 280 for (j = 0; j < n_chains; j++) { 281 u32 val; 282 283 val = mt7915_eeprom_get_target_power(dev, chan, j); 284 target_power = max(target_power, val); 285 } 286 287 target_power += pwr_delta; 288 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 289 &limits, 290 target_power); 291 target_power += nss_delta; 292 target_power = DIV_ROUND_UP(target_power, 2); 293 chan->max_power = min_t(int, chan->max_reg_power, 294 target_power); 295 chan->orig_mpwr = target_power; 296 } 297 } 298 299 static void 300 mt7915_regd_notifier(struct wiphy *wiphy, 301 struct regulatory_request *request) 302 { 303 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 304 struct mt7915_dev *dev = mt7915_hw_dev(hw); 305 struct mt76_phy *mphy = hw->priv; 306 struct mt7915_phy *phy = mphy->priv; 307 308 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 309 dev->mt76.region = request->dfs_region; 310 311 if (dev->mt76.region == NL80211_DFS_UNSET) 312 mt7915_mcu_rdd_background_enable(phy, NULL); 313 314 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 315 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 316 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 317 318 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 319 mt7915_dfs_init_radar_detector(phy); 320 } 321 322 static void 323 mt7915_init_wiphy(struct mt7915_phy *phy) 324 { 325 struct mt76_phy *mphy = phy->mt76; 326 struct ieee80211_hw *hw = mphy->hw; 327 struct mt76_dev *mdev = &phy->dev->mt76; 328 struct wiphy *wiphy = hw->wiphy; 329 struct mt7915_dev *dev = phy->dev; 330 331 hw->queues = 4; 332 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 333 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 334 hw->netdev_features = NETIF_F_RXCSUM; 335 336 hw->radiotap_timestamp.units_pos = 337 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 338 339 phy->slottime = 9; 340 341 hw->sta_data_size = sizeof(struct mt7915_sta); 342 hw->vif_data_size = sizeof(struct mt7915_vif); 343 344 wiphy->iface_combinations = if_comb; 345 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 346 wiphy->reg_notifier = mt7915_regd_notifier; 347 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 348 wiphy->mbssid_max_interfaces = 16; 349 350 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 351 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 352 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 353 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 354 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 355 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 356 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 357 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 358 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 359 360 if (!is_mt7915(&dev->mt76)) 361 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 362 363 if (!mdev->dev->of_node || 364 !of_property_read_bool(mdev->dev->of_node, 365 "mediatek,disable-radar-background")) 366 wiphy_ext_feature_set(wiphy, 367 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 368 369 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 370 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 371 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 372 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 373 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 374 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 375 376 hw->max_tx_fragments = 4; 377 378 if (phy->mt76->cap.has_2ghz) { 379 phy->mt76->sband_2g.sband.ht_cap.cap |= 380 IEEE80211_HT_CAP_LDPC_CODING | 381 IEEE80211_HT_CAP_MAX_AMSDU; 382 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 383 IEEE80211_HT_MPDU_DENSITY_4; 384 } 385 386 if (phy->mt76->cap.has_5ghz) { 387 phy->mt76->sband_5g.sband.ht_cap.cap |= 388 IEEE80211_HT_CAP_LDPC_CODING | 389 IEEE80211_HT_CAP_MAX_AMSDU; 390 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 391 IEEE80211_HT_MPDU_DENSITY_4; 392 393 if (is_mt7915(&dev->mt76)) { 394 phy->mt76->sband_5g.sband.vht_cap.cap |= 395 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 396 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 397 398 if (!dev->dbdc_support) 399 phy->mt76->sband_5g.sband.vht_cap.cap |= 400 IEEE80211_VHT_CAP_SHORT_GI_160 | 401 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ; 402 } else { 403 phy->mt76->sband_5g.sband.vht_cap.cap |= 404 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 405 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 406 407 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 408 phy->mt76->sband_5g.sband.vht_cap.cap |= 409 IEEE80211_VHT_CAP_SHORT_GI_160 | 410 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 411 } 412 } 413 414 mt76_set_stream_caps(phy->mt76, true); 415 mt7915_set_stream_vht_txbf_caps(phy); 416 mt7915_set_stream_he_caps(phy); 417 418 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 419 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 420 421 /* init led callbacks */ 422 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 423 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 424 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 425 } 426 } 427 428 static void 429 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 430 { 431 u32 mask, set; 432 433 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 434 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 435 mt76_set(dev, MT_TMAC_CTCR0(band), 436 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 437 MT_TMAC_CTCR0_INS_DDLMT_EN); 438 439 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 440 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 441 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 442 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 443 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 444 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 445 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 446 447 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 448 MT_MDP_RCFR1_RX_DROPPED_UCAST | 449 MT_MDP_RCFR1_RX_DROPPED_MCAST; 450 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 451 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 452 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 453 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 454 455 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 456 457 /* mt7915: disable rx rate report by default due to hw issues */ 458 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 459 460 /* clear estimated value of EIFS for Rx duration & OBSS time */ 461 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 462 463 /* clear backoff time for Rx duration */ 464 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 465 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 466 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 467 MT_WF_RMAC_MIB_QOS01_BACKOFF); 468 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 469 MT_WF_RMAC_MIB_QOS23_BACKOFF); 470 471 /* clear backoff time and set software compensation for OBSS time */ 472 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 473 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 474 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 475 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 476 477 /* filter out non-resp frames and get instanstaeous signal reporting */ 478 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 479 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 480 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 481 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 482 } 483 484 static void 485 mt7915_init_led_mux(struct mt7915_dev *dev) 486 { 487 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 488 return; 489 490 if (dev->dbdc_support) { 491 switch (mt76_chip(&dev->mt76)) { 492 case 0x7915: 493 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 494 GENMASK(11, 8), 4); 495 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 496 GENMASK(11, 8), 4); 497 break; 498 case 0x7986: 499 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 500 GENMASK(7, 4), 1); 501 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 502 GENMASK(11, 8), 1); 503 break; 504 case 0x7916: 505 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 506 GENMASK(27, 24), 3); 507 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 508 GENMASK(31, 28), 3); 509 break; 510 default: 511 break; 512 } 513 } else if (dev->mphy.leds.pin) { 514 switch (mt76_chip(&dev->mt76)) { 515 case 0x7915: 516 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 517 GENMASK(11, 8), 4); 518 break; 519 case 0x7986: 520 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 521 GENMASK(11, 8), 1); 522 break; 523 case 0x7916: 524 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 525 GENMASK(31, 28), 3); 526 break; 527 default: 528 break; 529 } 530 } else { 531 switch (mt76_chip(&dev->mt76)) { 532 case 0x7915: 533 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 534 GENMASK(11, 8), 4); 535 break; 536 case 0x7986: 537 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 538 GENMASK(7, 4), 1); 539 break; 540 case 0x7916: 541 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 542 GENMASK(27, 24), 3); 543 break; 544 default: 545 break; 546 } 547 } 548 } 549 550 void mt7915_mac_init(struct mt7915_dev *dev) 551 { 552 int i; 553 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 554 555 /* config pse qid6 wfdma port selection */ 556 if (!is_mt7915(&dev->mt76) && dev->hif2) 557 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 558 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 559 560 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 561 562 if (!is_mt7915(&dev->mt76)) 563 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 564 565 /* enable hardware de-agg */ 566 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 567 568 for (i = 0; i < mt7915_wtbl_size(dev); i++) 569 mt7915_mac_wtbl_update(dev, i, 570 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 571 for (i = 0; i < 2; i++) 572 mt7915_mac_init_band(dev, i); 573 574 mt7915_init_led_mux(dev); 575 } 576 577 int mt7915_txbf_init(struct mt7915_dev *dev) 578 { 579 int ret; 580 581 if (dev->dbdc_support) { 582 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 583 if (ret) 584 return ret; 585 } 586 587 /* trigger sounding packets */ 588 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 589 if (ret) 590 return ret; 591 592 /* enable eBF */ 593 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 594 } 595 596 static struct mt7915_phy * 597 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 598 { 599 struct mt7915_phy *phy; 600 struct mt76_phy *mphy; 601 602 if (!dev->dbdc_support) 603 return NULL; 604 605 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 606 if (!mphy) 607 return ERR_PTR(-ENOMEM); 608 609 phy = mphy->priv; 610 phy->dev = dev; 611 phy->mt76 = mphy; 612 613 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 614 phy->mt76->band_idx = 1; 615 616 return phy; 617 } 618 619 static int 620 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 621 { 622 struct mt76_phy *mphy = phy->mt76; 623 int ret; 624 625 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 626 627 mt7915_eeprom_parse_hw_cap(dev, phy); 628 629 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 630 ETH_ALEN); 631 /* Make the secondary PHY MAC address local without overlapping with 632 * the usual MAC address allocation scheme on multiple virtual interfaces 633 */ 634 if (!is_valid_ether_addr(mphy->macaddr)) { 635 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 636 ETH_ALEN); 637 mphy->macaddr[0] |= 2; 638 mphy->macaddr[0] ^= BIT(7); 639 } 640 mt76_eeprom_override(mphy); 641 642 /* init wiphy according to mphy and phy */ 643 mt7915_init_wiphy(phy); 644 645 ret = mt76_register_phy(mphy, true, mt76_rates, 646 ARRAY_SIZE(mt76_rates)); 647 if (ret) 648 return ret; 649 650 ret = mt7915_thermal_init(phy); 651 if (ret) 652 goto unreg; 653 654 mt7915_init_debugfs(phy); 655 656 return 0; 657 658 unreg: 659 mt76_unregister_phy(mphy); 660 return ret; 661 } 662 663 static void mt7915_init_work(struct work_struct *work) 664 { 665 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 666 init_work); 667 668 mt7915_mcu_set_eeprom(dev); 669 mt7915_mac_init(dev); 670 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 671 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 672 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 673 mt7915_txbf_init(dev); 674 } 675 676 void mt7915_wfsys_reset(struct mt7915_dev *dev) 677 { 678 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 679 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 680 681 if (is_mt7915(&dev->mt76)) { 682 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 683 684 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 685 686 /* change to software control */ 687 val |= MT_TOP_PWR_SW_RST; 688 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 689 690 /* reset wfsys */ 691 val &= ~MT_TOP_PWR_SW_RST; 692 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 693 694 /* release wfsys then mcu re-executes romcode */ 695 val |= MT_TOP_PWR_SW_RST; 696 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 697 698 /* switch to hw control */ 699 val &= ~MT_TOP_PWR_SW_RST; 700 val |= MT_TOP_PWR_HW_CTRL; 701 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 702 703 /* check whether mcu resets to default */ 704 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 705 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 706 1000)) { 707 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 708 return; 709 } 710 711 /* wfsys reset won't clear host registers */ 712 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 713 714 msleep(100); 715 } else if (is_mt7986(&dev->mt76)) { 716 mt7986_wmac_disable(dev); 717 msleep(20); 718 719 mt7986_wmac_enable(dev); 720 msleep(20); 721 } else { 722 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 723 msleep(20); 724 725 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 726 msleep(20); 727 } 728 } 729 730 static bool mt7915_band_config(struct mt7915_dev *dev) 731 { 732 bool ret = true; 733 734 dev->phy.mt76->band_idx = 0; 735 736 if (is_mt7986(&dev->mt76)) { 737 u32 sku = mt7915_check_adie(dev, true); 738 739 /* 740 * for mt7986, dbdc support is determined by the number 741 * of adie chips and the main phy is bound to band1 when 742 * dbdc is disabled. 743 */ 744 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 745 dev->phy.mt76->band_idx = 1; 746 ret = false; 747 } 748 } else { 749 ret = is_mt7915(&dev->mt76) ? 750 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 751 } 752 753 return ret; 754 } 755 756 static int 757 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 758 { 759 int ret, idx; 760 761 mt76_wr(dev, MT_INT_MASK_CSR, 0); 762 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 763 764 INIT_WORK(&dev->init_work, mt7915_init_work); 765 766 ret = mt7915_dma_init(dev, phy2); 767 if (ret) 768 return ret; 769 770 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 771 772 ret = mt7915_mcu_init(dev); 773 if (ret) 774 return ret; 775 776 ret = mt7915_eeprom_init(dev); 777 if (ret < 0) 778 return ret; 779 780 if (dev->flash_mode) { 781 ret = mt7915_mcu_apply_group_cal(dev); 782 if (ret) 783 return ret; 784 } 785 786 /* Beacon and mgmt frames should occupy wcid 0 */ 787 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 788 if (idx) 789 return -ENOSPC; 790 791 dev->mt76.global_wcid.idx = idx; 792 dev->mt76.global_wcid.hw_key_idx = -1; 793 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 794 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 795 796 return 0; 797 } 798 799 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 800 { 801 int sts; 802 u32 *cap; 803 804 if (!phy->mt76->cap.has_5ghz) 805 return; 806 807 sts = hweight8(phy->mt76->chainmask); 808 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 809 810 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 811 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 812 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 813 sts - 1); 814 815 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 816 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 817 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 818 819 if (sts < 2) 820 return; 821 822 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 823 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 824 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 825 sts - 1); 826 } 827 828 static void 829 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 830 struct ieee80211_sta_he_cap *he_cap, int vif) 831 { 832 struct mt7915_dev *dev = phy->dev; 833 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 834 int sts = hweight8(phy->mt76->chainmask); 835 u8 c, sts_160 = sts; 836 837 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 838 if (is_mt7915(&dev->mt76)) { 839 if (!dev->dbdc_support) 840 sts_160 /= 2; 841 else 842 sts_160 = 0; 843 } 844 845 #ifdef CONFIG_MAC80211_MESH 846 if (vif == NL80211_IFTYPE_MESH_POINT) 847 return; 848 #endif 849 850 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 851 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 852 853 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 854 if (sts_160) 855 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 856 elem->phy_cap_info[5] &= ~c; 857 858 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 859 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 860 elem->phy_cap_info[6] &= ~c; 861 862 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 863 864 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 865 if (!is_mt7915(&dev->mt76)) 866 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 867 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 868 elem->phy_cap_info[2] |= c; 869 870 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 871 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 872 if (sts_160) 873 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 874 elem->phy_cap_info[4] |= c; 875 876 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 877 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 878 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 879 880 if (vif == NL80211_IFTYPE_STATION) 881 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 882 883 elem->phy_cap_info[6] |= c; 884 885 if (sts < 2) 886 return; 887 888 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 889 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 890 891 if (vif != NL80211_IFTYPE_AP) 892 return; 893 894 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 895 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 896 897 /* num_snd_dim 898 * for mt7915, max supported sts is 2 for bw > 80MHz and 0 if dbdc 899 */ 900 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 901 sts - 1); 902 if (sts_160) 903 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 904 sts_160 - 1); 905 elem->phy_cap_info[5] |= c; 906 907 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 908 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 909 elem->phy_cap_info[6] |= c; 910 911 if (!is_mt7915(&dev->mt76)) { 912 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 913 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 914 elem->phy_cap_info[7] |= c; 915 } 916 } 917 918 static void 919 mt7915_gen_ppe_thresh(u8 *he_ppet, int nss) 920 { 921 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */ 922 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71}; 923 924 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | 925 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, 926 ru_bit_mask); 927 928 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE * 929 nss * hweight8(ru_bit_mask) * 2; 930 ppet_size = DIV_ROUND_UP(ppet_bits, 8); 931 932 for (i = 0; i < ppet_size - 1; i++) 933 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3]; 934 935 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] & 936 (0xff >> (8 - (ppet_bits - 1) % 8)); 937 } 938 939 static int 940 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 941 struct ieee80211_sband_iftype_data *data) 942 { 943 struct mt7915_dev *dev = phy->dev; 944 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 945 u16 mcs_map = 0; 946 u16 mcs_map_160 = 0; 947 u8 nss_160; 948 949 if (!is_mt7915(&dev->mt76)) 950 nss_160 = nss; 951 else if (!dev->dbdc_support) 952 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 953 nss_160 = nss / 2; 954 else 955 /* Can't do 160MHz with mt7915 dbdc */ 956 nss_160 = 0; 957 958 for (i = 0; i < 8; i++) { 959 if (i < nss) 960 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 961 else 962 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 963 964 if (i < nss_160) 965 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 966 else 967 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 968 } 969 970 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 971 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 972 struct ieee80211_he_cap_elem *he_cap_elem = 973 &he_cap->he_cap_elem; 974 struct ieee80211_he_mcs_nss_supp *he_mcs = 975 &he_cap->he_mcs_nss_supp; 976 977 switch (i) { 978 case NL80211_IFTYPE_STATION: 979 case NL80211_IFTYPE_AP: 980 #ifdef CONFIG_MAC80211_MESH 981 case NL80211_IFTYPE_MESH_POINT: 982 #endif 983 break; 984 default: 985 continue; 986 } 987 988 data[idx].types_mask = BIT(i); 989 he_cap->has_he = true; 990 991 he_cap_elem->mac_cap_info[0] = 992 IEEE80211_HE_MAC_CAP0_HTC_HE; 993 he_cap_elem->mac_cap_info[3] = 994 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 995 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 996 he_cap_elem->mac_cap_info[4] = 997 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 998 999 if (band == NL80211_BAND_2GHZ) 1000 he_cap_elem->phy_cap_info[0] = 1001 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1002 else if (nss_160) 1003 he_cap_elem->phy_cap_info[0] = 1004 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1005 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G | 1006 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; 1007 else 1008 he_cap_elem->phy_cap_info[0] = 1009 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1010 1011 he_cap_elem->phy_cap_info[1] = 1012 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1013 he_cap_elem->phy_cap_info[2] = 1014 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1015 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1016 1017 switch (i) { 1018 case NL80211_IFTYPE_AP: 1019 he_cap_elem->mac_cap_info[0] |= 1020 IEEE80211_HE_MAC_CAP0_TWT_RES; 1021 he_cap_elem->mac_cap_info[2] |= 1022 IEEE80211_HE_MAC_CAP2_BSR; 1023 he_cap_elem->mac_cap_info[4] |= 1024 IEEE80211_HE_MAC_CAP4_BQR; 1025 he_cap_elem->mac_cap_info[5] |= 1026 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1027 he_cap_elem->phy_cap_info[3] |= 1028 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1029 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1030 he_cap_elem->phy_cap_info[6] |= 1031 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1032 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1033 he_cap_elem->phy_cap_info[9] |= 1034 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1035 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1036 break; 1037 case NL80211_IFTYPE_STATION: 1038 he_cap_elem->mac_cap_info[1] |= 1039 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1040 1041 if (band == NL80211_BAND_2GHZ) 1042 he_cap_elem->phy_cap_info[0] |= 1043 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1044 else 1045 he_cap_elem->phy_cap_info[0] |= 1046 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1047 1048 he_cap_elem->phy_cap_info[1] |= 1049 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1050 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1051 he_cap_elem->phy_cap_info[3] |= 1052 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1053 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1054 he_cap_elem->phy_cap_info[6] |= 1055 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1056 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1057 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1058 he_cap_elem->phy_cap_info[7] |= 1059 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1060 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1061 he_cap_elem->phy_cap_info[8] |= 1062 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1063 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1064 if (nss_160) 1065 he_cap_elem->phy_cap_info[8] |= 1066 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1067 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1068 he_cap_elem->phy_cap_info[9] |= 1069 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1070 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1071 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1072 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1073 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1074 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1075 break; 1076 } 1077 1078 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1079 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1080 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1081 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1082 he_mcs->rx_mcs_80p80 = cpu_to_le16(mcs_map_160); 1083 he_mcs->tx_mcs_80p80 = cpu_to_le16(mcs_map_160); 1084 1085 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1086 1087 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1088 if (he_cap_elem->phy_cap_info[6] & 1089 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1090 mt7915_gen_ppe_thresh(he_cap->ppe_thres, nss); 1091 } else { 1092 he_cap_elem->phy_cap_info[9] |= 1093 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1094 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1095 } 1096 1097 if (band == NL80211_BAND_6GHZ) { 1098 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1099 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1100 1101 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1102 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1103 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1104 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1105 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1106 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1107 1108 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1109 } 1110 1111 idx++; 1112 } 1113 1114 return idx; 1115 } 1116 1117 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1118 { 1119 struct ieee80211_sband_iftype_data *data; 1120 struct ieee80211_supported_band *band; 1121 int n; 1122 1123 if (phy->mt76->cap.has_2ghz) { 1124 data = phy->iftype[NL80211_BAND_2GHZ]; 1125 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1126 1127 band = &phy->mt76->sband_2g.sband; 1128 band->iftype_data = data; 1129 band->n_iftype_data = n; 1130 } 1131 1132 if (phy->mt76->cap.has_5ghz) { 1133 data = phy->iftype[NL80211_BAND_5GHZ]; 1134 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1135 1136 band = &phy->mt76->sband_5g.sband; 1137 band->iftype_data = data; 1138 band->n_iftype_data = n; 1139 } 1140 1141 if (phy->mt76->cap.has_6ghz) { 1142 data = phy->iftype[NL80211_BAND_6GHZ]; 1143 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1144 1145 band = &phy->mt76->sband_6g.sband; 1146 band->iftype_data = data; 1147 band->n_iftype_data = n; 1148 } 1149 } 1150 1151 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1152 { 1153 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1154 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1155 1156 if (!phy) 1157 return; 1158 1159 mt7915_unregister_thermal(phy); 1160 mt76_unregister_phy(mphy); 1161 ieee80211_free_hw(mphy->hw); 1162 } 1163 1164 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1165 { 1166 mt7915_mcu_exit(dev); 1167 mt7915_tx_token_put(dev); 1168 mt7915_dma_cleanup(dev); 1169 tasklet_disable(&dev->irq_tasklet); 1170 1171 if (is_mt7986(&dev->mt76)) 1172 mt7986_wmac_disable(dev); 1173 } 1174 1175 1176 int mt7915_register_device(struct mt7915_dev *dev) 1177 { 1178 struct mt7915_phy *phy2; 1179 int ret; 1180 1181 dev->phy.dev = dev; 1182 dev->phy.mt76 = &dev->mt76.phy; 1183 dev->mt76.phy.priv = &dev->phy; 1184 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1185 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1186 INIT_LIST_HEAD(&dev->sta_rc_list); 1187 INIT_LIST_HEAD(&dev->sta_poll_list); 1188 INIT_LIST_HEAD(&dev->twt_list); 1189 spin_lock_init(&dev->sta_poll_lock); 1190 1191 init_waitqueue_head(&dev->reset_wait); 1192 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1193 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1194 mutex_init(&dev->dump_mutex); 1195 1196 dev->dbdc_support = mt7915_band_config(dev); 1197 1198 phy2 = mt7915_alloc_ext_phy(dev); 1199 if (IS_ERR(phy2)) 1200 return PTR_ERR(phy2); 1201 1202 ret = mt7915_init_hardware(dev, phy2); 1203 if (ret) 1204 goto free_phy2; 1205 1206 mt7915_init_wiphy(&dev->phy); 1207 1208 #ifdef CONFIG_NL80211_TESTMODE 1209 dev->mt76.test_ops = &mt7915_testmode_ops; 1210 #endif 1211 1212 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1213 ARRAY_SIZE(mt76_rates)); 1214 if (ret) 1215 goto stop_hw; 1216 1217 ret = mt7915_thermal_init(&dev->phy); 1218 if (ret) 1219 goto unreg_dev; 1220 1221 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1222 1223 if (phy2) { 1224 ret = mt7915_register_ext_phy(dev, phy2); 1225 if (ret) 1226 goto unreg_thermal; 1227 } 1228 1229 dev->recovery.hw_init_done = true; 1230 1231 ret = mt7915_init_debugfs(&dev->phy); 1232 if (ret) 1233 goto unreg_thermal; 1234 1235 ret = mt7915_coredump_register(dev); 1236 if (ret) 1237 goto unreg_thermal; 1238 1239 return 0; 1240 1241 unreg_thermal: 1242 mt7915_unregister_thermal(&dev->phy); 1243 unreg_dev: 1244 mt76_unregister_device(&dev->mt76); 1245 stop_hw: 1246 mt7915_stop_hardware(dev); 1247 free_phy2: 1248 if (phy2) 1249 ieee80211_free_hw(phy2->mt76->hw); 1250 return ret; 1251 } 1252 1253 void mt7915_unregister_device(struct mt7915_dev *dev) 1254 { 1255 mt7915_unregister_ext_phy(dev); 1256 mt7915_coredump_unregister(dev); 1257 mt7915_unregister_thermal(&dev->phy); 1258 mt76_unregister_device(&dev->mt76); 1259 mt7915_stop_hardware(dev); 1260 1261 mt76_free_device(&dev->mt76); 1262 } 1263