1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/of.h> 8 #include <linux/thermal.h> 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "mcu.h" 12 #include "coredump.h" 13 #include "eeprom.h" 14 15 static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }, { 26 .max = MT7915_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29 }; 30 31 static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7915_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 temperature = mt7915_mcu_get_temperature(phy); 57 if (temperature < 0) 58 return temperature; 59 /* display in millidegree celcius */ 60 return sprintf(buf, "%u\n", temperature * 1000); 61 case 1: 62 case 2: 63 return sprintf(buf, "%u\n", 64 phy->throttle_temp[i - 1] * 1000); 65 case 3: 66 return sprintf(buf, "%hhu\n", phy->throttle_state); 67 default: 68 return -EINVAL; 69 } 70 } 71 72 static ssize_t mt7915_thermal_temp_store(struct device *dev, 73 struct device_attribute *attr, 74 const char *buf, size_t count) 75 { 76 struct mt7915_phy *phy = dev_get_drvdata(dev); 77 int ret, i = to_sensor_dev_attr(attr)->index; 78 long val; 79 80 ret = kstrtol(buf, 10, &val); 81 if (ret < 0) 82 return ret; 83 84 mutex_lock(&phy->dev->mt76.mutex); 85 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 86 87 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 88 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 89 (i - 1 == MT7915_MAX_TEMP_IDX && 90 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 91 dev_err(phy->dev->mt76.dev, 92 "temp1_max shall be greater than temp1_crit."); 93 mutex_unlock(&phy->dev->mt76.mutex); 94 return -EINVAL; 95 } 96 97 phy->throttle_temp[i - 1] = val; 98 mutex_unlock(&phy->dev->mt76.mutex); 99 100 ret = mt7915_mcu_set_thermal_protect(phy); 101 if (ret) 102 return ret; 103 104 return count; 105 } 106 107 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 108 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 109 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 110 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 111 112 static struct attribute *mt7915_hwmon_attrs[] = { 113 &sensor_dev_attr_temp1_input.dev_attr.attr, 114 &sensor_dev_attr_temp1_crit.dev_attr.attr, 115 &sensor_dev_attr_temp1_max.dev_attr.attr, 116 &sensor_dev_attr_throttle1.dev_attr.attr, 117 NULL, 118 }; 119 ATTRIBUTE_GROUPS(mt7915_hwmon); 120 121 static int 122 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 123 unsigned long *state) 124 { 125 *state = MT7915_CDEV_THROTTLE_MAX; 126 127 return 0; 128 } 129 130 static int 131 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 132 unsigned long *state) 133 { 134 struct mt7915_phy *phy = cdev->devdata; 135 136 *state = phy->cdev_state; 137 138 return 0; 139 } 140 141 static int 142 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 143 unsigned long state) 144 { 145 struct mt7915_phy *phy = cdev->devdata; 146 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 147 int ret; 148 149 if (state > MT7915_CDEV_THROTTLE_MAX) { 150 dev_err(phy->dev->mt76.dev, 151 "please specify a valid throttling state\n"); 152 return -EINVAL; 153 } 154 155 if (state == phy->cdev_state) 156 return 0; 157 158 /* 159 * cooling_device convention: 0 = no cooling, more = more cooling 160 * mcu convention: 1 = max cooling, more = less cooling 161 */ 162 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 163 if (ret) 164 return ret; 165 166 phy->cdev_state = state; 167 168 return 0; 169 } 170 171 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 172 .get_max_state = mt7915_thermal_get_max_throttle_state, 173 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 174 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 175 }; 176 177 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 178 { 179 struct wiphy *wiphy = phy->mt76->hw->wiphy; 180 181 if (!phy->cdev) 182 return; 183 184 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 185 thermal_cooling_device_unregister(phy->cdev); 186 } 187 188 static int mt7915_thermal_init(struct mt7915_phy *phy) 189 { 190 struct wiphy *wiphy = phy->mt76->hw->wiphy; 191 struct thermal_cooling_device *cdev; 192 struct device *hwmon; 193 const char *name; 194 195 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 196 wiphy_name(wiphy)); 197 if (!name) 198 return -ENOMEM; 199 200 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 201 if (!IS_ERR(cdev)) { 202 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 203 "cooling_device") < 0) 204 thermal_cooling_device_unregister(cdev); 205 else 206 phy->cdev = cdev; 207 } 208 209 /* initialize critical/maximum high temperature */ 210 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 211 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 212 213 if (!IS_REACHABLE(CONFIG_HWMON)) 214 return 0; 215 216 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 217 mt7915_hwmon_groups); 218 if (IS_ERR(hwmon)) 219 return PTR_ERR(hwmon); 220 221 return 0; 222 } 223 224 static void mt7915_led_set_config(struct led_classdev *led_cdev, 225 u8 delay_on, u8 delay_off) 226 { 227 struct mt7915_dev *dev; 228 struct mt76_phy *mphy; 229 u32 val; 230 231 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 232 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 233 234 /* set PWM mode */ 235 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 236 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 237 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 238 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 239 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 240 241 /* enable LED */ 242 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 243 244 /* control LED */ 245 val = MT_LED_CTRL_KICK; 246 if (dev->mphy.leds.al) 247 val |= MT_LED_CTRL_POLARITY; 248 if (mphy->band_idx) 249 val |= MT_LED_CTRL_BAND; 250 251 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 252 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 253 } 254 255 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 256 unsigned long *delay_on, 257 unsigned long *delay_off) 258 { 259 u16 delta_on = 0, delta_off = 0; 260 261 #define HW_TICK 10 262 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 263 264 if (*delay_on) 265 delta_on = TO_HW_TICK(*delay_on); 266 if (*delay_off) 267 delta_off = TO_HW_TICK(*delay_off); 268 269 mt7915_led_set_config(led_cdev, delta_on, delta_off); 270 271 return 0; 272 } 273 274 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 275 enum led_brightness brightness) 276 { 277 if (!brightness) 278 mt7915_led_set_config(led_cdev, 0, 0xff); 279 else 280 mt7915_led_set_config(led_cdev, 0xff, 0); 281 } 282 283 void mt7915_init_txpower(struct mt7915_dev *dev, 284 struct ieee80211_supported_band *sband) 285 { 286 int i, n_chains = hweight8(dev->mphy.antenna_mask); 287 int nss_delta = mt76_tx_power_nss_delta(n_chains); 288 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 289 struct mt76_power_limits limits; 290 291 for (i = 0; i < sband->n_channels; i++) { 292 struct ieee80211_channel *chan = &sband->channels[i]; 293 u32 target_power = 0; 294 int j; 295 296 for (j = 0; j < n_chains; j++) { 297 u32 val; 298 299 val = mt7915_eeprom_get_target_power(dev, chan, j); 300 target_power = max(target_power, val); 301 } 302 303 target_power += pwr_delta; 304 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 305 &limits, 306 target_power); 307 target_power += nss_delta; 308 target_power = DIV_ROUND_UP(target_power, 2); 309 chan->max_power = min_t(int, chan->max_reg_power, 310 target_power); 311 chan->orig_mpwr = target_power; 312 } 313 } 314 315 static void 316 mt7915_regd_notifier(struct wiphy *wiphy, 317 struct regulatory_request *request) 318 { 319 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 320 struct mt7915_dev *dev = mt7915_hw_dev(hw); 321 struct mt76_phy *mphy = hw->priv; 322 struct mt7915_phy *phy = mphy->priv; 323 324 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 325 dev->mt76.region = request->dfs_region; 326 327 if (dev->mt76.region == NL80211_DFS_UNSET) 328 mt7915_mcu_rdd_background_enable(phy, NULL); 329 330 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 331 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 332 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 333 334 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 335 mt7915_dfs_init_radar_detector(phy); 336 } 337 338 static void 339 mt7915_init_wiphy(struct mt7915_phy *phy) 340 { 341 struct mt76_phy *mphy = phy->mt76; 342 struct ieee80211_hw *hw = mphy->hw; 343 struct mt76_dev *mdev = &phy->dev->mt76; 344 struct wiphy *wiphy = hw->wiphy; 345 struct mt7915_dev *dev = phy->dev; 346 347 hw->queues = 4; 348 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 349 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 350 hw->netdev_features = NETIF_F_RXCSUM; 351 352 hw->radiotap_timestamp.units_pos = 353 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 354 355 phy->slottime = 9; 356 357 hw->sta_data_size = sizeof(struct mt7915_sta); 358 hw->vif_data_size = sizeof(struct mt7915_vif); 359 360 wiphy->iface_combinations = if_comb; 361 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 362 wiphy->reg_notifier = mt7915_regd_notifier; 363 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 364 wiphy->mbssid_max_interfaces = 16; 365 366 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 367 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 368 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 369 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 370 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 371 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 372 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 373 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 374 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 375 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 376 377 if (!is_mt7915(&dev->mt76)) 378 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 379 380 if (!mdev->dev->of_node || 381 !of_property_read_bool(mdev->dev->of_node, 382 "mediatek,disable-radar-background")) 383 wiphy_ext_feature_set(wiphy, 384 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 385 386 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 387 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 388 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 389 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 390 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 391 ieee80211_hw_set(hw, SUPPORTS_TX_FRAG); 392 393 hw->max_tx_fragments = 4; 394 395 if (phy->mt76->cap.has_2ghz) { 396 phy->mt76->sband_2g.sband.ht_cap.cap |= 397 IEEE80211_HT_CAP_LDPC_CODING | 398 IEEE80211_HT_CAP_MAX_AMSDU; 399 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 400 IEEE80211_HT_MPDU_DENSITY_4; 401 } 402 403 if (phy->mt76->cap.has_5ghz) { 404 struct ieee80211_sta_vht_cap *vht_cap; 405 406 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 407 phy->mt76->sband_5g.sband.ht_cap.cap |= 408 IEEE80211_HT_CAP_LDPC_CODING | 409 IEEE80211_HT_CAP_MAX_AMSDU; 410 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 411 IEEE80211_HT_MPDU_DENSITY_4; 412 413 if (is_mt7915(&dev->mt76)) { 414 vht_cap->cap |= 415 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 416 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 417 418 if (!dev->dbdc_support) 419 vht_cap->cap |= 420 IEEE80211_VHT_CAP_SHORT_GI_160 | 421 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 422 } else { 423 vht_cap->cap |= 424 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 425 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 426 427 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 428 vht_cap->cap |= 429 IEEE80211_VHT_CAP_SHORT_GI_160 | 430 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 431 } 432 433 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 434 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 435 } 436 437 mt76_set_stream_caps(phy->mt76, true); 438 mt7915_set_stream_vht_txbf_caps(phy); 439 mt7915_set_stream_he_caps(phy); 440 441 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 442 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 443 444 /* init led callbacks */ 445 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 446 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 447 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 448 } 449 } 450 451 static void 452 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 453 { 454 u32 mask, set; 455 456 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 457 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 458 mt76_set(dev, MT_TMAC_CTCR0(band), 459 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 460 MT_TMAC_CTCR0_INS_DDLMT_EN); 461 462 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 463 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 464 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 465 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 466 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 467 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 468 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 469 470 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 471 MT_MDP_RCFR1_RX_DROPPED_UCAST | 472 MT_MDP_RCFR1_RX_DROPPED_MCAST; 473 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 474 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 475 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 476 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 477 478 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 479 480 /* mt7915: disable rx rate report by default due to hw issues */ 481 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 482 483 /* clear estimated value of EIFS for Rx duration & OBSS time */ 484 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 485 486 /* clear backoff time for Rx duration */ 487 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 488 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 489 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 490 MT_WF_RMAC_MIB_QOS01_BACKOFF); 491 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 492 MT_WF_RMAC_MIB_QOS23_BACKOFF); 493 494 /* clear backoff time and set software compensation for OBSS time */ 495 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 496 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 497 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 498 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 499 500 /* filter out non-resp frames and get instanstaeous signal reporting */ 501 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 502 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 503 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 504 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 505 506 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 507 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 508 */ 509 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 510 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 511 } 512 513 static void 514 mt7915_init_led_mux(struct mt7915_dev *dev) 515 { 516 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 517 return; 518 519 if (dev->dbdc_support) { 520 switch (mt76_chip(&dev->mt76)) { 521 case 0x7915: 522 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 523 GENMASK(11, 8), 4); 524 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 525 GENMASK(11, 8), 4); 526 break; 527 case 0x7986: 528 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 529 GENMASK(7, 4), 1); 530 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 531 GENMASK(11, 8), 1); 532 break; 533 case 0x7916: 534 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 535 GENMASK(27, 24), 3); 536 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 537 GENMASK(31, 28), 3); 538 break; 539 default: 540 break; 541 } 542 } else if (dev->mphy.leds.pin) { 543 switch (mt76_chip(&dev->mt76)) { 544 case 0x7915: 545 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 546 GENMASK(11, 8), 4); 547 break; 548 case 0x7986: 549 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 550 GENMASK(11, 8), 1); 551 break; 552 case 0x7916: 553 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 554 GENMASK(31, 28), 3); 555 break; 556 default: 557 break; 558 } 559 } else { 560 switch (mt76_chip(&dev->mt76)) { 561 case 0x7915: 562 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 563 GENMASK(11, 8), 4); 564 break; 565 case 0x7986: 566 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 567 GENMASK(7, 4), 1); 568 break; 569 case 0x7916: 570 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 571 GENMASK(27, 24), 3); 572 break; 573 default: 574 break; 575 } 576 } 577 } 578 579 void mt7915_mac_init(struct mt7915_dev *dev) 580 { 581 int i; 582 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 583 584 /* config pse qid6 wfdma port selection */ 585 if (!is_mt7915(&dev->mt76) && dev->hif2) 586 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 587 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 588 589 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 590 591 if (!is_mt7915(&dev->mt76)) 592 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 593 else 594 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); 595 596 /* enable hardware de-agg */ 597 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 598 599 for (i = 0; i < mt7915_wtbl_size(dev); i++) 600 mt7915_mac_wtbl_update(dev, i, 601 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 602 for (i = 0; i < 2; i++) 603 mt7915_mac_init_band(dev, i); 604 605 mt7915_init_led_mux(dev); 606 } 607 608 int mt7915_txbf_init(struct mt7915_dev *dev) 609 { 610 int ret; 611 612 if (dev->dbdc_support) { 613 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 614 if (ret) 615 return ret; 616 } 617 618 /* trigger sounding packets */ 619 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 620 if (ret) 621 return ret; 622 623 /* enable eBF */ 624 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 625 } 626 627 static struct mt7915_phy * 628 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 629 { 630 struct mt7915_phy *phy; 631 struct mt76_phy *mphy; 632 633 if (!dev->dbdc_support) 634 return NULL; 635 636 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 637 if (!mphy) 638 return ERR_PTR(-ENOMEM); 639 640 phy = mphy->priv; 641 phy->dev = dev; 642 phy->mt76 = mphy; 643 644 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 645 phy->mt76->band_idx = 1; 646 647 return phy; 648 } 649 650 static int 651 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 652 { 653 struct mt76_phy *mphy = phy->mt76; 654 int ret; 655 656 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 657 658 mt7915_eeprom_parse_hw_cap(dev, phy); 659 660 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 661 ETH_ALEN); 662 /* Make the secondary PHY MAC address local without overlapping with 663 * the usual MAC address allocation scheme on multiple virtual interfaces 664 */ 665 if (!is_valid_ether_addr(mphy->macaddr)) { 666 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 667 ETH_ALEN); 668 mphy->macaddr[0] |= 2; 669 mphy->macaddr[0] ^= BIT(7); 670 } 671 mt76_eeprom_override(mphy); 672 673 /* init wiphy according to mphy and phy */ 674 mt7915_init_wiphy(phy); 675 676 ret = mt76_register_phy(mphy, true, mt76_rates, 677 ARRAY_SIZE(mt76_rates)); 678 if (ret) 679 return ret; 680 681 ret = mt7915_thermal_init(phy); 682 if (ret) 683 goto unreg; 684 685 mt7915_init_debugfs(phy); 686 687 return 0; 688 689 unreg: 690 mt76_unregister_phy(mphy); 691 return ret; 692 } 693 694 static void mt7915_init_work(struct work_struct *work) 695 { 696 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 697 init_work); 698 699 mt7915_mcu_set_eeprom(dev); 700 mt7915_mac_init(dev); 701 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 702 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 703 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 704 mt7915_txbf_init(dev); 705 } 706 707 void mt7915_wfsys_reset(struct mt7915_dev *dev) 708 { 709 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 710 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 711 712 if (is_mt7915(&dev->mt76)) { 713 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 714 715 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 716 717 /* change to software control */ 718 val |= MT_TOP_PWR_SW_RST; 719 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 720 721 /* reset wfsys */ 722 val &= ~MT_TOP_PWR_SW_RST; 723 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 724 725 /* release wfsys then mcu re-executes romcode */ 726 val |= MT_TOP_PWR_SW_RST; 727 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 728 729 /* switch to hw control */ 730 val &= ~MT_TOP_PWR_SW_RST; 731 val |= MT_TOP_PWR_HW_CTRL; 732 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 733 734 /* check whether mcu resets to default */ 735 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 736 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 737 1000)) { 738 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 739 return; 740 } 741 742 /* wfsys reset won't clear host registers */ 743 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 744 745 msleep(100); 746 } else if (is_mt798x(&dev->mt76)) { 747 mt7986_wmac_disable(dev); 748 msleep(20); 749 750 mt7986_wmac_enable(dev); 751 msleep(20); 752 } else { 753 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 754 msleep(20); 755 756 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 757 msleep(20); 758 } 759 } 760 761 static bool mt7915_band_config(struct mt7915_dev *dev) 762 { 763 bool ret = true; 764 765 dev->phy.mt76->band_idx = 0; 766 767 if (is_mt798x(&dev->mt76)) { 768 u32 sku = mt7915_check_adie(dev, true); 769 770 /* 771 * for mt7986, dbdc support is determined by the number 772 * of adie chips and the main phy is bound to band1 when 773 * dbdc is disabled. 774 */ 775 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 776 dev->phy.mt76->band_idx = 1; 777 ret = false; 778 } 779 } else { 780 ret = is_mt7915(&dev->mt76) ? 781 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 782 } 783 784 return ret; 785 } 786 787 static int 788 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 789 { 790 int ret, idx; 791 792 mt76_wr(dev, MT_INT_MASK_CSR, 0); 793 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 794 795 INIT_WORK(&dev->init_work, mt7915_init_work); 796 797 ret = mt7915_dma_init(dev, phy2); 798 if (ret) 799 return ret; 800 801 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 802 803 ret = mt7915_mcu_init(dev); 804 if (ret) 805 return ret; 806 807 ret = mt7915_eeprom_init(dev); 808 if (ret < 0) 809 return ret; 810 811 if (dev->flash_mode) { 812 ret = mt7915_mcu_apply_group_cal(dev); 813 if (ret) 814 return ret; 815 } 816 817 /* Beacon and mgmt frames should occupy wcid 0 */ 818 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 819 if (idx) 820 return -ENOSPC; 821 822 dev->mt76.global_wcid.idx = idx; 823 dev->mt76.global_wcid.hw_key_idx = -1; 824 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 825 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 826 827 return 0; 828 } 829 830 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 831 { 832 int sts; 833 u32 *cap; 834 835 if (!phy->mt76->cap.has_5ghz) 836 return; 837 838 sts = hweight8(phy->mt76->chainmask); 839 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 840 841 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 842 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 843 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 844 sts - 1); 845 846 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 847 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 848 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 849 850 if (sts < 2) 851 return; 852 853 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 854 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 855 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 856 sts - 1); 857 } 858 859 static void 860 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 861 struct ieee80211_sta_he_cap *he_cap, int vif) 862 { 863 struct mt7915_dev *dev = phy->dev; 864 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 865 int sts = hweight8(phy->mt76->chainmask); 866 u8 c, sts_160 = sts; 867 868 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 869 if (is_mt7915(&dev->mt76)) { 870 if (!dev->dbdc_support) 871 sts_160 /= 2; 872 else 873 sts_160 = 0; 874 } 875 876 #ifdef CONFIG_MAC80211_MESH 877 if (vif == NL80211_IFTYPE_MESH_POINT) 878 return; 879 #endif 880 881 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 882 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 883 884 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 885 if (sts_160) 886 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 887 elem->phy_cap_info[5] &= ~c; 888 889 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 890 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 891 elem->phy_cap_info[6] &= ~c; 892 893 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 894 895 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 896 if (!is_mt7915(&dev->mt76)) 897 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 898 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 899 elem->phy_cap_info[2] |= c; 900 901 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 902 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 903 if (sts_160) 904 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 905 elem->phy_cap_info[4] |= c; 906 907 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 908 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 909 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 910 911 if (vif == NL80211_IFTYPE_STATION) 912 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 913 914 elem->phy_cap_info[6] |= c; 915 916 if (sts < 2) 917 return; 918 919 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 920 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 921 922 if (vif != NL80211_IFTYPE_AP) 923 return; 924 925 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 926 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 927 928 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 929 sts - 1); 930 if (sts_160) 931 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 932 sts_160 - 1); 933 elem->phy_cap_info[5] |= c; 934 935 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 936 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 937 elem->phy_cap_info[6] |= c; 938 939 if (!is_mt7915(&dev->mt76)) { 940 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 941 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 942 elem->phy_cap_info[7] |= c; 943 } 944 } 945 946 static int 947 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 948 struct ieee80211_sband_iftype_data *data) 949 { 950 struct mt7915_dev *dev = phy->dev; 951 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 952 u16 mcs_map = 0; 953 u16 mcs_map_160 = 0; 954 u8 nss_160; 955 956 if (!is_mt7915(&dev->mt76)) 957 nss_160 = nss; 958 else if (!dev->dbdc_support) 959 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 960 nss_160 = nss / 2; 961 else 962 /* Can't do 160MHz with mt7915 dbdc */ 963 nss_160 = 0; 964 965 for (i = 0; i < 8; i++) { 966 if (i < nss) 967 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 968 else 969 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 970 971 if (i < nss_160) 972 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 973 else 974 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 975 } 976 977 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 978 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 979 struct ieee80211_he_cap_elem *he_cap_elem = 980 &he_cap->he_cap_elem; 981 struct ieee80211_he_mcs_nss_supp *he_mcs = 982 &he_cap->he_mcs_nss_supp; 983 984 switch (i) { 985 case NL80211_IFTYPE_STATION: 986 case NL80211_IFTYPE_AP: 987 #ifdef CONFIG_MAC80211_MESH 988 case NL80211_IFTYPE_MESH_POINT: 989 #endif 990 break; 991 default: 992 continue; 993 } 994 995 data[idx].types_mask = BIT(i); 996 he_cap->has_he = true; 997 998 he_cap_elem->mac_cap_info[0] = 999 IEEE80211_HE_MAC_CAP0_HTC_HE; 1000 he_cap_elem->mac_cap_info[3] = 1001 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1002 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1003 he_cap_elem->mac_cap_info[4] = 1004 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1005 1006 if (band == NL80211_BAND_2GHZ) 1007 he_cap_elem->phy_cap_info[0] = 1008 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1009 else if (nss_160) 1010 he_cap_elem->phy_cap_info[0] = 1011 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1012 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1013 else 1014 he_cap_elem->phy_cap_info[0] = 1015 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1016 1017 he_cap_elem->phy_cap_info[1] = 1018 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1019 he_cap_elem->phy_cap_info[2] = 1020 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1021 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1022 1023 switch (i) { 1024 case NL80211_IFTYPE_AP: 1025 he_cap_elem->mac_cap_info[0] |= 1026 IEEE80211_HE_MAC_CAP0_TWT_RES; 1027 he_cap_elem->mac_cap_info[2] |= 1028 IEEE80211_HE_MAC_CAP2_BSR; 1029 he_cap_elem->mac_cap_info[4] |= 1030 IEEE80211_HE_MAC_CAP4_BQR; 1031 he_cap_elem->mac_cap_info[5] |= 1032 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1033 he_cap_elem->phy_cap_info[3] |= 1034 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1035 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1036 he_cap_elem->phy_cap_info[6] |= 1037 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1038 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1039 he_cap_elem->phy_cap_info[9] |= 1040 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1041 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1042 break; 1043 case NL80211_IFTYPE_STATION: 1044 he_cap_elem->mac_cap_info[1] |= 1045 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1046 1047 if (band == NL80211_BAND_2GHZ) 1048 he_cap_elem->phy_cap_info[0] |= 1049 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1050 else 1051 he_cap_elem->phy_cap_info[0] |= 1052 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1053 1054 he_cap_elem->phy_cap_info[1] |= 1055 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1056 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1057 he_cap_elem->phy_cap_info[3] |= 1058 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1059 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1060 he_cap_elem->phy_cap_info[6] |= 1061 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1062 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1063 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1064 he_cap_elem->phy_cap_info[7] |= 1065 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1066 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1067 he_cap_elem->phy_cap_info[8] |= 1068 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1069 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1070 if (nss_160) 1071 he_cap_elem->phy_cap_info[8] |= 1072 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1073 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1074 he_cap_elem->phy_cap_info[9] |= 1075 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1076 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1077 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1078 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1079 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1080 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1081 break; 1082 } 1083 1084 memset(he_mcs, 0, sizeof(*he_mcs)); 1085 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1086 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1087 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1088 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1089 1090 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1091 1092 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1093 if (he_cap_elem->phy_cap_info[6] & 1094 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1095 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1096 } else { 1097 he_cap_elem->phy_cap_info[9] |= 1098 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1099 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1100 } 1101 1102 if (band == NL80211_BAND_6GHZ) { 1103 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1104 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1105 1106 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1107 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1108 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1109 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1110 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1111 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1112 1113 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1114 } 1115 1116 idx++; 1117 } 1118 1119 return idx; 1120 } 1121 1122 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1123 { 1124 struct ieee80211_sband_iftype_data *data; 1125 struct ieee80211_supported_band *band; 1126 int n; 1127 1128 if (phy->mt76->cap.has_2ghz) { 1129 data = phy->iftype[NL80211_BAND_2GHZ]; 1130 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1131 1132 band = &phy->mt76->sband_2g.sband; 1133 band->iftype_data = data; 1134 band->n_iftype_data = n; 1135 } 1136 1137 if (phy->mt76->cap.has_5ghz) { 1138 data = phy->iftype[NL80211_BAND_5GHZ]; 1139 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1140 1141 band = &phy->mt76->sband_5g.sband; 1142 band->iftype_data = data; 1143 band->n_iftype_data = n; 1144 } 1145 1146 if (phy->mt76->cap.has_6ghz) { 1147 data = phy->iftype[NL80211_BAND_6GHZ]; 1148 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1149 1150 band = &phy->mt76->sband_6g.sband; 1151 band->iftype_data = data; 1152 band->n_iftype_data = n; 1153 } 1154 } 1155 1156 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1157 { 1158 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1159 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1160 1161 if (!phy) 1162 return; 1163 1164 mt7915_unregister_thermal(phy); 1165 mt76_unregister_phy(mphy); 1166 ieee80211_free_hw(mphy->hw); 1167 } 1168 1169 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1170 { 1171 mt7915_mcu_exit(dev); 1172 mt76_connac2_tx_token_put(&dev->mt76); 1173 mt7915_dma_cleanup(dev); 1174 tasklet_disable(&dev->mt76.irq_tasklet); 1175 1176 if (is_mt798x(&dev->mt76)) 1177 mt7986_wmac_disable(dev); 1178 } 1179 1180 int mt7915_register_device(struct mt7915_dev *dev) 1181 { 1182 struct mt7915_phy *phy2; 1183 int ret; 1184 1185 dev->phy.dev = dev; 1186 dev->phy.mt76 = &dev->mt76.phy; 1187 dev->mt76.phy.priv = &dev->phy; 1188 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1189 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1190 INIT_LIST_HEAD(&dev->sta_rc_list); 1191 INIT_LIST_HEAD(&dev->twt_list); 1192 1193 init_waitqueue_head(&dev->reset_wait); 1194 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1195 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1196 mutex_init(&dev->dump_mutex); 1197 1198 dev->dbdc_support = mt7915_band_config(dev); 1199 1200 phy2 = mt7915_alloc_ext_phy(dev); 1201 if (IS_ERR(phy2)) 1202 return PTR_ERR(phy2); 1203 1204 ret = mt7915_init_hardware(dev, phy2); 1205 if (ret) 1206 goto free_phy2; 1207 1208 mt7915_init_wiphy(&dev->phy); 1209 1210 #ifdef CONFIG_NL80211_TESTMODE 1211 dev->mt76.test_ops = &mt7915_testmode_ops; 1212 #endif 1213 1214 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1215 ARRAY_SIZE(mt76_rates)); 1216 if (ret) 1217 goto stop_hw; 1218 1219 ret = mt7915_thermal_init(&dev->phy); 1220 if (ret) 1221 goto unreg_dev; 1222 1223 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1224 1225 if (phy2) { 1226 ret = mt7915_register_ext_phy(dev, phy2); 1227 if (ret) 1228 goto unreg_thermal; 1229 } 1230 1231 dev->recovery.hw_init_done = true; 1232 1233 ret = mt7915_init_debugfs(&dev->phy); 1234 if (ret) 1235 goto unreg_thermal; 1236 1237 ret = mt7915_coredump_register(dev); 1238 if (ret) 1239 goto unreg_thermal; 1240 1241 return 0; 1242 1243 unreg_thermal: 1244 mt7915_unregister_thermal(&dev->phy); 1245 unreg_dev: 1246 mt76_unregister_device(&dev->mt76); 1247 stop_hw: 1248 mt7915_stop_hardware(dev); 1249 free_phy2: 1250 if (phy2) 1251 ieee80211_free_hw(phy2->mt76->hw); 1252 return ret; 1253 } 1254 1255 void mt7915_unregister_device(struct mt7915_dev *dev) 1256 { 1257 mt7915_unregister_ext_phy(dev); 1258 mt7915_coredump_unregister(dev); 1259 mt7915_unregister_thermal(&dev->phy); 1260 mt76_unregister_device(&dev->mt76); 1261 mt7915_stop_hardware(dev); 1262 1263 mt76_free_device(&dev->mt76); 1264 } 1265