1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/thermal.h> 8 #include "mt7915.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "coredump.h" 12 #include "eeprom.h" 13 14 static const struct ieee80211_iface_limit if_limits[] = { 15 { 16 .max = 1, 17 .types = BIT(NL80211_IFTYPE_ADHOC) 18 }, { 19 .max = 16, 20 .types = BIT(NL80211_IFTYPE_AP) 21 #ifdef CONFIG_MAC80211_MESH 22 | BIT(NL80211_IFTYPE_MESH_POINT) 23 #endif 24 }, { 25 .max = MT7915_MAX_INTERFACES, 26 .types = BIT(NL80211_IFTYPE_STATION) 27 } 28 }; 29 30 static const struct ieee80211_iface_combination if_comb[] = { 31 { 32 .limits = if_limits, 33 .n_limits = ARRAY_SIZE(if_limits), 34 .max_interfaces = MT7915_MAX_INTERFACES, 35 .num_different_channels = 1, 36 .beacon_int_infra_match = true, 37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 38 BIT(NL80211_CHAN_WIDTH_20) | 39 BIT(NL80211_CHAN_WIDTH_40) | 40 BIT(NL80211_CHAN_WIDTH_80) | 41 BIT(NL80211_CHAN_WIDTH_160), 42 } 43 }; 44 45 static ssize_t mt7915_thermal_temp_show(struct device *dev, 46 struct device_attribute *attr, 47 char *buf) 48 { 49 struct mt7915_phy *phy = dev_get_drvdata(dev); 50 int i = to_sensor_dev_attr(attr)->index; 51 int temperature; 52 53 switch (i) { 54 case 0: 55 temperature = mt7915_mcu_get_temperature(phy); 56 if (temperature < 0) 57 return temperature; 58 /* display in millidegree celcius */ 59 return sprintf(buf, "%u\n", temperature * 1000); 60 case 1: 61 case 2: 62 return sprintf(buf, "%u\n", 63 phy->throttle_temp[i - 1] * 1000); 64 case 3: 65 return sprintf(buf, "%hhu\n", phy->throttle_state); 66 default: 67 return -EINVAL; 68 } 69 } 70 71 static ssize_t mt7915_thermal_temp_store(struct device *dev, 72 struct device_attribute *attr, 73 const char *buf, size_t count) 74 { 75 struct mt7915_phy *phy = dev_get_drvdata(dev); 76 int ret, i = to_sensor_dev_attr(attr)->index; 77 long val; 78 79 ret = kstrtol(buf, 10, &val); 80 if (ret < 0) 81 return ret; 82 83 mutex_lock(&phy->dev->mt76.mutex); 84 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 85 86 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 87 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 88 (i - 1 == MT7915_MAX_TEMP_IDX && 89 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 90 dev_err(phy->dev->mt76.dev, 91 "temp1_max shall be greater than temp1_crit."); 92 return -EINVAL; 93 } 94 95 phy->throttle_temp[i - 1] = val; 96 mutex_unlock(&phy->dev->mt76.mutex); 97 98 ret = mt7915_mcu_set_thermal_protect(phy); 99 if (ret) 100 return ret; 101 102 return count; 103 } 104 105 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 106 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 107 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 108 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 109 110 static struct attribute *mt7915_hwmon_attrs[] = { 111 &sensor_dev_attr_temp1_input.dev_attr.attr, 112 &sensor_dev_attr_temp1_crit.dev_attr.attr, 113 &sensor_dev_attr_temp1_max.dev_attr.attr, 114 &sensor_dev_attr_throttle1.dev_attr.attr, 115 NULL, 116 }; 117 ATTRIBUTE_GROUPS(mt7915_hwmon); 118 119 static int 120 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 121 unsigned long *state) 122 { 123 *state = MT7915_CDEV_THROTTLE_MAX; 124 125 return 0; 126 } 127 128 static int 129 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 130 unsigned long *state) 131 { 132 struct mt7915_phy *phy = cdev->devdata; 133 134 *state = phy->cdev_state; 135 136 return 0; 137 } 138 139 static int 140 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 141 unsigned long state) 142 { 143 struct mt7915_phy *phy = cdev->devdata; 144 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 145 int ret; 146 147 if (state > MT7915_CDEV_THROTTLE_MAX) { 148 dev_err(phy->dev->mt76.dev, 149 "please specify a valid throttling state\n"); 150 return -EINVAL; 151 } 152 153 if (state == phy->cdev_state) 154 return 0; 155 156 /* 157 * cooling_device convention: 0 = no cooling, more = more cooling 158 * mcu convention: 1 = max cooling, more = less cooling 159 */ 160 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 161 if (ret) 162 return ret; 163 164 phy->cdev_state = state; 165 166 return 0; 167 } 168 169 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 170 .get_max_state = mt7915_thermal_get_max_throttle_state, 171 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 172 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 173 }; 174 175 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 176 { 177 struct wiphy *wiphy = phy->mt76->hw->wiphy; 178 179 if (!phy->cdev) 180 return; 181 182 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 183 thermal_cooling_device_unregister(phy->cdev); 184 } 185 186 static int mt7915_thermal_init(struct mt7915_phy *phy) 187 { 188 struct wiphy *wiphy = phy->mt76->hw->wiphy; 189 struct thermal_cooling_device *cdev; 190 struct device *hwmon; 191 const char *name; 192 193 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 194 wiphy_name(wiphy)); 195 196 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 197 if (!IS_ERR(cdev)) { 198 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 199 "cooling_device") < 0) 200 thermal_cooling_device_unregister(cdev); 201 else 202 phy->cdev = cdev; 203 } 204 205 if (!IS_REACHABLE(CONFIG_HWMON)) 206 return 0; 207 208 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 209 mt7915_hwmon_groups); 210 if (IS_ERR(hwmon)) 211 return PTR_ERR(hwmon); 212 213 /* initialize critical/maximum high temperature */ 214 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 215 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 216 217 return 0; 218 } 219 220 static void mt7915_led_set_config(struct led_classdev *led_cdev, 221 u8 delay_on, u8 delay_off) 222 { 223 struct mt7915_dev *dev; 224 struct mt76_phy *mphy; 225 u32 val; 226 227 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 228 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 229 230 /* set PWM mode */ 231 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 232 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 233 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 234 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 235 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 236 237 /* enable LED */ 238 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 239 240 /* control LED */ 241 val = MT_LED_CTRL_KICK; 242 if (dev->mphy.leds.al) 243 val |= MT_LED_CTRL_POLARITY; 244 if (mphy->band_idx) 245 val |= MT_LED_CTRL_BAND; 246 247 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 248 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 249 } 250 251 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 252 unsigned long *delay_on, 253 unsigned long *delay_off) 254 { 255 u16 delta_on = 0, delta_off = 0; 256 257 #define HW_TICK 10 258 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 259 260 if (*delay_on) 261 delta_on = TO_HW_TICK(*delay_on); 262 if (*delay_off) 263 delta_off = TO_HW_TICK(*delay_off); 264 265 mt7915_led_set_config(led_cdev, delta_on, delta_off); 266 267 return 0; 268 } 269 270 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 271 enum led_brightness brightness) 272 { 273 if (!brightness) 274 mt7915_led_set_config(led_cdev, 0, 0xff); 275 else 276 mt7915_led_set_config(led_cdev, 0xff, 0); 277 } 278 279 void mt7915_init_txpower(struct mt7915_dev *dev, 280 struct ieee80211_supported_band *sband) 281 { 282 int i, n_chains = hweight8(dev->mphy.antenna_mask); 283 int nss_delta = mt76_tx_power_nss_delta(n_chains); 284 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 285 struct mt76_power_limits limits; 286 287 for (i = 0; i < sband->n_channels; i++) { 288 struct ieee80211_channel *chan = &sband->channels[i]; 289 u32 target_power = 0; 290 int j; 291 292 for (j = 0; j < n_chains; j++) { 293 u32 val; 294 295 val = mt7915_eeprom_get_target_power(dev, chan, j); 296 target_power = max(target_power, val); 297 } 298 299 target_power += pwr_delta; 300 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 301 &limits, 302 target_power); 303 target_power += nss_delta; 304 target_power = DIV_ROUND_UP(target_power, 2); 305 chan->max_power = min_t(int, chan->max_reg_power, 306 target_power); 307 chan->orig_mpwr = target_power; 308 } 309 } 310 311 static void 312 mt7915_regd_notifier(struct wiphy *wiphy, 313 struct regulatory_request *request) 314 { 315 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 316 struct mt7915_dev *dev = mt7915_hw_dev(hw); 317 struct mt76_phy *mphy = hw->priv; 318 struct mt7915_phy *phy = mphy->priv; 319 320 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 321 dev->mt76.region = request->dfs_region; 322 323 if (dev->mt76.region == NL80211_DFS_UNSET) 324 mt7915_mcu_rdd_background_enable(phy, NULL); 325 326 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 327 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 328 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 329 330 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 331 mt7915_dfs_init_radar_detector(phy); 332 } 333 334 static void 335 mt7915_init_wiphy(struct mt7915_phy *phy) 336 { 337 struct mt76_phy *mphy = phy->mt76; 338 struct ieee80211_hw *hw = mphy->hw; 339 struct mt76_dev *mdev = &phy->dev->mt76; 340 struct wiphy *wiphy = hw->wiphy; 341 struct mt7915_dev *dev = phy->dev; 342 343 hw->queues = 4; 344 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 345 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 346 hw->netdev_features = NETIF_F_RXCSUM; 347 348 hw->radiotap_timestamp.units_pos = 349 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 350 351 phy->slottime = 9; 352 353 hw->sta_data_size = sizeof(struct mt7915_sta); 354 hw->vif_data_size = sizeof(struct mt7915_vif); 355 356 wiphy->iface_combinations = if_comb; 357 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 358 wiphy->reg_notifier = mt7915_regd_notifier; 359 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 360 wiphy->mbssid_max_interfaces = 16; 361 362 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 363 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 364 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 365 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 366 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 367 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 368 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 369 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 370 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 371 372 if (!is_mt7915(&dev->mt76)) 373 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 374 375 if (!mdev->dev->of_node || 376 !of_property_read_bool(mdev->dev->of_node, 377 "mediatek,disable-radar-background")) 378 wiphy_ext_feature_set(wiphy, 379 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 380 381 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 382 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 383 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 384 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 385 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 386 387 hw->max_tx_fragments = 4; 388 389 if (phy->mt76->cap.has_2ghz) { 390 phy->mt76->sband_2g.sband.ht_cap.cap |= 391 IEEE80211_HT_CAP_LDPC_CODING | 392 IEEE80211_HT_CAP_MAX_AMSDU; 393 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 394 IEEE80211_HT_MPDU_DENSITY_4; 395 } 396 397 if (phy->mt76->cap.has_5ghz) { 398 struct ieee80211_sta_vht_cap *vht_cap; 399 400 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 401 phy->mt76->sband_5g.sband.ht_cap.cap |= 402 IEEE80211_HT_CAP_LDPC_CODING | 403 IEEE80211_HT_CAP_MAX_AMSDU; 404 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 405 IEEE80211_HT_MPDU_DENSITY_4; 406 407 if (is_mt7915(&dev->mt76)) { 408 vht_cap->cap |= 409 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 410 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 411 412 if (!dev->dbdc_support) 413 vht_cap->cap |= 414 IEEE80211_VHT_CAP_SHORT_GI_160 | 415 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 416 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 417 } else { 418 vht_cap->cap |= 419 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 420 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 421 422 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 423 vht_cap->cap |= 424 IEEE80211_VHT_CAP_SHORT_GI_160 | 425 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 426 } 427 428 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 429 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 430 } 431 432 mt76_set_stream_caps(phy->mt76, true); 433 mt7915_set_stream_vht_txbf_caps(phy); 434 mt7915_set_stream_he_caps(phy); 435 436 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 437 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 438 439 /* init led callbacks */ 440 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 441 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 442 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 443 } 444 } 445 446 static void 447 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 448 { 449 u32 mask, set; 450 451 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 452 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 453 mt76_set(dev, MT_TMAC_CTCR0(band), 454 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 455 MT_TMAC_CTCR0_INS_DDLMT_EN); 456 457 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 458 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 459 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 460 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 461 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 462 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 463 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 464 465 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 466 MT_MDP_RCFR1_RX_DROPPED_UCAST | 467 MT_MDP_RCFR1_RX_DROPPED_MCAST; 468 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 469 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 470 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 471 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 472 473 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 474 475 /* mt7915: disable rx rate report by default due to hw issues */ 476 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 477 478 /* clear estimated value of EIFS for Rx duration & OBSS time */ 479 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 480 481 /* clear backoff time for Rx duration */ 482 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 483 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 484 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 485 MT_WF_RMAC_MIB_QOS01_BACKOFF); 486 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 487 MT_WF_RMAC_MIB_QOS23_BACKOFF); 488 489 /* clear backoff time and set software compensation for OBSS time */ 490 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 491 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 492 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 493 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 494 495 /* filter out non-resp frames and get instanstaeous signal reporting */ 496 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 497 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 498 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 499 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 500 } 501 502 static void 503 mt7915_init_led_mux(struct mt7915_dev *dev) 504 { 505 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 506 return; 507 508 if (dev->dbdc_support) { 509 switch (mt76_chip(&dev->mt76)) { 510 case 0x7915: 511 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 512 GENMASK(11, 8), 4); 513 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 514 GENMASK(11, 8), 4); 515 break; 516 case 0x7986: 517 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 518 GENMASK(7, 4), 1); 519 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 520 GENMASK(11, 8), 1); 521 break; 522 case 0x7916: 523 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 524 GENMASK(27, 24), 3); 525 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 526 GENMASK(31, 28), 3); 527 break; 528 default: 529 break; 530 } 531 } else if (dev->mphy.leds.pin) { 532 switch (mt76_chip(&dev->mt76)) { 533 case 0x7915: 534 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 535 GENMASK(11, 8), 4); 536 break; 537 case 0x7986: 538 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 539 GENMASK(11, 8), 1); 540 break; 541 case 0x7916: 542 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 543 GENMASK(31, 28), 3); 544 break; 545 default: 546 break; 547 } 548 } else { 549 switch (mt76_chip(&dev->mt76)) { 550 case 0x7915: 551 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 552 GENMASK(11, 8), 4); 553 break; 554 case 0x7986: 555 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 556 GENMASK(7, 4), 1); 557 break; 558 case 0x7916: 559 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 560 GENMASK(27, 24), 3); 561 break; 562 default: 563 break; 564 } 565 } 566 } 567 568 void mt7915_mac_init(struct mt7915_dev *dev) 569 { 570 int i; 571 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 572 573 /* config pse qid6 wfdma port selection */ 574 if (!is_mt7915(&dev->mt76) && dev->hif2) 575 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 576 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 577 578 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 579 580 if (!is_mt7915(&dev->mt76)) 581 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 582 583 /* enable hardware de-agg */ 584 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 585 586 for (i = 0; i < mt7915_wtbl_size(dev); i++) 587 mt7915_mac_wtbl_update(dev, i, 588 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 589 for (i = 0; i < 2; i++) 590 mt7915_mac_init_band(dev, i); 591 592 mt7915_init_led_mux(dev); 593 } 594 595 int mt7915_txbf_init(struct mt7915_dev *dev) 596 { 597 int ret; 598 599 if (dev->dbdc_support) { 600 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 601 if (ret) 602 return ret; 603 } 604 605 /* trigger sounding packets */ 606 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 607 if (ret) 608 return ret; 609 610 /* enable eBF */ 611 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 612 } 613 614 static struct mt7915_phy * 615 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 616 { 617 struct mt7915_phy *phy; 618 struct mt76_phy *mphy; 619 620 if (!dev->dbdc_support) 621 return NULL; 622 623 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 624 if (!mphy) 625 return ERR_PTR(-ENOMEM); 626 627 phy = mphy->priv; 628 phy->dev = dev; 629 phy->mt76 = mphy; 630 631 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 632 phy->mt76->band_idx = 1; 633 634 return phy; 635 } 636 637 static int 638 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 639 { 640 struct mt76_phy *mphy = phy->mt76; 641 int ret; 642 643 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 644 645 mt7915_eeprom_parse_hw_cap(dev, phy); 646 647 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 648 ETH_ALEN); 649 /* Make the secondary PHY MAC address local without overlapping with 650 * the usual MAC address allocation scheme on multiple virtual interfaces 651 */ 652 if (!is_valid_ether_addr(mphy->macaddr)) { 653 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 654 ETH_ALEN); 655 mphy->macaddr[0] |= 2; 656 mphy->macaddr[0] ^= BIT(7); 657 } 658 mt76_eeprom_override(mphy); 659 660 /* init wiphy according to mphy and phy */ 661 mt7915_init_wiphy(phy); 662 663 ret = mt76_register_phy(mphy, true, mt76_rates, 664 ARRAY_SIZE(mt76_rates)); 665 if (ret) 666 return ret; 667 668 ret = mt7915_thermal_init(phy); 669 if (ret) 670 goto unreg; 671 672 mt7915_init_debugfs(phy); 673 674 return 0; 675 676 unreg: 677 mt76_unregister_phy(mphy); 678 return ret; 679 } 680 681 static void mt7915_init_work(struct work_struct *work) 682 { 683 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 684 init_work); 685 686 mt7915_mcu_set_eeprom(dev); 687 mt7915_mac_init(dev); 688 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 689 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 690 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 691 mt7915_txbf_init(dev); 692 } 693 694 void mt7915_wfsys_reset(struct mt7915_dev *dev) 695 { 696 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 697 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 698 699 if (is_mt7915(&dev->mt76)) { 700 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 701 702 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 703 704 /* change to software control */ 705 val |= MT_TOP_PWR_SW_RST; 706 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 707 708 /* reset wfsys */ 709 val &= ~MT_TOP_PWR_SW_RST; 710 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 711 712 /* release wfsys then mcu re-executes romcode */ 713 val |= MT_TOP_PWR_SW_RST; 714 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 715 716 /* switch to hw control */ 717 val &= ~MT_TOP_PWR_SW_RST; 718 val |= MT_TOP_PWR_HW_CTRL; 719 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 720 721 /* check whether mcu resets to default */ 722 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 723 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 724 1000)) { 725 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 726 return; 727 } 728 729 /* wfsys reset won't clear host registers */ 730 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 731 732 msleep(100); 733 } else if (is_mt7986(&dev->mt76)) { 734 mt7986_wmac_disable(dev); 735 msleep(20); 736 737 mt7986_wmac_enable(dev); 738 msleep(20); 739 } else { 740 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 741 msleep(20); 742 743 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 744 msleep(20); 745 } 746 } 747 748 static bool mt7915_band_config(struct mt7915_dev *dev) 749 { 750 bool ret = true; 751 752 dev->phy.mt76->band_idx = 0; 753 754 if (is_mt7986(&dev->mt76)) { 755 u32 sku = mt7915_check_adie(dev, true); 756 757 /* 758 * for mt7986, dbdc support is determined by the number 759 * of adie chips and the main phy is bound to band1 when 760 * dbdc is disabled. 761 */ 762 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 763 dev->phy.mt76->band_idx = 1; 764 ret = false; 765 } 766 } else { 767 ret = is_mt7915(&dev->mt76) ? 768 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 769 } 770 771 return ret; 772 } 773 774 static int 775 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 776 { 777 int ret, idx; 778 779 mt76_wr(dev, MT_INT_MASK_CSR, 0); 780 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 781 782 INIT_WORK(&dev->init_work, mt7915_init_work); 783 784 ret = mt7915_dma_init(dev, phy2); 785 if (ret) 786 return ret; 787 788 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 789 790 ret = mt7915_mcu_init(dev); 791 if (ret) 792 return ret; 793 794 ret = mt7915_eeprom_init(dev); 795 if (ret < 0) 796 return ret; 797 798 if (dev->flash_mode) { 799 ret = mt7915_mcu_apply_group_cal(dev); 800 if (ret) 801 return ret; 802 } 803 804 /* Beacon and mgmt frames should occupy wcid 0 */ 805 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 806 if (idx) 807 return -ENOSPC; 808 809 dev->mt76.global_wcid.idx = idx; 810 dev->mt76.global_wcid.hw_key_idx = -1; 811 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 812 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 813 814 return 0; 815 } 816 817 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 818 { 819 int sts; 820 u32 *cap; 821 822 if (!phy->mt76->cap.has_5ghz) 823 return; 824 825 sts = hweight8(phy->mt76->chainmask); 826 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 827 828 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 829 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 830 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 831 sts - 1); 832 833 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 834 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 835 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 836 837 if (sts < 2) 838 return; 839 840 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 841 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 842 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 843 sts - 1); 844 } 845 846 static void 847 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 848 struct ieee80211_sta_he_cap *he_cap, int vif) 849 { 850 struct mt7915_dev *dev = phy->dev; 851 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 852 int sts = hweight8(phy->mt76->chainmask); 853 u8 c, sts_160 = sts; 854 855 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 856 if (is_mt7915(&dev->mt76)) { 857 if (!dev->dbdc_support) 858 sts_160 /= 2; 859 else 860 sts_160 = 0; 861 } 862 863 #ifdef CONFIG_MAC80211_MESH 864 if (vif == NL80211_IFTYPE_MESH_POINT) 865 return; 866 #endif 867 868 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 869 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 870 871 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 872 if (sts_160) 873 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 874 elem->phy_cap_info[5] &= ~c; 875 876 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 877 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 878 elem->phy_cap_info[6] &= ~c; 879 880 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 881 882 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 883 if (!is_mt7915(&dev->mt76)) 884 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 885 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 886 elem->phy_cap_info[2] |= c; 887 888 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 889 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 890 if (sts_160) 891 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 892 elem->phy_cap_info[4] |= c; 893 894 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 895 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 896 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 897 898 if (vif == NL80211_IFTYPE_STATION) 899 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 900 901 elem->phy_cap_info[6] |= c; 902 903 if (sts < 2) 904 return; 905 906 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 907 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 908 909 if (vif != NL80211_IFTYPE_AP) 910 return; 911 912 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 913 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 914 915 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 916 sts - 1); 917 if (sts_160) 918 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 919 sts_160 - 1); 920 elem->phy_cap_info[5] |= c; 921 922 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 923 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 924 elem->phy_cap_info[6] |= c; 925 926 if (!is_mt7915(&dev->mt76)) { 927 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 928 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 929 elem->phy_cap_info[7] |= c; 930 } 931 } 932 933 static void 934 mt7915_gen_ppe_thresh(u8 *he_ppet, int nss) 935 { 936 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */ 937 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71}; 938 939 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | 940 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, 941 ru_bit_mask); 942 943 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE * 944 nss * hweight8(ru_bit_mask) * 2; 945 ppet_size = DIV_ROUND_UP(ppet_bits, 8); 946 947 for (i = 0; i < ppet_size - 1; i++) 948 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3]; 949 950 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] & 951 (0xff >> (8 - (ppet_bits - 1) % 8)); 952 } 953 954 static int 955 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 956 struct ieee80211_sband_iftype_data *data) 957 { 958 struct mt7915_dev *dev = phy->dev; 959 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 960 u16 mcs_map = 0; 961 u16 mcs_map_160 = 0; 962 u8 nss_160; 963 964 if (!is_mt7915(&dev->mt76)) 965 nss_160 = nss; 966 else if (!dev->dbdc_support) 967 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 968 nss_160 = nss / 2; 969 else 970 /* Can't do 160MHz with mt7915 dbdc */ 971 nss_160 = 0; 972 973 for (i = 0; i < 8; i++) { 974 if (i < nss) 975 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 976 else 977 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 978 979 if (i < nss_160) 980 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 981 else 982 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 983 } 984 985 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 986 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 987 struct ieee80211_he_cap_elem *he_cap_elem = 988 &he_cap->he_cap_elem; 989 struct ieee80211_he_mcs_nss_supp *he_mcs = 990 &he_cap->he_mcs_nss_supp; 991 992 switch (i) { 993 case NL80211_IFTYPE_STATION: 994 case NL80211_IFTYPE_AP: 995 #ifdef CONFIG_MAC80211_MESH 996 case NL80211_IFTYPE_MESH_POINT: 997 #endif 998 break; 999 default: 1000 continue; 1001 } 1002 1003 data[idx].types_mask = BIT(i); 1004 he_cap->has_he = true; 1005 1006 he_cap_elem->mac_cap_info[0] = 1007 IEEE80211_HE_MAC_CAP0_HTC_HE; 1008 he_cap_elem->mac_cap_info[3] = 1009 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1010 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1011 he_cap_elem->mac_cap_info[4] = 1012 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1013 1014 if (band == NL80211_BAND_2GHZ) 1015 he_cap_elem->phy_cap_info[0] = 1016 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1017 else if (nss_160) 1018 he_cap_elem->phy_cap_info[0] = 1019 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1020 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1021 else 1022 he_cap_elem->phy_cap_info[0] = 1023 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1024 1025 he_cap_elem->phy_cap_info[1] = 1026 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1027 he_cap_elem->phy_cap_info[2] = 1028 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1029 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1030 1031 switch (i) { 1032 case NL80211_IFTYPE_AP: 1033 he_cap_elem->mac_cap_info[0] |= 1034 IEEE80211_HE_MAC_CAP0_TWT_RES; 1035 he_cap_elem->mac_cap_info[2] |= 1036 IEEE80211_HE_MAC_CAP2_BSR; 1037 he_cap_elem->mac_cap_info[4] |= 1038 IEEE80211_HE_MAC_CAP4_BQR; 1039 he_cap_elem->mac_cap_info[5] |= 1040 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1041 he_cap_elem->phy_cap_info[3] |= 1042 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1043 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1044 he_cap_elem->phy_cap_info[6] |= 1045 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1046 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1047 he_cap_elem->phy_cap_info[9] |= 1048 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1049 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1050 break; 1051 case NL80211_IFTYPE_STATION: 1052 he_cap_elem->mac_cap_info[1] |= 1053 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1054 1055 if (band == NL80211_BAND_2GHZ) 1056 he_cap_elem->phy_cap_info[0] |= 1057 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1058 else 1059 he_cap_elem->phy_cap_info[0] |= 1060 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1061 1062 he_cap_elem->phy_cap_info[1] |= 1063 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1064 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1065 he_cap_elem->phy_cap_info[3] |= 1066 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1067 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1068 he_cap_elem->phy_cap_info[6] |= 1069 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1070 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1071 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1072 he_cap_elem->phy_cap_info[7] |= 1073 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1074 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1075 he_cap_elem->phy_cap_info[8] |= 1076 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1077 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1078 if (nss_160) 1079 he_cap_elem->phy_cap_info[8] |= 1080 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1081 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1082 he_cap_elem->phy_cap_info[9] |= 1083 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1084 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1085 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1086 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1087 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1088 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1089 break; 1090 } 1091 1092 memset(he_mcs, 0, sizeof(*he_mcs)); 1093 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1094 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1095 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1096 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1097 1098 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1099 1100 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1101 if (he_cap_elem->phy_cap_info[6] & 1102 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1103 mt7915_gen_ppe_thresh(he_cap->ppe_thres, nss); 1104 } else { 1105 he_cap_elem->phy_cap_info[9] |= 1106 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1107 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1108 } 1109 1110 if (band == NL80211_BAND_6GHZ) { 1111 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1112 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1113 1114 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1115 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1116 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1117 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1118 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1119 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1120 1121 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1122 } 1123 1124 idx++; 1125 } 1126 1127 return idx; 1128 } 1129 1130 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1131 { 1132 struct ieee80211_sband_iftype_data *data; 1133 struct ieee80211_supported_band *band; 1134 int n; 1135 1136 if (phy->mt76->cap.has_2ghz) { 1137 data = phy->iftype[NL80211_BAND_2GHZ]; 1138 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1139 1140 band = &phy->mt76->sband_2g.sband; 1141 band->iftype_data = data; 1142 band->n_iftype_data = n; 1143 } 1144 1145 if (phy->mt76->cap.has_5ghz) { 1146 data = phy->iftype[NL80211_BAND_5GHZ]; 1147 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1148 1149 band = &phy->mt76->sband_5g.sband; 1150 band->iftype_data = data; 1151 band->n_iftype_data = n; 1152 } 1153 1154 if (phy->mt76->cap.has_6ghz) { 1155 data = phy->iftype[NL80211_BAND_6GHZ]; 1156 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1157 1158 band = &phy->mt76->sband_6g.sband; 1159 band->iftype_data = data; 1160 band->n_iftype_data = n; 1161 } 1162 } 1163 1164 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1165 { 1166 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1167 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1168 1169 if (!phy) 1170 return; 1171 1172 mt7915_unregister_thermal(phy); 1173 mt76_unregister_phy(mphy); 1174 ieee80211_free_hw(mphy->hw); 1175 } 1176 1177 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1178 { 1179 mt7915_mcu_exit(dev); 1180 mt7915_tx_token_put(dev); 1181 mt7915_dma_cleanup(dev); 1182 tasklet_disable(&dev->irq_tasklet); 1183 1184 if (is_mt7986(&dev->mt76)) 1185 mt7986_wmac_disable(dev); 1186 } 1187 1188 int mt7915_register_device(struct mt7915_dev *dev) 1189 { 1190 struct mt7915_phy *phy2; 1191 int ret; 1192 1193 dev->phy.dev = dev; 1194 dev->phy.mt76 = &dev->mt76.phy; 1195 dev->mt76.phy.priv = &dev->phy; 1196 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1197 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1198 INIT_LIST_HEAD(&dev->sta_rc_list); 1199 INIT_LIST_HEAD(&dev->sta_poll_list); 1200 INIT_LIST_HEAD(&dev->twt_list); 1201 spin_lock_init(&dev->sta_poll_lock); 1202 1203 init_waitqueue_head(&dev->reset_wait); 1204 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1205 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1206 mutex_init(&dev->dump_mutex); 1207 1208 dev->dbdc_support = mt7915_band_config(dev); 1209 1210 phy2 = mt7915_alloc_ext_phy(dev); 1211 if (IS_ERR(phy2)) 1212 return PTR_ERR(phy2); 1213 1214 ret = mt7915_init_hardware(dev, phy2); 1215 if (ret) 1216 goto free_phy2; 1217 1218 mt7915_init_wiphy(&dev->phy); 1219 1220 #ifdef CONFIG_NL80211_TESTMODE 1221 dev->mt76.test_ops = &mt7915_testmode_ops; 1222 #endif 1223 1224 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1225 ARRAY_SIZE(mt76_rates)); 1226 if (ret) 1227 goto stop_hw; 1228 1229 ret = mt7915_thermal_init(&dev->phy); 1230 if (ret) 1231 goto unreg_dev; 1232 1233 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1234 1235 if (phy2) { 1236 ret = mt7915_register_ext_phy(dev, phy2); 1237 if (ret) 1238 goto unreg_thermal; 1239 } 1240 1241 dev->recovery.hw_init_done = true; 1242 1243 ret = mt7915_init_debugfs(&dev->phy); 1244 if (ret) 1245 goto unreg_thermal; 1246 1247 ret = mt7915_coredump_register(dev); 1248 if (ret) 1249 goto unreg_thermal; 1250 1251 return 0; 1252 1253 unreg_thermal: 1254 mt7915_unregister_thermal(&dev->phy); 1255 unreg_dev: 1256 mt76_unregister_device(&dev->mt76); 1257 stop_hw: 1258 mt7915_stop_hardware(dev); 1259 free_phy2: 1260 if (phy2) 1261 ieee80211_free_hw(phy2->mt76->hw); 1262 return ret; 1263 } 1264 1265 void mt7915_unregister_device(struct mt7915_dev *dev) 1266 { 1267 mt7915_unregister_ext_phy(dev); 1268 mt7915_coredump_unregister(dev); 1269 mt7915_unregister_thermal(&dev->phy); 1270 mt76_unregister_device(&dev->mt76); 1271 mt7915_stop_hardware(dev); 1272 1273 mt76_free_device(&dev->mt76); 1274 } 1275