1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/thermal.h> 8 #include "mt7915.h" 9 #include "mac.h" 10 #include "mcu.h" 11 #include "coredump.h" 12 #include "eeprom.h" 13 14 static const struct ieee80211_iface_limit if_limits[] = { 15 { 16 .max = 1, 17 .types = BIT(NL80211_IFTYPE_ADHOC) 18 }, { 19 .max = 16, 20 .types = BIT(NL80211_IFTYPE_AP) 21 #ifdef CONFIG_MAC80211_MESH 22 | BIT(NL80211_IFTYPE_MESH_POINT) 23 #endif 24 }, { 25 .max = MT7915_MAX_INTERFACES, 26 .types = BIT(NL80211_IFTYPE_STATION) 27 } 28 }; 29 30 static const struct ieee80211_iface_combination if_comb[] = { 31 { 32 .limits = if_limits, 33 .n_limits = ARRAY_SIZE(if_limits), 34 .max_interfaces = MT7915_MAX_INTERFACES, 35 .num_different_channels = 1, 36 .beacon_int_infra_match = true, 37 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 38 BIT(NL80211_CHAN_WIDTH_20) | 39 BIT(NL80211_CHAN_WIDTH_40) | 40 BIT(NL80211_CHAN_WIDTH_80) | 41 BIT(NL80211_CHAN_WIDTH_160), 42 } 43 }; 44 45 static ssize_t mt7915_thermal_temp_show(struct device *dev, 46 struct device_attribute *attr, 47 char *buf) 48 { 49 struct mt7915_phy *phy = dev_get_drvdata(dev); 50 int i = to_sensor_dev_attr(attr)->index; 51 int temperature; 52 53 switch (i) { 54 case 0: 55 temperature = mt7915_mcu_get_temperature(phy); 56 if (temperature < 0) 57 return temperature; 58 /* display in millidegree celcius */ 59 return sprintf(buf, "%u\n", temperature * 1000); 60 case 1: 61 case 2: 62 return sprintf(buf, "%u\n", 63 phy->throttle_temp[i - 1] * 1000); 64 case 3: 65 return sprintf(buf, "%hhu\n", phy->throttle_state); 66 default: 67 return -EINVAL; 68 } 69 } 70 71 static ssize_t mt7915_thermal_temp_store(struct device *dev, 72 struct device_attribute *attr, 73 const char *buf, size_t count) 74 { 75 struct mt7915_phy *phy = dev_get_drvdata(dev); 76 int ret, i = to_sensor_dev_attr(attr)->index; 77 long val; 78 79 ret = kstrtol(buf, 10, &val); 80 if (ret < 0) 81 return ret; 82 83 mutex_lock(&phy->dev->mt76.mutex); 84 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 85 86 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 87 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 88 (i - 1 == MT7915_MAX_TEMP_IDX && 89 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 90 dev_err(phy->dev->mt76.dev, 91 "temp1_max shall be greater than temp1_crit."); 92 return -EINVAL; 93 } 94 95 phy->throttle_temp[i - 1] = val; 96 mutex_unlock(&phy->dev->mt76.mutex); 97 98 ret = mt7915_mcu_set_thermal_protect(phy); 99 if (ret) 100 return ret; 101 102 return count; 103 } 104 105 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 106 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 107 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 108 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 109 110 static struct attribute *mt7915_hwmon_attrs[] = { 111 &sensor_dev_attr_temp1_input.dev_attr.attr, 112 &sensor_dev_attr_temp1_crit.dev_attr.attr, 113 &sensor_dev_attr_temp1_max.dev_attr.attr, 114 &sensor_dev_attr_throttle1.dev_attr.attr, 115 NULL, 116 }; 117 ATTRIBUTE_GROUPS(mt7915_hwmon); 118 119 static int 120 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 121 unsigned long *state) 122 { 123 *state = MT7915_CDEV_THROTTLE_MAX; 124 125 return 0; 126 } 127 128 static int 129 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 130 unsigned long *state) 131 { 132 struct mt7915_phy *phy = cdev->devdata; 133 134 *state = phy->cdev_state; 135 136 return 0; 137 } 138 139 static int 140 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 141 unsigned long state) 142 { 143 struct mt7915_phy *phy = cdev->devdata; 144 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 145 int ret; 146 147 if (state > MT7915_CDEV_THROTTLE_MAX) { 148 dev_err(phy->dev->mt76.dev, 149 "please specify a valid throttling state\n"); 150 return -EINVAL; 151 } 152 153 if (state == phy->cdev_state) 154 return 0; 155 156 /* 157 * cooling_device convention: 0 = no cooling, more = more cooling 158 * mcu convention: 1 = max cooling, more = less cooling 159 */ 160 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 161 if (ret) 162 return ret; 163 164 phy->cdev_state = state; 165 166 return 0; 167 } 168 169 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 170 .get_max_state = mt7915_thermal_get_max_throttle_state, 171 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 172 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 173 }; 174 175 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 176 { 177 struct wiphy *wiphy = phy->mt76->hw->wiphy; 178 179 if (!phy->cdev) 180 return; 181 182 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 183 thermal_cooling_device_unregister(phy->cdev); 184 } 185 186 static int mt7915_thermal_init(struct mt7915_phy *phy) 187 { 188 struct wiphy *wiphy = phy->mt76->hw->wiphy; 189 struct thermal_cooling_device *cdev; 190 struct device *hwmon; 191 const char *name; 192 193 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 194 wiphy_name(wiphy)); 195 196 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 197 if (!IS_ERR(cdev)) { 198 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 199 "cooling_device") < 0) 200 thermal_cooling_device_unregister(cdev); 201 else 202 phy->cdev = cdev; 203 } 204 205 if (!IS_REACHABLE(CONFIG_HWMON)) 206 return 0; 207 208 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 209 mt7915_hwmon_groups); 210 if (IS_ERR(hwmon)) 211 return PTR_ERR(hwmon); 212 213 /* initialize critical/maximum high temperature */ 214 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 215 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 216 217 return 0; 218 } 219 220 static void mt7915_led_set_config(struct led_classdev *led_cdev, 221 u8 delay_on, u8 delay_off) 222 { 223 struct mt7915_dev *dev; 224 struct mt76_phy *mphy; 225 u32 val; 226 227 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 228 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 229 230 /* set PWM mode */ 231 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 232 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 233 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 234 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 235 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 236 237 /* enable LED */ 238 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 239 240 /* control LED */ 241 val = MT_LED_CTRL_KICK; 242 if (dev->mphy.leds.al) 243 val |= MT_LED_CTRL_POLARITY; 244 if (mphy->band_idx) 245 val |= MT_LED_CTRL_BAND; 246 247 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 248 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 249 } 250 251 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 252 unsigned long *delay_on, 253 unsigned long *delay_off) 254 { 255 u16 delta_on = 0, delta_off = 0; 256 257 #define HW_TICK 10 258 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 259 260 if (*delay_on) 261 delta_on = TO_HW_TICK(*delay_on); 262 if (*delay_off) 263 delta_off = TO_HW_TICK(*delay_off); 264 265 mt7915_led_set_config(led_cdev, delta_on, delta_off); 266 267 return 0; 268 } 269 270 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 271 enum led_brightness brightness) 272 { 273 if (!brightness) 274 mt7915_led_set_config(led_cdev, 0, 0xff); 275 else 276 mt7915_led_set_config(led_cdev, 0xff, 0); 277 } 278 279 void mt7915_init_txpower(struct mt7915_dev *dev, 280 struct ieee80211_supported_band *sband) 281 { 282 int i, n_chains = hweight8(dev->mphy.antenna_mask); 283 int nss_delta = mt76_tx_power_nss_delta(n_chains); 284 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 285 struct mt76_power_limits limits; 286 287 for (i = 0; i < sband->n_channels; i++) { 288 struct ieee80211_channel *chan = &sband->channels[i]; 289 u32 target_power = 0; 290 int j; 291 292 for (j = 0; j < n_chains; j++) { 293 u32 val; 294 295 val = mt7915_eeprom_get_target_power(dev, chan, j); 296 target_power = max(target_power, val); 297 } 298 299 target_power += pwr_delta; 300 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 301 &limits, 302 target_power); 303 target_power += nss_delta; 304 target_power = DIV_ROUND_UP(target_power, 2); 305 chan->max_power = min_t(int, chan->max_reg_power, 306 target_power); 307 chan->orig_mpwr = target_power; 308 } 309 } 310 311 static void 312 mt7915_regd_notifier(struct wiphy *wiphy, 313 struct regulatory_request *request) 314 { 315 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 316 struct mt7915_dev *dev = mt7915_hw_dev(hw); 317 struct mt76_phy *mphy = hw->priv; 318 struct mt7915_phy *phy = mphy->priv; 319 320 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 321 dev->mt76.region = request->dfs_region; 322 323 if (dev->mt76.region == NL80211_DFS_UNSET) 324 mt7915_mcu_rdd_background_enable(phy, NULL); 325 326 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 327 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 328 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 329 330 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 331 mt7915_dfs_init_radar_detector(phy); 332 } 333 334 static void 335 mt7915_init_wiphy(struct mt7915_phy *phy) 336 { 337 struct mt76_phy *mphy = phy->mt76; 338 struct ieee80211_hw *hw = mphy->hw; 339 struct mt76_dev *mdev = &phy->dev->mt76; 340 struct wiphy *wiphy = hw->wiphy; 341 struct mt7915_dev *dev = phy->dev; 342 343 hw->queues = 4; 344 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 345 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 346 hw->netdev_features = NETIF_F_RXCSUM; 347 348 hw->radiotap_timestamp.units_pos = 349 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 350 351 phy->slottime = 9; 352 353 hw->sta_data_size = sizeof(struct mt7915_sta); 354 hw->vif_data_size = sizeof(struct mt7915_vif); 355 356 wiphy->iface_combinations = if_comb; 357 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 358 wiphy->reg_notifier = mt7915_regd_notifier; 359 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 360 wiphy->mbssid_max_interfaces = 16; 361 362 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 363 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 364 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 365 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 366 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 367 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 368 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 369 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 370 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 371 372 if (!is_mt7915(&dev->mt76)) 373 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 374 375 if (!mdev->dev->of_node || 376 !of_property_read_bool(mdev->dev->of_node, 377 "mediatek,disable-radar-background")) 378 wiphy_ext_feature_set(wiphy, 379 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 380 381 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 382 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 383 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 384 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 385 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 386 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 387 388 hw->max_tx_fragments = 4; 389 390 if (phy->mt76->cap.has_2ghz) { 391 phy->mt76->sband_2g.sband.ht_cap.cap |= 392 IEEE80211_HT_CAP_LDPC_CODING | 393 IEEE80211_HT_CAP_MAX_AMSDU; 394 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 395 IEEE80211_HT_MPDU_DENSITY_4; 396 } 397 398 if (phy->mt76->cap.has_5ghz) { 399 phy->mt76->sband_5g.sband.ht_cap.cap |= 400 IEEE80211_HT_CAP_LDPC_CODING | 401 IEEE80211_HT_CAP_MAX_AMSDU; 402 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 403 IEEE80211_HT_MPDU_DENSITY_4; 404 405 if (is_mt7915(&dev->mt76)) { 406 phy->mt76->sband_5g.sband.vht_cap.cap |= 407 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 408 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 409 } else { 410 phy->mt76->sband_5g.sband.vht_cap.cap |= 411 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 412 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 413 414 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 415 phy->mt76->sband_5g.sband.vht_cap.cap |= 416 IEEE80211_VHT_CAP_SHORT_GI_160 | 417 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 418 } 419 } 420 421 mt76_set_stream_caps(phy->mt76, true); 422 mt7915_set_stream_vht_txbf_caps(phy); 423 mt7915_set_stream_he_caps(phy); 424 425 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 426 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 427 428 /* init led callbacks */ 429 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 430 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 431 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 432 } 433 } 434 435 static void 436 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 437 { 438 u32 mask, set; 439 440 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 441 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 442 mt76_set(dev, MT_TMAC_CTCR0(band), 443 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 444 MT_TMAC_CTCR0_INS_DDLMT_EN); 445 446 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 447 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 448 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 449 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 450 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 451 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 452 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 453 454 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 455 MT_MDP_RCFR1_RX_DROPPED_UCAST | 456 MT_MDP_RCFR1_RX_DROPPED_MCAST; 457 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 458 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 459 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 460 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 461 462 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 463 464 /* mt7915: disable rx rate report by default due to hw issues */ 465 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 466 467 /* clear estimated value of EIFS for Rx duration & OBSS time */ 468 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 469 470 /* clear backoff time for Rx duration */ 471 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 472 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 473 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 474 MT_WF_RMAC_MIB_QOS01_BACKOFF); 475 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 476 MT_WF_RMAC_MIB_QOS23_BACKOFF); 477 478 /* clear backoff time and set software compensation for OBSS time */ 479 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 480 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 481 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 482 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 483 484 /* filter out non-resp frames and get instanstaeous signal reporting */ 485 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 486 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 487 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 488 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 489 } 490 491 static void 492 mt7915_init_led_mux(struct mt7915_dev *dev) 493 { 494 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 495 return; 496 497 if (dev->dbdc_support) { 498 switch (mt76_chip(&dev->mt76)) { 499 case 0x7915: 500 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 501 GENMASK(11, 8), 4); 502 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 503 GENMASK(11, 8), 4); 504 break; 505 case 0x7986: 506 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 507 GENMASK(7, 4), 1); 508 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 509 GENMASK(11, 8), 1); 510 break; 511 case 0x7916: 512 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 513 GENMASK(27, 24), 3); 514 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 515 GENMASK(31, 28), 3); 516 break; 517 default: 518 break; 519 } 520 } else if (dev->mphy.leds.pin) { 521 switch (mt76_chip(&dev->mt76)) { 522 case 0x7915: 523 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 524 GENMASK(11, 8), 4); 525 break; 526 case 0x7986: 527 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 528 GENMASK(11, 8), 1); 529 break; 530 case 0x7916: 531 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 532 GENMASK(31, 28), 3); 533 break; 534 default: 535 break; 536 } 537 } else { 538 switch (mt76_chip(&dev->mt76)) { 539 case 0x7915: 540 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 541 GENMASK(11, 8), 4); 542 break; 543 case 0x7986: 544 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 545 GENMASK(7, 4), 1); 546 break; 547 case 0x7916: 548 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 549 GENMASK(27, 24), 3); 550 break; 551 default: 552 break; 553 } 554 } 555 } 556 557 void mt7915_mac_init(struct mt7915_dev *dev) 558 { 559 int i; 560 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 561 562 /* config pse qid6 wfdma port selection */ 563 if (!is_mt7915(&dev->mt76) && dev->hif2) 564 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 565 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 566 567 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 568 569 if (!is_mt7915(&dev->mt76)) 570 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 571 572 /* enable hardware de-agg */ 573 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 574 575 for (i = 0; i < mt7915_wtbl_size(dev); i++) 576 mt7915_mac_wtbl_update(dev, i, 577 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 578 for (i = 0; i < 2; i++) 579 mt7915_mac_init_band(dev, i); 580 581 mt7915_init_led_mux(dev); 582 } 583 584 int mt7915_txbf_init(struct mt7915_dev *dev) 585 { 586 int ret; 587 588 if (dev->dbdc_support) { 589 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 590 if (ret) 591 return ret; 592 } 593 594 /* trigger sounding packets */ 595 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 596 if (ret) 597 return ret; 598 599 /* enable eBF */ 600 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 601 } 602 603 static struct mt7915_phy * 604 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 605 { 606 struct mt7915_phy *phy; 607 struct mt76_phy *mphy; 608 609 if (!dev->dbdc_support) 610 return NULL; 611 612 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 613 if (!mphy) 614 return ERR_PTR(-ENOMEM); 615 616 phy = mphy->priv; 617 phy->dev = dev; 618 phy->mt76 = mphy; 619 620 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 621 phy->mt76->band_idx = 1; 622 623 return phy; 624 } 625 626 static int 627 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 628 { 629 struct mt76_phy *mphy = phy->mt76; 630 int ret; 631 632 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 633 634 mt7915_eeprom_parse_hw_cap(dev, phy); 635 636 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 637 ETH_ALEN); 638 /* Make the secondary PHY MAC address local without overlapping with 639 * the usual MAC address allocation scheme on multiple virtual interfaces 640 */ 641 if (!is_valid_ether_addr(mphy->macaddr)) { 642 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 643 ETH_ALEN); 644 mphy->macaddr[0] |= 2; 645 mphy->macaddr[0] ^= BIT(7); 646 } 647 mt76_eeprom_override(mphy); 648 649 /* init wiphy according to mphy and phy */ 650 mt7915_init_wiphy(phy); 651 652 ret = mt76_register_phy(mphy, true, mt76_rates, 653 ARRAY_SIZE(mt76_rates)); 654 if (ret) 655 return ret; 656 657 ret = mt7915_thermal_init(phy); 658 if (ret) 659 goto unreg; 660 661 mt7915_init_debugfs(phy); 662 663 return 0; 664 665 unreg: 666 mt76_unregister_phy(mphy); 667 return ret; 668 } 669 670 static void mt7915_init_work(struct work_struct *work) 671 { 672 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 673 init_work); 674 675 mt7915_mcu_set_eeprom(dev); 676 mt7915_mac_init(dev); 677 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 678 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 679 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 680 mt7915_txbf_init(dev); 681 } 682 683 void mt7915_wfsys_reset(struct mt7915_dev *dev) 684 { 685 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 686 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 687 688 if (is_mt7915(&dev->mt76)) { 689 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 690 691 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 692 693 /* change to software control */ 694 val |= MT_TOP_PWR_SW_RST; 695 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 696 697 /* reset wfsys */ 698 val &= ~MT_TOP_PWR_SW_RST; 699 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 700 701 /* release wfsys then mcu re-executes romcode */ 702 val |= MT_TOP_PWR_SW_RST; 703 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 704 705 /* switch to hw control */ 706 val &= ~MT_TOP_PWR_SW_RST; 707 val |= MT_TOP_PWR_HW_CTRL; 708 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 709 710 /* check whether mcu resets to default */ 711 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 712 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 713 1000)) { 714 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 715 return; 716 } 717 718 /* wfsys reset won't clear host registers */ 719 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 720 721 msleep(100); 722 } else if (is_mt7986(&dev->mt76)) { 723 mt7986_wmac_disable(dev); 724 msleep(20); 725 726 mt7986_wmac_enable(dev); 727 msleep(20); 728 } else { 729 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 730 msleep(20); 731 732 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 733 msleep(20); 734 } 735 } 736 737 static bool mt7915_band_config(struct mt7915_dev *dev) 738 { 739 bool ret = true; 740 741 dev->phy.mt76->band_idx = 0; 742 743 if (is_mt7986(&dev->mt76)) { 744 u32 sku = mt7915_check_adie(dev, true); 745 746 /* 747 * for mt7986, dbdc support is determined by the number 748 * of adie chips and the main phy is bound to band1 when 749 * dbdc is disabled. 750 */ 751 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 752 dev->phy.mt76->band_idx = 1; 753 ret = false; 754 } 755 } else { 756 ret = is_mt7915(&dev->mt76) ? 757 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 758 } 759 760 return ret; 761 } 762 763 static int 764 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 765 { 766 int ret, idx; 767 768 mt76_wr(dev, MT_INT_MASK_CSR, 0); 769 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 770 771 INIT_WORK(&dev->init_work, mt7915_init_work); 772 773 ret = mt7915_dma_init(dev, phy2); 774 if (ret) 775 return ret; 776 777 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 778 779 ret = mt7915_mcu_init(dev); 780 if (ret) 781 return ret; 782 783 ret = mt7915_eeprom_init(dev); 784 if (ret < 0) 785 return ret; 786 787 if (dev->flash_mode) { 788 ret = mt7915_mcu_apply_group_cal(dev); 789 if (ret) 790 return ret; 791 } 792 793 /* Beacon and mgmt frames should occupy wcid 0 */ 794 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 795 if (idx) 796 return -ENOSPC; 797 798 dev->mt76.global_wcid.idx = idx; 799 dev->mt76.global_wcid.hw_key_idx = -1; 800 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 801 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 802 803 return 0; 804 } 805 806 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 807 { 808 int sts; 809 u32 *cap; 810 811 if (!phy->mt76->cap.has_5ghz) 812 return; 813 814 sts = hweight8(phy->mt76->chainmask); 815 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 816 817 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 818 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 819 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 820 sts - 1); 821 822 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 823 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 824 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 825 826 if (sts < 2) 827 return; 828 829 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 830 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 831 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 832 sts - 1); 833 } 834 835 static void 836 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 837 struct ieee80211_sta_he_cap *he_cap, int vif) 838 { 839 struct mt7915_dev *dev = phy->dev; 840 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 841 int sts = hweight8(phy->mt76->chainmask); 842 u8 c, sts_160 = sts; 843 844 /* mt7915 doesn't support bw160 */ 845 if (is_mt7915(&dev->mt76)) 846 sts_160 = 0; 847 848 #ifdef CONFIG_MAC80211_MESH 849 if (vif == NL80211_IFTYPE_MESH_POINT) 850 return; 851 #endif 852 853 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 854 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 855 856 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 857 if (sts_160) 858 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 859 elem->phy_cap_info[5] &= ~c; 860 861 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 862 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 863 elem->phy_cap_info[6] &= ~c; 864 865 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 866 867 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 868 if (!is_mt7915(&dev->mt76)) 869 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 870 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 871 elem->phy_cap_info[2] |= c; 872 873 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 874 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 875 if (sts_160) 876 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 877 elem->phy_cap_info[4] |= c; 878 879 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 880 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 881 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 882 883 if (vif == NL80211_IFTYPE_STATION) 884 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 885 886 elem->phy_cap_info[6] |= c; 887 888 if (sts < 2) 889 return; 890 891 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 892 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 893 894 if (vif != NL80211_IFTYPE_AP) 895 return; 896 897 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 898 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 899 900 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 901 sts - 1); 902 if (sts_160) 903 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 904 sts_160 - 1); 905 elem->phy_cap_info[5] |= c; 906 907 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 908 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 909 elem->phy_cap_info[6] |= c; 910 911 if (!is_mt7915(&dev->mt76)) { 912 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 913 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 914 elem->phy_cap_info[7] |= c; 915 } 916 } 917 918 static void 919 mt7915_gen_ppe_thresh(u8 *he_ppet, int nss) 920 { 921 u8 i, ppet_bits, ppet_size, ru_bit_mask = 0x7; /* HE80 */ 922 static const u8 ppet16_ppet8_ru3_ru0[] = {0x1c, 0xc7, 0x71}; 923 924 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | 925 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, 926 ru_bit_mask); 927 928 ppet_bits = IEEE80211_PPE_THRES_INFO_PPET_SIZE * 929 nss * hweight8(ru_bit_mask) * 2; 930 ppet_size = DIV_ROUND_UP(ppet_bits, 8); 931 932 for (i = 0; i < ppet_size - 1; i++) 933 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3]; 934 935 he_ppet[i + 1] = ppet16_ppet8_ru3_ru0[i % 3] & 936 (0xff >> (8 - (ppet_bits - 1) % 8)); 937 } 938 939 static int 940 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 941 struct ieee80211_sband_iftype_data *data) 942 { 943 struct mt7915_dev *dev = phy->dev; 944 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 945 u16 mcs_map = 0; 946 u16 mcs_map_160 = 0; 947 u8 nss_160 = nss; 948 949 /* Can't do 160MHz with mt7915 */ 950 if (is_mt7915(&dev->mt76)) 951 nss_160 = 0; 952 953 for (i = 0; i < 8; i++) { 954 if (i < nss) 955 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 956 else 957 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 958 959 if (i < nss_160) 960 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 961 else 962 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 963 } 964 965 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 966 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 967 struct ieee80211_he_cap_elem *he_cap_elem = 968 &he_cap->he_cap_elem; 969 struct ieee80211_he_mcs_nss_supp *he_mcs = 970 &he_cap->he_mcs_nss_supp; 971 972 switch (i) { 973 case NL80211_IFTYPE_STATION: 974 case NL80211_IFTYPE_AP: 975 #ifdef CONFIG_MAC80211_MESH 976 case NL80211_IFTYPE_MESH_POINT: 977 #endif 978 break; 979 default: 980 continue; 981 } 982 983 data[idx].types_mask = BIT(i); 984 he_cap->has_he = true; 985 986 he_cap_elem->mac_cap_info[0] = 987 IEEE80211_HE_MAC_CAP0_HTC_HE; 988 he_cap_elem->mac_cap_info[3] = 989 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 990 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 991 he_cap_elem->mac_cap_info[4] = 992 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 993 994 if (band == NL80211_BAND_2GHZ) 995 he_cap_elem->phy_cap_info[0] = 996 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 997 else if (nss_160) 998 he_cap_elem->phy_cap_info[0] = 999 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1000 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1001 else 1002 he_cap_elem->phy_cap_info[0] = 1003 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1004 1005 he_cap_elem->phy_cap_info[1] = 1006 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1007 he_cap_elem->phy_cap_info[2] = 1008 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1009 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1010 1011 switch (i) { 1012 case NL80211_IFTYPE_AP: 1013 he_cap_elem->mac_cap_info[0] |= 1014 IEEE80211_HE_MAC_CAP0_TWT_RES; 1015 he_cap_elem->mac_cap_info[2] |= 1016 IEEE80211_HE_MAC_CAP2_BSR; 1017 he_cap_elem->mac_cap_info[4] |= 1018 IEEE80211_HE_MAC_CAP4_BQR; 1019 he_cap_elem->mac_cap_info[5] |= 1020 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1021 he_cap_elem->phy_cap_info[3] |= 1022 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1023 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1024 he_cap_elem->phy_cap_info[6] |= 1025 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1026 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1027 he_cap_elem->phy_cap_info[9] |= 1028 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1029 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1030 break; 1031 case NL80211_IFTYPE_STATION: 1032 he_cap_elem->mac_cap_info[1] |= 1033 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1034 1035 if (band == NL80211_BAND_2GHZ) 1036 he_cap_elem->phy_cap_info[0] |= 1037 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1038 else 1039 he_cap_elem->phy_cap_info[0] |= 1040 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1041 1042 he_cap_elem->phy_cap_info[1] |= 1043 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1044 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1045 he_cap_elem->phy_cap_info[3] |= 1046 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1047 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1048 he_cap_elem->phy_cap_info[6] |= 1049 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1050 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1051 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1052 he_cap_elem->phy_cap_info[7] |= 1053 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1054 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1055 he_cap_elem->phy_cap_info[8] |= 1056 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1057 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1058 if (nss_160) 1059 he_cap_elem->phy_cap_info[8] |= 1060 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1061 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1062 he_cap_elem->phy_cap_info[9] |= 1063 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1064 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1065 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1066 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1067 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1068 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1069 break; 1070 } 1071 1072 memset(he_mcs, 0, sizeof(*he_mcs)); 1073 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1074 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1075 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1076 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1077 1078 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1079 1080 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1081 if (he_cap_elem->phy_cap_info[6] & 1082 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1083 mt7915_gen_ppe_thresh(he_cap->ppe_thres, nss); 1084 } else { 1085 he_cap_elem->phy_cap_info[9] |= 1086 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1087 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1088 } 1089 1090 if (band == NL80211_BAND_6GHZ) { 1091 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1092 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1093 1094 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1095 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1096 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1097 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1098 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1099 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1100 1101 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1102 } 1103 1104 idx++; 1105 } 1106 1107 return idx; 1108 } 1109 1110 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1111 { 1112 struct ieee80211_sband_iftype_data *data; 1113 struct ieee80211_supported_band *band; 1114 int n; 1115 1116 if (phy->mt76->cap.has_2ghz) { 1117 data = phy->iftype[NL80211_BAND_2GHZ]; 1118 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1119 1120 band = &phy->mt76->sband_2g.sband; 1121 band->iftype_data = data; 1122 band->n_iftype_data = n; 1123 } 1124 1125 if (phy->mt76->cap.has_5ghz) { 1126 data = phy->iftype[NL80211_BAND_5GHZ]; 1127 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1128 1129 band = &phy->mt76->sband_5g.sband; 1130 band->iftype_data = data; 1131 band->n_iftype_data = n; 1132 } 1133 1134 if (phy->mt76->cap.has_6ghz) { 1135 data = phy->iftype[NL80211_BAND_6GHZ]; 1136 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1137 1138 band = &phy->mt76->sband_6g.sband; 1139 band->iftype_data = data; 1140 band->n_iftype_data = n; 1141 } 1142 } 1143 1144 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1145 { 1146 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1147 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1148 1149 if (!phy) 1150 return; 1151 1152 mt7915_unregister_thermal(phy); 1153 mt76_unregister_phy(mphy); 1154 ieee80211_free_hw(mphy->hw); 1155 } 1156 1157 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1158 { 1159 mt7915_mcu_exit(dev); 1160 mt7915_tx_token_put(dev); 1161 mt7915_dma_cleanup(dev); 1162 tasklet_disable(&dev->irq_tasklet); 1163 1164 if (is_mt7986(&dev->mt76)) 1165 mt7986_wmac_disable(dev); 1166 } 1167 1168 int mt7915_register_device(struct mt7915_dev *dev) 1169 { 1170 struct mt7915_phy *phy2; 1171 int ret; 1172 1173 dev->phy.dev = dev; 1174 dev->phy.mt76 = &dev->mt76.phy; 1175 dev->mt76.phy.priv = &dev->phy; 1176 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1177 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1178 INIT_LIST_HEAD(&dev->sta_rc_list); 1179 INIT_LIST_HEAD(&dev->sta_poll_list); 1180 INIT_LIST_HEAD(&dev->twt_list); 1181 spin_lock_init(&dev->sta_poll_lock); 1182 1183 init_waitqueue_head(&dev->reset_wait); 1184 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1185 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1186 mutex_init(&dev->dump_mutex); 1187 1188 dev->dbdc_support = mt7915_band_config(dev); 1189 1190 phy2 = mt7915_alloc_ext_phy(dev); 1191 if (IS_ERR(phy2)) 1192 return PTR_ERR(phy2); 1193 1194 ret = mt7915_init_hardware(dev, phy2); 1195 if (ret) 1196 goto free_phy2; 1197 1198 mt7915_init_wiphy(&dev->phy); 1199 1200 #ifdef CONFIG_NL80211_TESTMODE 1201 dev->mt76.test_ops = &mt7915_testmode_ops; 1202 #endif 1203 1204 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1205 ARRAY_SIZE(mt76_rates)); 1206 if (ret) 1207 goto stop_hw; 1208 1209 ret = mt7915_thermal_init(&dev->phy); 1210 if (ret) 1211 goto unreg_dev; 1212 1213 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1214 1215 if (phy2) { 1216 ret = mt7915_register_ext_phy(dev, phy2); 1217 if (ret) 1218 goto unreg_thermal; 1219 } 1220 1221 dev->recovery.hw_init_done = true; 1222 1223 ret = mt7915_init_debugfs(&dev->phy); 1224 if (ret) 1225 goto unreg_thermal; 1226 1227 ret = mt7915_coredump_register(dev); 1228 if (ret) 1229 goto unreg_thermal; 1230 1231 return 0; 1232 1233 unreg_thermal: 1234 mt7915_unregister_thermal(&dev->phy); 1235 unreg_dev: 1236 mt76_unregister_device(&dev->mt76); 1237 stop_hw: 1238 mt7915_stop_hardware(dev); 1239 free_phy2: 1240 if (phy2) 1241 ieee80211_free_hw(phy2->mt76->hw); 1242 return ret; 1243 } 1244 1245 void mt7915_unregister_device(struct mt7915_dev *dev) 1246 { 1247 mt7915_unregister_ext_phy(dev); 1248 mt7915_coredump_unregister(dev); 1249 mt7915_unregister_thermal(&dev->phy); 1250 mt76_unregister_device(&dev->mt76); 1251 mt7915_stop_hardware(dev); 1252 1253 mt76_free_device(&dev->mt76); 1254 } 1255