1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/hwmon.h> 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/of.h> 8 #include <linux/thermal.h> 9 #include "mt7915.h" 10 #include "mac.h" 11 #include "mcu.h" 12 #include "coredump.h" 13 #include "eeprom.h" 14 15 static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }, { 26 .max = MT7915_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29 }; 30 31 static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7915_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44 }; 45 46 static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49 { 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 temperature = mt7915_mcu_get_temperature(phy); 57 if (temperature < 0) 58 return temperature; 59 /* display in millidegree celcius */ 60 return sprintf(buf, "%u\n", temperature * 1000); 61 case 1: 62 case 2: 63 return sprintf(buf, "%u\n", 64 phy->throttle_temp[i - 1] * 1000); 65 case 3: 66 return sprintf(buf, "%hhu\n", phy->throttle_state); 67 default: 68 return -EINVAL; 69 } 70 } 71 72 static ssize_t mt7915_thermal_temp_store(struct device *dev, 73 struct device_attribute *attr, 74 const char *buf, size_t count) 75 { 76 struct mt7915_phy *phy = dev_get_drvdata(dev); 77 int ret, i = to_sensor_dev_attr(attr)->index; 78 long val; 79 80 ret = kstrtol(buf, 10, &val); 81 if (ret < 0) 82 return ret; 83 84 mutex_lock(&phy->dev->mt76.mutex); 85 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 86 87 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 88 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 89 (i - 1 == MT7915_MAX_TEMP_IDX && 90 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 91 dev_err(phy->dev->mt76.dev, 92 "temp1_max shall be greater than temp1_crit."); 93 mutex_unlock(&phy->dev->mt76.mutex); 94 return -EINVAL; 95 } 96 97 phy->throttle_temp[i - 1] = val; 98 mutex_unlock(&phy->dev->mt76.mutex); 99 100 ret = mt7915_mcu_set_thermal_protect(phy); 101 if (ret) 102 return ret; 103 104 return count; 105 } 106 107 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 108 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 109 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 110 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 111 112 static struct attribute *mt7915_hwmon_attrs[] = { 113 &sensor_dev_attr_temp1_input.dev_attr.attr, 114 &sensor_dev_attr_temp1_crit.dev_attr.attr, 115 &sensor_dev_attr_temp1_max.dev_attr.attr, 116 &sensor_dev_attr_throttle1.dev_attr.attr, 117 NULL, 118 }; 119 ATTRIBUTE_GROUPS(mt7915_hwmon); 120 121 static int 122 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 123 unsigned long *state) 124 { 125 *state = MT7915_CDEV_THROTTLE_MAX; 126 127 return 0; 128 } 129 130 static int 131 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 132 unsigned long *state) 133 { 134 struct mt7915_phy *phy = cdev->devdata; 135 136 *state = phy->cdev_state; 137 138 return 0; 139 } 140 141 static int 142 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 143 unsigned long state) 144 { 145 struct mt7915_phy *phy = cdev->devdata; 146 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 147 int ret; 148 149 if (state > MT7915_CDEV_THROTTLE_MAX) { 150 dev_err(phy->dev->mt76.dev, 151 "please specify a valid throttling state\n"); 152 return -EINVAL; 153 } 154 155 if (state == phy->cdev_state) 156 return 0; 157 158 /* 159 * cooling_device convention: 0 = no cooling, more = more cooling 160 * mcu convention: 1 = max cooling, more = less cooling 161 */ 162 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 163 if (ret) 164 return ret; 165 166 phy->cdev_state = state; 167 168 return 0; 169 } 170 171 static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 172 .get_max_state = mt7915_thermal_get_max_throttle_state, 173 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 174 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 175 }; 176 177 static void mt7915_unregister_thermal(struct mt7915_phy *phy) 178 { 179 struct wiphy *wiphy = phy->mt76->hw->wiphy; 180 181 if (!phy->cdev) 182 return; 183 184 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 185 thermal_cooling_device_unregister(phy->cdev); 186 } 187 188 static int mt7915_thermal_init(struct mt7915_phy *phy) 189 { 190 struct wiphy *wiphy = phy->mt76->hw->wiphy; 191 struct thermal_cooling_device *cdev; 192 struct device *hwmon; 193 const char *name; 194 195 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 196 wiphy_name(wiphy)); 197 if (!name) 198 return -ENOMEM; 199 200 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 201 if (!IS_ERR(cdev)) { 202 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 203 "cooling_device") < 0) 204 thermal_cooling_device_unregister(cdev); 205 else 206 phy->cdev = cdev; 207 } 208 209 /* initialize critical/maximum high temperature */ 210 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 211 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 212 213 if (!IS_REACHABLE(CONFIG_HWMON)) 214 return 0; 215 216 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 217 mt7915_hwmon_groups); 218 if (IS_ERR(hwmon)) 219 return PTR_ERR(hwmon); 220 221 return 0; 222 } 223 224 static void mt7915_led_set_config(struct led_classdev *led_cdev, 225 u8 delay_on, u8 delay_off) 226 { 227 struct mt7915_dev *dev; 228 struct mt76_phy *mphy; 229 u32 val; 230 231 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 232 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 233 234 /* set PWM mode */ 235 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 236 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 237 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 238 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 239 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 240 241 /* enable LED */ 242 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 243 244 /* control LED */ 245 val = MT_LED_CTRL_KICK; 246 if (dev->mphy.leds.al) 247 val |= MT_LED_CTRL_POLARITY; 248 if (mphy->band_idx) 249 val |= MT_LED_CTRL_BAND; 250 251 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 252 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 253 } 254 255 static int mt7915_led_set_blink(struct led_classdev *led_cdev, 256 unsigned long *delay_on, 257 unsigned long *delay_off) 258 { 259 u16 delta_on = 0, delta_off = 0; 260 261 #define HW_TICK 10 262 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 263 264 if (*delay_on) 265 delta_on = TO_HW_TICK(*delay_on); 266 if (*delay_off) 267 delta_off = TO_HW_TICK(*delay_off); 268 269 mt7915_led_set_config(led_cdev, delta_on, delta_off); 270 271 return 0; 272 } 273 274 static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 275 enum led_brightness brightness) 276 { 277 if (!brightness) 278 mt7915_led_set_config(led_cdev, 0, 0xff); 279 else 280 mt7915_led_set_config(led_cdev, 0xff, 0); 281 } 282 283 void mt7915_init_txpower(struct mt7915_dev *dev, 284 struct ieee80211_supported_band *sband) 285 { 286 int i, n_chains = hweight8(dev->mphy.antenna_mask); 287 int nss_delta = mt76_tx_power_nss_delta(n_chains); 288 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 289 struct mt76_power_limits limits; 290 291 for (i = 0; i < sband->n_channels; i++) { 292 struct ieee80211_channel *chan = &sband->channels[i]; 293 u32 target_power = 0; 294 int j; 295 296 for (j = 0; j < n_chains; j++) { 297 u32 val; 298 299 val = mt7915_eeprom_get_target_power(dev, chan, j); 300 target_power = max(target_power, val); 301 } 302 303 target_power += pwr_delta; 304 target_power = mt76_get_rate_power_limits(&dev->mphy, chan, 305 &limits, 306 target_power); 307 target_power += nss_delta; 308 target_power = DIV_ROUND_UP(target_power, 2); 309 chan->max_power = min_t(int, chan->max_reg_power, 310 target_power); 311 chan->orig_mpwr = target_power; 312 } 313 } 314 315 static void 316 mt7915_regd_notifier(struct wiphy *wiphy, 317 struct regulatory_request *request) 318 { 319 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 320 struct mt7915_dev *dev = mt7915_hw_dev(hw); 321 struct mt76_phy *mphy = hw->priv; 322 struct mt7915_phy *phy = mphy->priv; 323 324 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 325 dev->mt76.region = request->dfs_region; 326 327 if (dev->mt76.region == NL80211_DFS_UNSET) 328 mt7915_mcu_rdd_background_enable(phy, NULL); 329 330 mt7915_init_txpower(dev, &mphy->sband_2g.sband); 331 mt7915_init_txpower(dev, &mphy->sband_5g.sband); 332 mt7915_init_txpower(dev, &mphy->sband_6g.sband); 333 334 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 335 mt7915_dfs_init_radar_detector(phy); 336 } 337 338 static void 339 mt7915_init_wiphy(struct mt7915_phy *phy) 340 { 341 struct mt76_phy *mphy = phy->mt76; 342 struct ieee80211_hw *hw = mphy->hw; 343 struct mt76_dev *mdev = &phy->dev->mt76; 344 struct wiphy *wiphy = hw->wiphy; 345 struct mt7915_dev *dev = phy->dev; 346 347 hw->queues = 4; 348 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 349 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 350 hw->netdev_features = NETIF_F_RXCSUM; 351 352 hw->radiotap_timestamp.units_pos = 353 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 354 355 phy->slottime = 9; 356 357 hw->sta_data_size = sizeof(struct mt7915_sta); 358 hw->vif_data_size = sizeof(struct mt7915_vif); 359 360 wiphy->iface_combinations = if_comb; 361 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 362 wiphy->reg_notifier = mt7915_regd_notifier; 363 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 364 wiphy->mbssid_max_interfaces = 16; 365 366 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 367 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 368 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 369 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 370 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 371 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 372 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 373 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 374 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 375 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 376 377 if (!is_mt7915(&dev->mt76)) 378 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 379 380 if (!mdev->dev->of_node || 381 !of_property_read_bool(mdev->dev->of_node, 382 "mediatek,disable-radar-background")) 383 wiphy_ext_feature_set(wiphy, 384 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 385 386 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 387 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 388 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 389 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 390 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 391 392 hw->max_tx_fragments = 4; 393 394 if (phy->mt76->cap.has_2ghz) { 395 phy->mt76->sband_2g.sband.ht_cap.cap |= 396 IEEE80211_HT_CAP_LDPC_CODING | 397 IEEE80211_HT_CAP_MAX_AMSDU; 398 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 399 IEEE80211_HT_MPDU_DENSITY_4; 400 } 401 402 if (phy->mt76->cap.has_5ghz) { 403 struct ieee80211_sta_vht_cap *vht_cap; 404 405 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 406 phy->mt76->sband_5g.sband.ht_cap.cap |= 407 IEEE80211_HT_CAP_LDPC_CODING | 408 IEEE80211_HT_CAP_MAX_AMSDU; 409 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 410 IEEE80211_HT_MPDU_DENSITY_4; 411 412 if (is_mt7915(&dev->mt76)) { 413 vht_cap->cap |= 414 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 415 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 416 417 if (!dev->dbdc_support) 418 vht_cap->cap |= 419 IEEE80211_VHT_CAP_SHORT_GI_160 | 420 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 421 } else { 422 vht_cap->cap |= 423 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 424 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 425 426 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 427 vht_cap->cap |= 428 IEEE80211_VHT_CAP_SHORT_GI_160 | 429 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 430 } 431 432 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 433 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 434 } 435 436 mt76_set_stream_caps(phy->mt76, true); 437 mt7915_set_stream_vht_txbf_caps(phy); 438 mt7915_set_stream_he_caps(phy); 439 440 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 441 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 442 443 /* init led callbacks */ 444 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 445 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 446 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 447 } 448 } 449 450 static void 451 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 452 { 453 u32 mask, set; 454 455 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 456 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 457 mt76_set(dev, MT_TMAC_CTCR0(band), 458 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 459 MT_TMAC_CTCR0_INS_DDLMT_EN); 460 461 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 462 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 463 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 464 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 465 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 466 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 467 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 468 469 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 470 MT_MDP_RCFR1_RX_DROPPED_UCAST | 471 MT_MDP_RCFR1_RX_DROPPED_MCAST; 472 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 473 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 474 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 475 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 476 477 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 478 479 /* mt7915: disable rx rate report by default due to hw issues */ 480 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 481 482 /* clear estimated value of EIFS for Rx duration & OBSS time */ 483 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 484 485 /* clear backoff time for Rx duration */ 486 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 487 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 488 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 489 MT_WF_RMAC_MIB_QOS01_BACKOFF); 490 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 491 MT_WF_RMAC_MIB_QOS23_BACKOFF); 492 493 /* clear backoff time and set software compensation for OBSS time */ 494 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 495 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 496 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 497 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 498 499 /* filter out non-resp frames and get instanstaeous signal reporting */ 500 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 501 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 502 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 503 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 504 505 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 506 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 507 */ 508 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 509 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 510 } 511 512 static void 513 mt7915_init_led_mux(struct mt7915_dev *dev) 514 { 515 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 516 return; 517 518 if (dev->dbdc_support) { 519 switch (mt76_chip(&dev->mt76)) { 520 case 0x7915: 521 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 522 GENMASK(11, 8), 4); 523 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 524 GENMASK(11, 8), 4); 525 break; 526 case 0x7986: 527 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 528 GENMASK(7, 4), 1); 529 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 530 GENMASK(11, 8), 1); 531 break; 532 case 0x7916: 533 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 534 GENMASK(27, 24), 3); 535 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 536 GENMASK(31, 28), 3); 537 break; 538 default: 539 break; 540 } 541 } else if (dev->mphy.leds.pin) { 542 switch (mt76_chip(&dev->mt76)) { 543 case 0x7915: 544 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 545 GENMASK(11, 8), 4); 546 break; 547 case 0x7986: 548 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 549 GENMASK(11, 8), 1); 550 break; 551 case 0x7916: 552 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 553 GENMASK(31, 28), 3); 554 break; 555 default: 556 break; 557 } 558 } else { 559 switch (mt76_chip(&dev->mt76)) { 560 case 0x7915: 561 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 562 GENMASK(11, 8), 4); 563 break; 564 case 0x7986: 565 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 566 GENMASK(7, 4), 1); 567 break; 568 case 0x7916: 569 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 570 GENMASK(27, 24), 3); 571 break; 572 default: 573 break; 574 } 575 } 576 } 577 578 void mt7915_mac_init(struct mt7915_dev *dev) 579 { 580 int i; 581 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 582 583 /* config pse qid6 wfdma port selection */ 584 if (!is_mt7915(&dev->mt76) && dev->hif2) 585 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 586 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 587 588 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 589 590 if (!is_mt7915(&dev->mt76)) 591 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 592 else 593 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); 594 595 /* enable hardware de-agg */ 596 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 597 598 for (i = 0; i < mt7915_wtbl_size(dev); i++) 599 mt7915_mac_wtbl_update(dev, i, 600 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 601 for (i = 0; i < 2; i++) 602 mt7915_mac_init_band(dev, i); 603 604 mt7915_init_led_mux(dev); 605 } 606 607 int mt7915_txbf_init(struct mt7915_dev *dev) 608 { 609 int ret; 610 611 if (dev->dbdc_support) { 612 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 613 if (ret) 614 return ret; 615 } 616 617 /* trigger sounding packets */ 618 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 619 if (ret) 620 return ret; 621 622 /* enable eBF */ 623 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 624 } 625 626 static struct mt7915_phy * 627 mt7915_alloc_ext_phy(struct mt7915_dev *dev) 628 { 629 struct mt7915_phy *phy; 630 struct mt76_phy *mphy; 631 632 if (!dev->dbdc_support) 633 return NULL; 634 635 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 636 if (!mphy) 637 return ERR_PTR(-ENOMEM); 638 639 phy = mphy->priv; 640 phy->dev = dev; 641 phy->mt76 = mphy; 642 643 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 644 phy->mt76->band_idx = 1; 645 646 return phy; 647 } 648 649 static int 650 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 651 { 652 struct mt76_phy *mphy = phy->mt76; 653 int ret; 654 655 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 656 657 mt7915_eeprom_parse_hw_cap(dev, phy); 658 659 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 660 ETH_ALEN); 661 /* Make the secondary PHY MAC address local without overlapping with 662 * the usual MAC address allocation scheme on multiple virtual interfaces 663 */ 664 if (!is_valid_ether_addr(mphy->macaddr)) { 665 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 666 ETH_ALEN); 667 mphy->macaddr[0] |= 2; 668 mphy->macaddr[0] ^= BIT(7); 669 } 670 mt76_eeprom_override(mphy); 671 672 /* init wiphy according to mphy and phy */ 673 mt7915_init_wiphy(phy); 674 675 ret = mt76_register_phy(mphy, true, mt76_rates, 676 ARRAY_SIZE(mt76_rates)); 677 if (ret) 678 return ret; 679 680 ret = mt7915_thermal_init(phy); 681 if (ret) 682 goto unreg; 683 684 mt7915_init_debugfs(phy); 685 686 return 0; 687 688 unreg: 689 mt76_unregister_phy(mphy); 690 return ret; 691 } 692 693 static void mt7915_init_work(struct work_struct *work) 694 { 695 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 696 init_work); 697 698 mt7915_mcu_set_eeprom(dev); 699 mt7915_mac_init(dev); 700 mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband); 701 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband); 702 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband); 703 mt7915_txbf_init(dev); 704 } 705 706 void mt7915_wfsys_reset(struct mt7915_dev *dev) 707 { 708 #define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 709 #define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 710 711 if (is_mt7915(&dev->mt76)) { 712 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 713 714 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 715 716 /* change to software control */ 717 val |= MT_TOP_PWR_SW_RST; 718 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 719 720 /* reset wfsys */ 721 val &= ~MT_TOP_PWR_SW_RST; 722 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 723 724 /* release wfsys then mcu re-executes romcode */ 725 val |= MT_TOP_PWR_SW_RST; 726 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 727 728 /* switch to hw control */ 729 val &= ~MT_TOP_PWR_SW_RST; 730 val |= MT_TOP_PWR_HW_CTRL; 731 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 732 733 /* check whether mcu resets to default */ 734 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 735 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 736 1000)) { 737 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 738 return; 739 } 740 741 /* wfsys reset won't clear host registers */ 742 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 743 744 msleep(100); 745 } else if (is_mt798x(&dev->mt76)) { 746 mt7986_wmac_disable(dev); 747 msleep(20); 748 749 mt7986_wmac_enable(dev); 750 msleep(20); 751 } else { 752 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 753 msleep(20); 754 755 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 756 msleep(20); 757 } 758 } 759 760 static bool mt7915_band_config(struct mt7915_dev *dev) 761 { 762 bool ret = true; 763 764 dev->phy.mt76->band_idx = 0; 765 766 if (is_mt798x(&dev->mt76)) { 767 u32 sku = mt7915_check_adie(dev, true); 768 769 /* 770 * for mt7986, dbdc support is determined by the number 771 * of adie chips and the main phy is bound to band1 when 772 * dbdc is disabled. 773 */ 774 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 775 dev->phy.mt76->band_idx = 1; 776 ret = false; 777 } 778 } else { 779 ret = is_mt7915(&dev->mt76) ? 780 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 781 } 782 783 return ret; 784 } 785 786 static int 787 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 788 { 789 int ret, idx; 790 791 mt76_wr(dev, MT_INT_MASK_CSR, 0); 792 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 793 794 INIT_WORK(&dev->init_work, mt7915_init_work); 795 796 ret = mt7915_dma_init(dev, phy2); 797 if (ret) 798 return ret; 799 800 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 801 802 ret = mt7915_mcu_init(dev); 803 if (ret) 804 return ret; 805 806 ret = mt7915_eeprom_init(dev); 807 if (ret < 0) 808 return ret; 809 810 if (dev->flash_mode) { 811 ret = mt7915_mcu_apply_group_cal(dev); 812 if (ret) 813 return ret; 814 } 815 816 /* Beacon and mgmt frames should occupy wcid 0 */ 817 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 818 if (idx) 819 return -ENOSPC; 820 821 dev->mt76.global_wcid.idx = idx; 822 dev->mt76.global_wcid.hw_key_idx = -1; 823 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 824 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 825 826 return 0; 827 } 828 829 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 830 { 831 int sts; 832 u32 *cap; 833 834 if (!phy->mt76->cap.has_5ghz) 835 return; 836 837 sts = hweight8(phy->mt76->chainmask); 838 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 839 840 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 841 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 842 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 843 sts - 1); 844 845 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 846 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 847 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 848 849 if (sts < 2) 850 return; 851 852 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 853 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 854 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 855 sts - 1); 856 } 857 858 static void 859 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 860 struct ieee80211_sta_he_cap *he_cap, int vif) 861 { 862 struct mt7915_dev *dev = phy->dev; 863 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 864 int sts = hweight8(phy->mt76->chainmask); 865 u8 c, sts_160 = sts; 866 867 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 868 if (is_mt7915(&dev->mt76)) { 869 if (!dev->dbdc_support) 870 sts_160 /= 2; 871 else 872 sts_160 = 0; 873 } 874 875 #ifdef CONFIG_MAC80211_MESH 876 if (vif == NL80211_IFTYPE_MESH_POINT) 877 return; 878 #endif 879 880 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 881 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 882 883 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 884 if (sts_160) 885 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 886 elem->phy_cap_info[5] &= ~c; 887 888 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 889 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 890 elem->phy_cap_info[6] &= ~c; 891 892 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 893 894 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 895 if (!is_mt7915(&dev->mt76)) 896 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 897 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 898 elem->phy_cap_info[2] |= c; 899 900 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 901 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 902 if (sts_160) 903 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 904 elem->phy_cap_info[4] |= c; 905 906 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 907 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 908 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 909 910 if (vif == NL80211_IFTYPE_STATION) 911 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 912 913 elem->phy_cap_info[6] |= c; 914 915 if (sts < 2) 916 return; 917 918 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 919 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 920 921 if (vif != NL80211_IFTYPE_AP) 922 return; 923 924 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 925 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 926 927 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 928 sts - 1); 929 if (sts_160) 930 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 931 sts_160 - 1); 932 elem->phy_cap_info[5] |= c; 933 934 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 935 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 936 elem->phy_cap_info[6] |= c; 937 938 if (!is_mt7915(&dev->mt76)) { 939 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 940 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 941 elem->phy_cap_info[7] |= c; 942 } 943 } 944 945 static int 946 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 947 struct ieee80211_sband_iftype_data *data) 948 { 949 struct mt7915_dev *dev = phy->dev; 950 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 951 u16 mcs_map = 0; 952 u16 mcs_map_160 = 0; 953 u8 nss_160; 954 955 if (!is_mt7915(&dev->mt76)) 956 nss_160 = nss; 957 else if (!dev->dbdc_support) 958 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 959 nss_160 = nss / 2; 960 else 961 /* Can't do 160MHz with mt7915 dbdc */ 962 nss_160 = 0; 963 964 for (i = 0; i < 8; i++) { 965 if (i < nss) 966 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 967 else 968 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 969 970 if (i < nss_160) 971 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 972 else 973 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 974 } 975 976 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 977 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 978 struct ieee80211_he_cap_elem *he_cap_elem = 979 &he_cap->he_cap_elem; 980 struct ieee80211_he_mcs_nss_supp *he_mcs = 981 &he_cap->he_mcs_nss_supp; 982 983 switch (i) { 984 case NL80211_IFTYPE_STATION: 985 case NL80211_IFTYPE_AP: 986 #ifdef CONFIG_MAC80211_MESH 987 case NL80211_IFTYPE_MESH_POINT: 988 #endif 989 break; 990 default: 991 continue; 992 } 993 994 data[idx].types_mask = BIT(i); 995 he_cap->has_he = true; 996 997 he_cap_elem->mac_cap_info[0] = 998 IEEE80211_HE_MAC_CAP0_HTC_HE; 999 he_cap_elem->mac_cap_info[3] = 1000 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1001 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1002 he_cap_elem->mac_cap_info[4] = 1003 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1004 1005 if (band == NL80211_BAND_2GHZ) 1006 he_cap_elem->phy_cap_info[0] = 1007 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1008 else if (nss_160) 1009 he_cap_elem->phy_cap_info[0] = 1010 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1011 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1012 else 1013 he_cap_elem->phy_cap_info[0] = 1014 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1015 1016 he_cap_elem->phy_cap_info[1] = 1017 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1018 he_cap_elem->phy_cap_info[2] = 1019 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1020 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1021 1022 switch (i) { 1023 case NL80211_IFTYPE_AP: 1024 he_cap_elem->mac_cap_info[0] |= 1025 IEEE80211_HE_MAC_CAP0_TWT_RES; 1026 he_cap_elem->mac_cap_info[2] |= 1027 IEEE80211_HE_MAC_CAP2_BSR; 1028 he_cap_elem->mac_cap_info[4] |= 1029 IEEE80211_HE_MAC_CAP4_BQR; 1030 he_cap_elem->mac_cap_info[5] |= 1031 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1032 he_cap_elem->phy_cap_info[3] |= 1033 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1034 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1035 he_cap_elem->phy_cap_info[6] |= 1036 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1037 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1038 he_cap_elem->phy_cap_info[9] |= 1039 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1040 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1041 break; 1042 case NL80211_IFTYPE_STATION: 1043 he_cap_elem->mac_cap_info[1] |= 1044 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1045 1046 if (band == NL80211_BAND_2GHZ) 1047 he_cap_elem->phy_cap_info[0] |= 1048 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1049 else 1050 he_cap_elem->phy_cap_info[0] |= 1051 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1052 1053 he_cap_elem->phy_cap_info[1] |= 1054 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1055 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1056 he_cap_elem->phy_cap_info[3] |= 1057 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1058 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1059 he_cap_elem->phy_cap_info[6] |= 1060 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1061 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1062 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1063 he_cap_elem->phy_cap_info[7] |= 1064 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1065 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1066 he_cap_elem->phy_cap_info[8] |= 1067 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1068 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1069 if (nss_160) 1070 he_cap_elem->phy_cap_info[8] |= 1071 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1072 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1073 he_cap_elem->phy_cap_info[9] |= 1074 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1075 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1076 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1077 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1078 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1079 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1080 break; 1081 } 1082 1083 memset(he_mcs, 0, sizeof(*he_mcs)); 1084 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1085 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1086 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1087 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1088 1089 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1090 1091 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1092 if (he_cap_elem->phy_cap_info[6] & 1093 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1094 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1095 } else { 1096 he_cap_elem->phy_cap_info[9] |= 1097 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1098 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1099 } 1100 1101 if (band == NL80211_BAND_6GHZ) { 1102 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1103 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1104 1105 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1106 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1107 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1108 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1109 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1110 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1111 1112 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1113 } 1114 1115 idx++; 1116 } 1117 1118 return idx; 1119 } 1120 1121 void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1122 { 1123 struct ieee80211_sband_iftype_data *data; 1124 struct ieee80211_supported_band *band; 1125 int n; 1126 1127 if (phy->mt76->cap.has_2ghz) { 1128 data = phy->iftype[NL80211_BAND_2GHZ]; 1129 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1130 1131 band = &phy->mt76->sband_2g.sband; 1132 band->iftype_data = data; 1133 band->n_iftype_data = n; 1134 } 1135 1136 if (phy->mt76->cap.has_5ghz) { 1137 data = phy->iftype[NL80211_BAND_5GHZ]; 1138 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1139 1140 band = &phy->mt76->sband_5g.sband; 1141 band->iftype_data = data; 1142 band->n_iftype_data = n; 1143 } 1144 1145 if (phy->mt76->cap.has_6ghz) { 1146 data = phy->iftype[NL80211_BAND_6GHZ]; 1147 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1148 1149 band = &phy->mt76->sband_6g.sband; 1150 band->iftype_data = data; 1151 band->n_iftype_data = n; 1152 } 1153 } 1154 1155 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1156 { 1157 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1158 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1159 1160 if (!phy) 1161 return; 1162 1163 mt7915_unregister_thermal(phy); 1164 mt76_unregister_phy(mphy); 1165 ieee80211_free_hw(mphy->hw); 1166 } 1167 1168 static void mt7915_stop_hardware(struct mt7915_dev *dev) 1169 { 1170 mt7915_mcu_exit(dev); 1171 mt76_connac2_tx_token_put(&dev->mt76); 1172 mt7915_dma_cleanup(dev); 1173 tasklet_disable(&dev->mt76.irq_tasklet); 1174 1175 if (is_mt798x(&dev->mt76)) 1176 mt7986_wmac_disable(dev); 1177 } 1178 1179 int mt7915_register_device(struct mt7915_dev *dev) 1180 { 1181 struct mt7915_phy *phy2; 1182 int ret; 1183 1184 dev->phy.dev = dev; 1185 dev->phy.mt76 = &dev->mt76.phy; 1186 dev->mt76.phy.priv = &dev->phy; 1187 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1188 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1189 INIT_LIST_HEAD(&dev->sta_rc_list); 1190 INIT_LIST_HEAD(&dev->twt_list); 1191 1192 init_waitqueue_head(&dev->reset_wait); 1193 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1194 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1195 mutex_init(&dev->dump_mutex); 1196 1197 dev->dbdc_support = mt7915_band_config(dev); 1198 1199 phy2 = mt7915_alloc_ext_phy(dev); 1200 if (IS_ERR(phy2)) 1201 return PTR_ERR(phy2); 1202 1203 ret = mt7915_init_hardware(dev, phy2); 1204 if (ret) 1205 goto free_phy2; 1206 1207 mt7915_init_wiphy(&dev->phy); 1208 1209 #ifdef CONFIG_NL80211_TESTMODE 1210 dev->mt76.test_ops = &mt7915_testmode_ops; 1211 #endif 1212 1213 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1214 ARRAY_SIZE(mt76_rates)); 1215 if (ret) 1216 goto stop_hw; 1217 1218 ret = mt7915_thermal_init(&dev->phy); 1219 if (ret) 1220 goto unreg_dev; 1221 1222 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1223 1224 if (phy2) { 1225 ret = mt7915_register_ext_phy(dev, phy2); 1226 if (ret) 1227 goto unreg_thermal; 1228 } 1229 1230 dev->recovery.hw_init_done = true; 1231 1232 ret = mt7915_init_debugfs(&dev->phy); 1233 if (ret) 1234 goto unreg_thermal; 1235 1236 ret = mt7915_coredump_register(dev); 1237 if (ret) 1238 goto unreg_thermal; 1239 1240 return 0; 1241 1242 unreg_thermal: 1243 mt7915_unregister_thermal(&dev->phy); 1244 unreg_dev: 1245 mt76_unregister_device(&dev->mt76); 1246 stop_hw: 1247 mt7915_stop_hardware(dev); 1248 free_phy2: 1249 if (phy2) 1250 ieee80211_free_hw(phy2->mt76->hw); 1251 return ret; 1252 } 1253 1254 void mt7915_unregister_device(struct mt7915_dev *dev) 1255 { 1256 mt7915_unregister_ext_phy(dev); 1257 mt7915_coredump_unregister(dev); 1258 mt7915_unregister_thermal(&dev->phy); 1259 mt76_unregister_device(&dev->mt76); 1260 mt7915_stop_hardware(dev); 1261 1262 mt76_free_device(&dev->mt76); 1263 } 1264