1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include "mt7915.h" 5 #include "../dma.h" 6 #include "mac.h" 7 8 int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc) 9 { 10 int i, err; 11 12 err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE); 13 if (err < 0) 14 return err; 15 16 for (i = 0; i <= MT_TXQ_PSD; i++) 17 phy->mt76->q_tx[i] = phy->mt76->q_tx[0]; 18 19 return 0; 20 } 21 22 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 23 struct sk_buff *skb) 24 { 25 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 26 __le32 *rxd = (__le32 *)skb->data; 27 enum rx_pkt_type type; 28 29 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 30 31 switch (type) { 32 case PKT_TYPE_TXRX_NOTIFY: 33 mt7915_mac_tx_free(dev, skb); 34 break; 35 case PKT_TYPE_RX_EVENT: 36 mt7915_mcu_rx_event(dev, skb); 37 break; 38 #ifdef CONFIG_NL80211_TESTMODE 39 case PKT_TYPE_TXRXV: 40 mt7915_mac_fill_rx_vector(dev, skb); 41 break; 42 #endif 43 case PKT_TYPE_NORMAL: 44 if (!mt7915_mac_fill_rx(dev, skb)) { 45 mt76_rx(&dev->mt76, q, skb); 46 return; 47 } 48 fallthrough; 49 default: 50 dev_kfree_skb(skb); 51 break; 52 } 53 } 54 55 static void 56 mt7915_tx_cleanup(struct mt7915_dev *dev) 57 { 58 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); 59 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], false); 60 } 61 62 static int mt7915_poll_tx(struct napi_struct *napi, int budget) 63 { 64 struct mt7915_dev *dev; 65 66 dev = container_of(napi, struct mt7915_dev, mt76.tx_napi); 67 68 mt7915_tx_cleanup(dev); 69 70 if (napi_complete_done(napi, 0)) 71 mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU); 72 73 return 0; 74 } 75 76 static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs) 77 { 78 #define PREFETCH(base, depth) ((base) << 16 | (depth)) 79 80 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x0, 0x4)); 81 mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x40, 0x4)); 82 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x80, 0x0)); 83 84 mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL + ofs, PREFETCH(0x80, 0x4)); 85 mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL + ofs, PREFETCH(0xc0, 0x4)); 86 mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL + ofs, PREFETCH(0x100, 0x4)); 87 mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL + ofs, PREFETCH(0x140, 0x4)); 88 mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL + ofs, PREFETCH(0x180, 0x4)); 89 mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL + ofs, PREFETCH(0x1c0, 0x4)); 90 mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL + ofs, PREFETCH(0x200, 0x4)); 91 mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL + ofs, PREFETCH(0x240, 0x4)); 92 93 mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL + ofs, PREFETCH(0x280, 0x4)); 94 mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL + ofs, PREFETCH(0x2c0, 0x4)); 95 mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL + ofs, PREFETCH(0x300, 0x4)); 96 mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL + ofs, PREFETCH(0x340, 0x4)); 97 mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL + ofs, PREFETCH(0x380, 0x4)); 98 mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x0)); 99 100 mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x4)); 101 mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x400, 0x4)); 102 mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x440, 0x4)); 103 mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL + ofs, PREFETCH(0x480, 0x0)); 104 } 105 106 void mt7915_dma_prefetch(struct mt7915_dev *dev) 107 { 108 __mt7915_dma_prefetch(dev, 0); 109 if (dev->hif2) 110 __mt7915_dma_prefetch(dev, MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE); 111 } 112 113 int mt7915_dma_init(struct mt7915_dev *dev) 114 { 115 /* Increase buffer size to receive large VHT/HE MPDUs */ 116 int rx_buf_size = MT_RX_BUF_SIZE * 2; 117 u32 hif1_ofs = 0; 118 int ret; 119 120 mt76_dma_attach(&dev->mt76); 121 122 if (dev->hif2) 123 hif1_ofs = MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE; 124 125 /* configure global setting */ 126 mt76_set(dev, MT_WFDMA1_GLO_CFG, 127 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 128 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 129 130 /* reset dma idx */ 131 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); 132 mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0); 133 134 /* configure delay interrupt */ 135 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); 136 mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0); 137 138 if (dev->hif2) { 139 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 140 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 141 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 142 143 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0); 144 mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0); 145 146 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0); 147 mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0 + hif1_ofs, 0); 148 } 149 150 /* configure perfetch settings */ 151 mt7915_dma_prefetch(dev); 152 153 /* init tx queue */ 154 ret = mt7915_init_tx_queues(&dev->phy, MT7915_TXQ_BAND0, 155 MT7915_TX_RING_SIZE); 156 if (ret) 157 return ret; 158 159 /* command to WM */ 160 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7915_TXQ_MCU_WM, 161 MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 162 if (ret) 163 return ret; 164 165 /* command to WA */ 166 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, MT7915_TXQ_MCU_WA, 167 MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 168 if (ret) 169 return ret; 170 171 /* firmware download */ 172 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7915_TXQ_FWDL, 173 MT7915_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 174 if (ret) 175 return ret; 176 177 /* event from WM */ 178 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 179 MT7915_RXQ_MCU_WM, MT7915_RX_MCU_RING_SIZE, 180 rx_buf_size, MT_RX_EVENT_RING_BASE); 181 if (ret) 182 return ret; 183 184 /* event from WA */ 185 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 186 MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE, 187 rx_buf_size, MT_RX_EVENT_RING_BASE); 188 if (ret) 189 return ret; 190 191 /* rx data queue */ 192 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 193 MT7915_RXQ_BAND0, MT7915_RX_RING_SIZE, 194 rx_buf_size, MT_RX_DATA_RING_BASE); 195 if (ret) 196 return ret; 197 198 if (dev->dbdc_support) { 199 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT], 200 MT7915_RXQ_BAND1, MT7915_RX_RING_SIZE, 201 rx_buf_size, 202 MT_RX_DATA_RING_BASE + hif1_ofs); 203 if (ret) 204 return ret; 205 206 /* event from WA */ 207 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT_WA], 208 MT7915_RXQ_MCU_WA_EXT, 209 MT7915_RX_MCU_RING_SIZE, 210 rx_buf_size, 211 MT_RX_EVENT_RING_BASE + hif1_ofs); 212 if (ret) 213 return ret; 214 } 215 216 ret = mt76_init_queues(dev, mt76_dma_rx_poll); 217 if (ret < 0) 218 return ret; 219 220 netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 221 mt7915_poll_tx, NAPI_POLL_WEIGHT); 222 napi_enable(&dev->mt76.tx_napi); 223 224 /* hif wait WFDMA idle */ 225 mt76_set(dev, MT_WFDMA0_BUSY_ENA, 226 MT_WFDMA0_BUSY_ENA_TX_FIFO0 | 227 MT_WFDMA0_BUSY_ENA_TX_FIFO1 | 228 MT_WFDMA0_BUSY_ENA_RX_FIFO); 229 230 mt76_set(dev, MT_WFDMA1_BUSY_ENA, 231 MT_WFDMA1_BUSY_ENA_TX_FIFO0 | 232 MT_WFDMA1_BUSY_ENA_TX_FIFO1 | 233 MT_WFDMA1_BUSY_ENA_RX_FIFO); 234 235 mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA, 236 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | 237 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | 238 MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); 239 240 mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA, 241 MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 | 242 MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 | 243 MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO); 244 245 mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, 246 MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); 247 248 /* set WFDMA Tx/Rx */ 249 mt76_set(dev, MT_WFDMA0_GLO_CFG, 250 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 251 mt76_set(dev, MT_WFDMA1_GLO_CFG, 252 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 253 254 if (dev->hif2) { 255 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 256 (MT_WFDMA0_GLO_CFG_TX_DMA_EN | 257 MT_WFDMA0_GLO_CFG_RX_DMA_EN)); 258 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 259 (MT_WFDMA1_GLO_CFG_TX_DMA_EN | 260 MT_WFDMA1_GLO_CFG_RX_DMA_EN)); 261 mt76_set(dev, MT_WFDMA_HOST_CONFIG, 262 MT_WFDMA_HOST_CONFIG_PDMA_BAND); 263 } 264 265 /* enable interrupts for TX/RX rings */ 266 mt7915_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_MCU | 267 MT_INT_MCU_CMD); 268 269 return 0; 270 } 271 272 void mt7915_dma_cleanup(struct mt7915_dev *dev) 273 { 274 /* disable */ 275 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 276 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 277 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 278 mt76_clear(dev, MT_WFDMA1_GLO_CFG, 279 MT_WFDMA1_GLO_CFG_TX_DMA_EN | 280 MT_WFDMA1_GLO_CFG_RX_DMA_EN); 281 282 /* reset */ 283 mt76_clear(dev, MT_WFDMA1_RST, 284 MT_WFDMA1_RST_DMASHDL_ALL_RST | 285 MT_WFDMA1_RST_LOGIC_RST); 286 287 mt76_set(dev, MT_WFDMA1_RST, 288 MT_WFDMA1_RST_DMASHDL_ALL_RST | 289 MT_WFDMA1_RST_LOGIC_RST); 290 291 mt76_clear(dev, MT_WFDMA0_RST, 292 MT_WFDMA0_RST_DMASHDL_ALL_RST | 293 MT_WFDMA0_RST_LOGIC_RST); 294 295 mt76_set(dev, MT_WFDMA0_RST, 296 MT_WFDMA0_RST_DMASHDL_ALL_RST | 297 MT_WFDMA0_RST_LOGIC_RST); 298 299 mt76_dma_cleanup(&dev->mt76); 300 } 301