1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include "mt7915.h" 5 #include "../dma.h" 6 #include "mac.h" 7 8 int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc) 9 { 10 int i, err; 11 12 err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE); 13 if (err < 0) 14 return err; 15 16 for (i = 0; i <= MT_TXQ_PSD; i++) 17 phy->mt76->q_tx[i] = phy->mt76->q_tx[0]; 18 19 return 0; 20 } 21 22 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 23 struct sk_buff *skb) 24 { 25 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 26 __le32 *rxd = (__le32 *)skb->data; 27 enum rx_pkt_type type; 28 29 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 30 31 switch (type) { 32 case PKT_TYPE_TXRX_NOTIFY: 33 mt7915_mac_tx_free(dev, skb); 34 break; 35 case PKT_TYPE_RX_EVENT: 36 mt7915_mcu_rx_event(dev, skb); 37 break; 38 #ifdef CONFIG_NL80211_TESTMODE 39 case PKT_TYPE_TXRXV: 40 mt7915_mac_fill_rx_vector(dev, skb); 41 break; 42 #endif 43 case PKT_TYPE_NORMAL: 44 if (!mt7915_mac_fill_rx(dev, skb)) { 45 mt76_rx(&dev->mt76, q, skb); 46 return; 47 } 48 fallthrough; 49 default: 50 dev_kfree_skb(skb); 51 break; 52 } 53 } 54 55 static void 56 mt7915_tx_cleanup(struct mt7915_dev *dev) 57 { 58 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); 59 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], false); 60 } 61 62 static int mt7915_poll_tx(struct napi_struct *napi, int budget) 63 { 64 struct mt7915_dev *dev; 65 66 dev = container_of(napi, struct mt7915_dev, mt76.tx_napi); 67 68 mt7915_tx_cleanup(dev); 69 70 if (napi_complete_done(napi, 0)) 71 mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU); 72 73 return 0; 74 } 75 76 void mt7915_dma_prefetch(struct mt7915_dev *dev) 77 { 78 #define PREFETCH(base, depth) ((base) << 16 | (depth)) 79 80 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4)); 81 mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x40, 0x4)); 82 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x80, 0x0)); 83 84 mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL, PREFETCH(0x80, 0x4)); 85 mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL, PREFETCH(0xc0, 0x4)); 86 mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL, PREFETCH(0x100, 0x4)); 87 mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL, PREFETCH(0x140, 0x4)); 88 mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL, PREFETCH(0x180, 0x4)); 89 mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL, PREFETCH(0x1c0, 0x4)); 90 mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL, PREFETCH(0x200, 0x4)); 91 mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL, PREFETCH(0x240, 0x4)); 92 93 mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL, PREFETCH(0x280, 0x4)); 94 mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL, PREFETCH(0x2c0, 0x4)); 95 mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL, PREFETCH(0x300, 0x4)); 96 mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL, PREFETCH(0x340, 0x4)); 97 mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL, PREFETCH(0x380, 0x4)); 98 mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL, PREFETCH(0x3c0, 0x0)); 99 100 mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL, PREFETCH(0x3c0, 0x4)); 101 mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL, PREFETCH(0x400, 0x4)); 102 mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL, PREFETCH(0x440, 0x4)); 103 mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL, PREFETCH(0x480, 0x0)); 104 } 105 106 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 107 { 108 static const struct { 109 u32 phys; 110 u32 mapped; 111 u32 size; 112 } fixed_map[] = { 113 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ 114 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ 115 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 116 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 117 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 118 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 119 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 120 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 121 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 122 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 123 { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */ 124 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 125 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 126 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 127 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 128 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 129 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 130 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 131 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 132 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 133 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 134 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 135 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 136 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 137 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 138 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 139 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 140 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 141 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 142 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 143 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 144 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 145 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 146 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 147 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 148 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 149 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 150 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 151 }; 152 int i; 153 154 if (addr < 0x100000) 155 return addr; 156 157 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 158 u32 ofs; 159 160 if (addr < fixed_map[i].phys) 161 continue; 162 163 ofs = addr - fixed_map[i].phys; 164 if (ofs > fixed_map[i].size) 165 continue; 166 167 return fixed_map[i].mapped + ofs; 168 } 169 170 if ((addr >= 0x18000000 && addr < 0x18c00000) || 171 (addr >= 0x70000000 && addr < 0x78000000) || 172 (addr >= 0x7c000000 && addr < 0x7c400000)) 173 return mt7915_reg_map_l1(dev, addr); 174 175 return mt7915_reg_map_l2(dev, addr); 176 } 177 178 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 179 { 180 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 181 u32 addr = __mt7915_reg_addr(dev, offset); 182 183 return dev->bus_ops->rr(mdev, addr); 184 } 185 186 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 187 { 188 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 189 u32 addr = __mt7915_reg_addr(dev, offset); 190 191 dev->bus_ops->wr(mdev, addr, val); 192 } 193 194 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 195 { 196 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 197 u32 addr = __mt7915_reg_addr(dev, offset); 198 199 return dev->bus_ops->rmw(mdev, addr, mask, val); 200 } 201 202 int mt7915_dma_init(struct mt7915_dev *dev) 203 { 204 /* Increase buffer size to receive large VHT/HE MPDUs */ 205 struct mt76_bus_ops *bus_ops; 206 int rx_buf_size = MT_RX_BUF_SIZE * 2; 207 int ret; 208 209 dev->bus_ops = dev->mt76.bus; 210 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 211 GFP_KERNEL); 212 if (!bus_ops) 213 return -ENOMEM; 214 215 bus_ops->rr = mt7915_rr; 216 bus_ops->wr = mt7915_wr; 217 bus_ops->rmw = mt7915_rmw; 218 dev->mt76.bus = bus_ops; 219 220 mt76_dma_attach(&dev->mt76); 221 222 /* configure global setting */ 223 mt76_set(dev, MT_WFDMA1_GLO_CFG, 224 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 225 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 226 227 /* configure perfetch settings */ 228 mt7915_dma_prefetch(dev); 229 230 /* reset dma idx */ 231 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); 232 mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0); 233 234 /* configure delay interrupt */ 235 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); 236 mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0); 237 238 /* init tx queue */ 239 ret = mt7915_init_tx_queues(&dev->phy, MT7915_TXQ_BAND0, 240 MT7915_TX_RING_SIZE); 241 if (ret) 242 return ret; 243 244 /* command to WM */ 245 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7915_TXQ_MCU_WM, 246 MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 247 if (ret) 248 return ret; 249 250 /* command to WA */ 251 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, MT7915_TXQ_MCU_WA, 252 MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 253 if (ret) 254 return ret; 255 256 /* firmware download */ 257 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7915_TXQ_FWDL, 258 MT7915_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 259 if (ret) 260 return ret; 261 262 /* event from WM */ 263 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 264 MT7915_RXQ_MCU_WM, MT7915_RX_MCU_RING_SIZE, 265 rx_buf_size, MT_RX_EVENT_RING_BASE); 266 if (ret) 267 return ret; 268 269 /* event from WA */ 270 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 271 MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE, 272 rx_buf_size, MT_RX_EVENT_RING_BASE); 273 if (ret) 274 return ret; 275 276 /* rx data queue */ 277 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 278 MT7915_RXQ_BAND0, MT7915_RX_RING_SIZE, 279 rx_buf_size, MT_RX_DATA_RING_BASE); 280 if (ret) 281 return ret; 282 283 if (dev->dbdc_support) { 284 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT], 285 MT7915_RXQ_BAND1, MT7915_RX_RING_SIZE, 286 rx_buf_size, MT_RX_DATA_RING_BASE); 287 if (ret) 288 return ret; 289 } 290 291 ret = mt76_init_queues(dev); 292 if (ret < 0) 293 return ret; 294 295 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 296 mt7915_poll_tx, NAPI_POLL_WEIGHT); 297 napi_enable(&dev->mt76.tx_napi); 298 299 /* hif wait WFDMA idle */ 300 mt76_set(dev, MT_WFDMA0_BUSY_ENA, 301 MT_WFDMA0_BUSY_ENA_TX_FIFO0 | 302 MT_WFDMA0_BUSY_ENA_TX_FIFO1 | 303 MT_WFDMA0_BUSY_ENA_RX_FIFO); 304 305 mt76_set(dev, MT_WFDMA1_BUSY_ENA, 306 MT_WFDMA1_BUSY_ENA_TX_FIFO0 | 307 MT_WFDMA1_BUSY_ENA_TX_FIFO1 | 308 MT_WFDMA1_BUSY_ENA_RX_FIFO); 309 310 mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA, 311 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | 312 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | 313 MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); 314 315 mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA, 316 MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 | 317 MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 | 318 MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO); 319 320 mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, 321 MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); 322 323 /* set WFDMA Tx/Rx */ 324 mt76_set(dev, MT_WFDMA0_GLO_CFG, 325 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 326 mt76_set(dev, MT_WFDMA1_GLO_CFG, 327 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 328 329 /* enable interrupts for TX/RX rings */ 330 mt7915_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_MCU | 331 MT_INT_MCU_CMD); 332 333 return 0; 334 } 335 336 void mt7915_dma_cleanup(struct mt7915_dev *dev) 337 { 338 /* disable */ 339 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 340 MT_WFDMA0_GLO_CFG_TX_DMA_EN | 341 MT_WFDMA0_GLO_CFG_RX_DMA_EN); 342 mt76_clear(dev, MT_WFDMA1_GLO_CFG, 343 MT_WFDMA1_GLO_CFG_TX_DMA_EN | 344 MT_WFDMA1_GLO_CFG_RX_DMA_EN); 345 346 /* reset */ 347 mt76_clear(dev, MT_WFDMA1_RST, 348 MT_WFDMA1_RST_DMASHDL_ALL_RST | 349 MT_WFDMA1_RST_LOGIC_RST); 350 351 mt76_set(dev, MT_WFDMA1_RST, 352 MT_WFDMA1_RST_DMASHDL_ALL_RST | 353 MT_WFDMA1_RST_LOGIC_RST); 354 355 mt76_clear(dev, MT_WFDMA0_RST, 356 MT_WFDMA0_RST_DMASHDL_ALL_RST | 357 MT_WFDMA0_RST_LOGIC_RST); 358 359 mt76_set(dev, MT_WFDMA0_RST, 360 MT_WFDMA0_RST_DMASHDL_ALL_RST | 361 MT_WFDMA0_RST_LOGIC_RST); 362 363 mt76_dma_cleanup(&dev->mt76); 364 } 365