1e57b7901SRyder Lee // SPDX-License-Identifier: ISC 2e57b7901SRyder Lee /* Copyright (C) 2020 MediaTek Inc. */ 3e57b7901SRyder Lee 4e57b7901SRyder Lee #include "mt7915.h" 5e57b7901SRyder Lee #include "../dma.h" 6e57b7901SRyder Lee #include "mac.h" 7e57b7901SRyder Lee 87b8e1ae8SFelix Fietkau static int 97b8e1ae8SFelix Fietkau mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base) 10e57b7901SRyder Lee { 11f68d6762SFelix Fietkau struct mt7915_dev *dev = phy->dev; 12e57b7901SRyder Lee 13f68d6762SFelix Fietkau if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { 14eebb7097SLorenzo Bianconi if (is_mt7986(&dev->mt76)) 15eebb7097SLorenzo Bianconi ring_base += MT_TXQ_ID(0) * MT_RING_SIZE; 16eebb7097SLorenzo Bianconi else 17f68d6762SFelix Fietkau ring_base = MT_WED_TX_RING_BASE; 18eebb7097SLorenzo Bianconi 19f68d6762SFelix Fietkau idx -= MT_TXQ_ID(0); 20f68d6762SFelix Fietkau } 21f68d6762SFelix Fietkau 229dfb28e9SLorenzo Bianconi return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, ring_base, 23f68d6762SFelix Fietkau MT_WED_Q_TX(idx)); 24dc076af5SRyder Lee } 25dc076af5SRyder Lee 26e57b7901SRyder Lee static int mt7915_poll_tx(struct napi_struct *napi, int budget) 27e57b7901SRyder Lee { 28e57b7901SRyder Lee struct mt7915_dev *dev; 29e57b7901SRyder Lee 30e57b7901SRyder Lee dev = container_of(napi, struct mt7915_dev, mt76.tx_napi); 31e57b7901SRyder Lee 329dfb28e9SLorenzo Bianconi mt76_connac_tx_cleanup(&dev->mt76); 3338b04398SFelix Fietkau if (napi_complete_done(napi, 0)) 34f8a667a9SFelix Fietkau mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU); 3538b04398SFelix Fietkau 36e57b7901SRyder Lee return 0; 37e57b7901SRyder Lee } 38e57b7901SRyder Lee 39cd4c314aSBo Jiao static void mt7915_dma_config(struct mt7915_dev *dev) 40cd4c314aSBo Jiao { 41cd4c314aSBo Jiao #define Q_CONFIG(q, wfdma, int, id) do { \ 42cd4c314aSBo Jiao if (wfdma) \ 43cd4c314aSBo Jiao dev->wfdma_mask |= (1 << (q)); \ 44cd4c314aSBo Jiao dev->q_int_mask[(q)] = int; \ 45cd4c314aSBo Jiao dev->q_id[(q)] = id; \ 46cd4c314aSBo Jiao } while (0) 47cd4c314aSBo Jiao 48cd4c314aSBo Jiao #define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id)) 49cd4c314aSBo Jiao #define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id)) 50cd4c314aSBo Jiao #define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id)) 51cd4c314aSBo Jiao 52cd4c314aSBo Jiao if (is_mt7915(&dev->mt76)) { 53d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, 54d493bb5bSBo Jiao MT7915_RXQ_BAND0); 55d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_MCU, WFDMA1, MT_INT_RX_DONE_WM, 56d493bb5bSBo Jiao MT7915_RXQ_MCU_WM); 57d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA1, MT_INT_RX_DONE_WA, 58d493bb5bSBo Jiao MT7915_RXQ_MCU_WA); 59d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, 60d493bb5bSBo Jiao MT7915_RXQ_BAND1); 61d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA1, MT_INT_RX_DONE_WA_EXT, 62d493bb5bSBo Jiao MT7915_RXQ_MCU_WA_EXT); 63d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA1, MT_INT_RX_DONE_WA_MAIN, 64d493bb5bSBo Jiao MT7915_RXQ_MCU_WA); 65cd4c314aSBo Jiao TXQ_CONFIG(0, WFDMA1, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0); 66cd4c314aSBo Jiao TXQ_CONFIG(1, WFDMA1, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1); 67d493bb5bSBo Jiao MCUQ_CONFIG(MT_MCUQ_WM, WFDMA1, MT_INT_TX_DONE_MCU_WM, 68d493bb5bSBo Jiao MT7915_TXQ_MCU_WM); 69d493bb5bSBo Jiao MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, 70d493bb5bSBo Jiao MT7915_TXQ_MCU_WA); 71d493bb5bSBo Jiao MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, 72d493bb5bSBo Jiao MT7915_TXQ_FWDL); 73cd4c314aSBo Jiao } else { 74d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, 75d493bb5bSBo Jiao MT7916_RXQ_MCU_WM); 76d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, 77d493bb5bSBo Jiao MT7916_RXQ_MCU_WA_EXT); 78d493bb5bSBo Jiao MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, 79d493bb5bSBo Jiao MT7915_TXQ_MCU_WM); 80d493bb5bSBo Jiao MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, 81d493bb5bSBo Jiao MT7915_TXQ_MCU_WA); 82d493bb5bSBo Jiao MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, 83d493bb5bSBo Jiao MT7915_TXQ_FWDL); 84eebb7097SLorenzo Bianconi 85eebb7097SLorenzo Bianconi if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) { 86eebb7097SLorenzo Bianconi RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_WED_RX_DONE_BAND0_MT7916, 87eebb7097SLorenzo Bianconi MT7916_RXQ_BAND0); 88eebb7097SLorenzo Bianconi RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MT7916, 89eebb7097SLorenzo Bianconi MT7916_RXQ_MCU_WA); 90eebb7097SLorenzo Bianconi RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916, 91eebb7097SLorenzo Bianconi MT7916_RXQ_BAND1); 92eebb7097SLorenzo Bianconi RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MAIN_MT7916, 93eebb7097SLorenzo Bianconi MT7916_RXQ_MCU_WA_MAIN); 94d493bb5bSBo Jiao TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0, 95d493bb5bSBo Jiao MT7915_TXQ_BAND0); 96d493bb5bSBo Jiao TXQ_CONFIG(1, WFDMA0, MT_INT_WED_TX_DONE_BAND1, 97d493bb5bSBo Jiao MT7915_TXQ_BAND1); 98eebb7097SLorenzo Bianconi } else { 99d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, 100d493bb5bSBo Jiao MT7916_RXQ_BAND0); 101d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, 102d493bb5bSBo Jiao MT7916_RXQ_MCU_WA); 103d493bb5bSBo Jiao RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, 104d493bb5bSBo Jiao MT7916_RXQ_BAND1); 105eebb7097SLorenzo Bianconi RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, 106eebb7097SLorenzo Bianconi MT7916_RXQ_MCU_WA_MAIN); 107d493bb5bSBo Jiao TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, 108d493bb5bSBo Jiao MT7915_TXQ_BAND0); 109d493bb5bSBo Jiao TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, 110d493bb5bSBo Jiao MT7915_TXQ_BAND1); 111eebb7097SLorenzo Bianconi } 112cd4c314aSBo Jiao } 113cd4c314aSBo Jiao } 114cd4c314aSBo Jiao 1159093cfffSFelix Fietkau static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs) 116e57b7901SRyder Lee { 117cd4c314aSBo Jiao #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) 118aa79fe87SBo Jiao u32 base = 0; 119e57b7901SRyder Lee 120cd4c314aSBo Jiao /* prefetch SRAM wrapping boundary for tx/rx ring. */ 121cd4c314aSBo Jiao mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x4)); 122cd4c314aSBo Jiao mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x40, 0x4)); 123cd4c314aSBo Jiao mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x80, 0x4)); 124cd4c314aSBo Jiao mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0xc0, 0x4)); 125cd4c314aSBo Jiao mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x100, 0x4)); 126e57b7901SRyder Lee 127fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, 128fc8f841bSLorenzo Bianconi PREFETCH(0x140, 0x4)); 129fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, 130fc8f841bSLorenzo Bianconi PREFETCH(0x180, 0x4)); 131aa79fe87SBo Jiao if (!is_mt7915(&dev->mt76)) { 132fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, 133fc8f841bSLorenzo Bianconi PREFETCH(0x1c0, 0x4)); 134aa79fe87SBo Jiao base = 0x40; 135aa79fe87SBo Jiao } 136fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1_WA) + ofs, 137fc8f841bSLorenzo Bianconi PREFETCH(0x1c0 + base, 0x4)); 138fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, 139fc8f841bSLorenzo Bianconi PREFETCH(0x200 + base, 0x4)); 140fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1) + ofs, 141fc8f841bSLorenzo Bianconi PREFETCH(0x240 + base, 0x4)); 142e57b7901SRyder Lee 143cd4c314aSBo Jiao /* for mt7915, the ring which is next the last 144cd4c314aSBo Jiao * used ring must be initialized. 145cd4c314aSBo Jiao */ 146cd4c314aSBo Jiao if (is_mt7915(&dev->mt76)) { 147cd4c314aSBo Jiao ofs += 0x4; 148fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, 149fc8f841bSLorenzo Bianconi PREFETCH(0x140, 0x0)); 150fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1_WA) + ofs, 151fc8f841bSLorenzo Bianconi PREFETCH(0x200 + base, 0x0)); 152fc8f841bSLorenzo Bianconi mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1) + ofs, 153fc8f841bSLorenzo Bianconi PREFETCH(0x280 + base, 0x0)); 154cd4c314aSBo Jiao } 1559093cfffSFelix Fietkau } 1569093cfffSFelix Fietkau 1579093cfffSFelix Fietkau void mt7915_dma_prefetch(struct mt7915_dev *dev) 1589093cfffSFelix Fietkau { 1599093cfffSFelix Fietkau __mt7915_dma_prefetch(dev, 0); 1609093cfffSFelix Fietkau if (dev->hif2) 161cd4c314aSBo Jiao __mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); 162e57b7901SRyder Lee } 163e57b7901SRyder Lee 164aa79fe87SBo Jiao static void mt7915_dma_disable(struct mt7915_dev *dev, bool rst) 165aa79fe87SBo Jiao { 166aa79fe87SBo Jiao struct mt76_dev *mdev = &dev->mt76; 167aa79fe87SBo Jiao u32 hif1_ofs = 0; 168aa79fe87SBo Jiao 169aa79fe87SBo Jiao if (dev->hif2) 170aa79fe87SBo Jiao hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 171aa79fe87SBo Jiao 172aa79fe87SBo Jiao /* reset */ 173aa79fe87SBo Jiao if (rst) { 174aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_RST, 175aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 176aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 177aa79fe87SBo Jiao 178aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_RST, 179aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 180aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 181aa79fe87SBo Jiao 182aa79fe87SBo Jiao if (is_mt7915(mdev)) { 183aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_RST, 184aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 185aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 186aa79fe87SBo Jiao 187aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_RST, 188aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 189aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 190aa79fe87SBo Jiao } 191aa79fe87SBo Jiao 192aa79fe87SBo Jiao if (dev->hif2) { 193aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs, 194aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 195aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 196aa79fe87SBo Jiao 197aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_RST + hif1_ofs, 198aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 199aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 200aa79fe87SBo Jiao 201aa79fe87SBo Jiao if (is_mt7915(mdev)) { 202aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_RST + hif1_ofs, 203aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 204aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 205aa79fe87SBo Jiao 206aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_RST + hif1_ofs, 207aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 208aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 209aa79fe87SBo Jiao } 210aa79fe87SBo Jiao } 211aa79fe87SBo Jiao } 212aa79fe87SBo Jiao 213aa79fe87SBo Jiao /* disable */ 214aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_GLO_CFG, 215aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 216aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 217aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 218aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | 219aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 220aa79fe87SBo Jiao 221aa79fe87SBo Jiao if (is_mt7915(mdev)) 222aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_GLO_CFG, 223aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 224aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 225aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 226aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO | 227aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2); 228aa79fe87SBo Jiao 229aa79fe87SBo Jiao if (dev->hif2) { 230aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 231aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 232aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 233aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 234aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | 235aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 236aa79fe87SBo Jiao 237aa79fe87SBo Jiao if (is_mt7915(mdev)) 238aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 239aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 240aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 241aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 242aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO | 243aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2); 244aa79fe87SBo Jiao } 245aa79fe87SBo Jiao } 246aa79fe87SBo Jiao 247aa79fe87SBo Jiao static int mt7915_dma_enable(struct mt7915_dev *dev) 248aa79fe87SBo Jiao { 249aa79fe87SBo Jiao struct mt76_dev *mdev = &dev->mt76; 250aa79fe87SBo Jiao u32 hif1_ofs = 0; 251aa79fe87SBo Jiao u32 irq_mask; 252aa79fe87SBo Jiao 253aa79fe87SBo Jiao if (dev->hif2) 254aa79fe87SBo Jiao hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 255aa79fe87SBo Jiao 256aa79fe87SBo Jiao /* reset dma idx */ 257aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); 258aa79fe87SBo Jiao if (is_mt7915(mdev)) 259aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0); 260aa79fe87SBo Jiao if (dev->hif2) { 261aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0); 262aa79fe87SBo Jiao if (is_mt7915(mdev)) 263aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0); 264aa79fe87SBo Jiao } 265aa79fe87SBo Jiao 266aa79fe87SBo Jiao /* configure delay interrupt off */ 267aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); 268aa79fe87SBo Jiao if (is_mt7915(mdev)) { 269aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0); 270aa79fe87SBo Jiao } else { 271aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0); 272aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0); 273aa79fe87SBo Jiao } 274aa79fe87SBo Jiao 275aa79fe87SBo Jiao if (dev->hif2) { 276aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0); 277aa79fe87SBo Jiao if (is_mt7915(mdev)) { 278aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0 + 279aa79fe87SBo Jiao hif1_ofs, 0); 280aa79fe87SBo Jiao } else { 281aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + 282aa79fe87SBo Jiao hif1_ofs, 0); 283aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + 284aa79fe87SBo Jiao hif1_ofs, 0); 285aa79fe87SBo Jiao } 286aa79fe87SBo Jiao } 287aa79fe87SBo Jiao 288aa79fe87SBo Jiao /* configure perfetch settings */ 289aa79fe87SBo Jiao mt7915_dma_prefetch(dev); 290aa79fe87SBo Jiao 291aa79fe87SBo Jiao /* hif wait WFDMA idle */ 292aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_BUSY_ENA, 293aa79fe87SBo Jiao MT_WFDMA0_BUSY_ENA_TX_FIFO0 | 294aa79fe87SBo Jiao MT_WFDMA0_BUSY_ENA_TX_FIFO1 | 295aa79fe87SBo Jiao MT_WFDMA0_BUSY_ENA_RX_FIFO); 296aa79fe87SBo Jiao 297aa79fe87SBo Jiao if (is_mt7915(mdev)) 298aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_BUSY_ENA, 299aa79fe87SBo Jiao MT_WFDMA1_BUSY_ENA_TX_FIFO0 | 300aa79fe87SBo Jiao MT_WFDMA1_BUSY_ENA_TX_FIFO1 | 301aa79fe87SBo Jiao MT_WFDMA1_BUSY_ENA_RX_FIFO); 302aa79fe87SBo Jiao 303aa79fe87SBo Jiao if (dev->hif2) { 304aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs, 305aa79fe87SBo Jiao MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | 306aa79fe87SBo Jiao MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | 307aa79fe87SBo Jiao MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); 308aa79fe87SBo Jiao 309aa79fe87SBo Jiao if (is_mt7915(mdev)) 310aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_BUSY_ENA + hif1_ofs, 311aa79fe87SBo Jiao MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 | 312aa79fe87SBo Jiao MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 | 313aa79fe87SBo Jiao MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO); 314aa79fe87SBo Jiao } 315aa79fe87SBo Jiao 316aa79fe87SBo Jiao mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, 317aa79fe87SBo Jiao MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); 318aa79fe87SBo Jiao 319aa79fe87SBo Jiao /* set WFDMA Tx/Rx */ 320aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_GLO_CFG, 321aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 322aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 323aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 324aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 325aa79fe87SBo Jiao 326aa79fe87SBo Jiao if (is_mt7915(mdev)) 327aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_GLO_CFG, 328aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 329aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 330aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 331aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 332aa79fe87SBo Jiao 333aa79fe87SBo Jiao if (dev->hif2) { 334aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 335aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 336aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 337aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 338aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 339aa79fe87SBo Jiao 340aa79fe87SBo Jiao if (is_mt7915(mdev)) 341aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 342aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 343aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 344aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 345aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 346aa79fe87SBo Jiao 347aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA_HOST_CONFIG, 348aa79fe87SBo Jiao MT_WFDMA_HOST_CONFIG_PDMA_BAND); 349aa79fe87SBo Jiao } 350aa79fe87SBo Jiao 351aa79fe87SBo Jiao /* enable interrupts for TX/RX rings */ 352aa79fe87SBo Jiao irq_mask = MT_INT_RX_DONE_MCU | 353aa79fe87SBo Jiao MT_INT_TX_DONE_MCU | 354006b9d4aSBo Jiao MT_INT_MCU_CMD; 355aa79fe87SBo Jiao 3563eb50cc9SRyder Lee if (!dev->phy.mt76->band_idx) 357006b9d4aSBo Jiao irq_mask |= MT_INT_BAND0_RX_DONE; 358006b9d4aSBo Jiao 3593eb50cc9SRyder Lee if (dev->dbdc_support || dev->phy.mt76->band_idx) 360aa79fe87SBo Jiao irq_mask |= MT_INT_BAND1_RX_DONE; 361aa79fe87SBo Jiao 362f68d6762SFelix Fietkau if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 363f68d6762SFelix Fietkau u32 wed_irq_mask = irq_mask; 364c6cde7b7SSujuan Chen int ret; 365f68d6762SFelix Fietkau 366f68d6762SFelix Fietkau wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1; 367eebb7097SLorenzo Bianconi if (!is_mt7986(&dev->mt76)) 368f68d6762SFelix Fietkau mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask); 3694f831d18SLorenzo Bianconi else 370b7ebf46eSLorenzo Bianconi mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); 371c6cde7b7SSujuan Chen 372c6cde7b7SSujuan Chen ret = mt7915_mcu_wed_enable_rx_stats(dev); 373c6cde7b7SSujuan Chen if (ret) 374c6cde7b7SSujuan Chen return ret; 375c6cde7b7SSujuan Chen 376f68d6762SFelix Fietkau mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask); 377f68d6762SFelix Fietkau } 378f68d6762SFelix Fietkau 379aa79fe87SBo Jiao mt7915_irq_enable(dev, irq_mask); 380aa79fe87SBo Jiao 381aa79fe87SBo Jiao return 0; 382aa79fe87SBo Jiao } 383aa79fe87SBo Jiao 3847b8e1ae8SFelix Fietkau int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) 385e57b7901SRyder Lee { 386aa79fe87SBo Jiao struct mt76_dev *mdev = &dev->mt76; 387f68d6762SFelix Fietkau u32 wa_rx_base, wa_rx_idx; 3889093cfffSFelix Fietkau u32 hif1_ofs = 0; 389e57b7901SRyder Lee int ret; 390e57b7901SRyder Lee 391cd4c314aSBo Jiao mt7915_dma_config(dev); 392cd4c314aSBo Jiao 393e57b7901SRyder Lee mt76_dma_attach(&dev->mt76); 394e57b7901SRyder Lee 3959093cfffSFelix Fietkau if (dev->hif2) 396cd4c314aSBo Jiao hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 3979093cfffSFelix Fietkau 398aa79fe87SBo Jiao mt7915_dma_disable(dev, true); 3999093cfffSFelix Fietkau 400eebb7097SLorenzo Bianconi if (mtk_wed_device_active(&mdev->mmio.wed)) { 401eebb7097SLorenzo Bianconi if (!is_mt7986(mdev)) { 402eebb7097SLorenzo Bianconi u8 wed_control_rx1 = is_mt7915(mdev) ? 1 : 2; 403f68d6762SFelix Fietkau 404eebb7097SLorenzo Bianconi mt76_set(dev, MT_WFDMA_HOST_CONFIG, 405eebb7097SLorenzo Bianconi MT_WFDMA_HOST_CONFIG_WED); 406f68d6762SFelix Fietkau mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL, 407f68d6762SFelix Fietkau FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) | 408f68d6762SFelix Fietkau FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) | 409eebb7097SLorenzo Bianconi FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 410eebb7097SLorenzo Bianconi wed_control_rx1)); 4114f831d18SLorenzo Bianconi if (is_mt7915(mdev)) 4124f831d18SLorenzo Bianconi mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP, 4134f831d18SLorenzo Bianconi MT_WFDMA0_EXT0_RXWB_KEEP); 414eebb7097SLorenzo Bianconi } 415f68d6762SFelix Fietkau } else { 416f68d6762SFelix Fietkau mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); 417f68d6762SFelix Fietkau } 418f68d6762SFelix Fietkau 419e57b7901SRyder Lee /* init tx queue */ 420cd4c314aSBo Jiao ret = mt7915_init_tx_queues(&dev->phy, 4213eb50cc9SRyder Lee MT_TXQ_ID(dev->phy.mt76->band_idx), 422cd4c314aSBo Jiao MT7915_TX_RING_SIZE, 423cd4c314aSBo Jiao MT_TXQ_RING_BASE(0)); 424e57b7901SRyder Lee if (ret) 425e57b7901SRyder Lee return ret; 426e57b7901SRyder Lee 4277b8e1ae8SFelix Fietkau if (phy2) { 4287b8e1ae8SFelix Fietkau ret = mt7915_init_tx_queues(phy2, 4293eb50cc9SRyder Lee MT_TXQ_ID(phy2->mt76->band_idx), 4307b8e1ae8SFelix Fietkau MT7915_TX_RING_SIZE, 4317b8e1ae8SFelix Fietkau MT_TXQ_RING_BASE(1)); 4327b8e1ae8SFelix Fietkau if (ret) 4337b8e1ae8SFelix Fietkau return ret; 4347b8e1ae8SFelix Fietkau } 4357b8e1ae8SFelix Fietkau 436e57b7901SRyder Lee /* command to WM */ 437cd4c314aSBo Jiao ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, 438cd4c314aSBo Jiao MT_MCUQ_ID(MT_MCUQ_WM), 439cd4c314aSBo Jiao MT7915_TX_MCU_RING_SIZE, 440cd4c314aSBo Jiao MT_MCUQ_RING_BASE(MT_MCUQ_WM)); 441e57b7901SRyder Lee if (ret) 442e57b7901SRyder Lee return ret; 443e57b7901SRyder Lee 444e57b7901SRyder Lee /* command to WA */ 445cd4c314aSBo Jiao ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, 446cd4c314aSBo Jiao MT_MCUQ_ID(MT_MCUQ_WA), 447cd4c314aSBo Jiao MT7915_TX_MCU_RING_SIZE, 448cd4c314aSBo Jiao MT_MCUQ_RING_BASE(MT_MCUQ_WA)); 449e57b7901SRyder Lee if (ret) 450e57b7901SRyder Lee return ret; 451e57b7901SRyder Lee 452e57b7901SRyder Lee /* firmware download */ 453cd4c314aSBo Jiao ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, 454cd4c314aSBo Jiao MT_MCUQ_ID(MT_MCUQ_FWDL), 455cd4c314aSBo Jiao MT7915_TX_FWDL_RING_SIZE, 456cd4c314aSBo Jiao MT_MCUQ_RING_BASE(MT_MCUQ_FWDL)); 457e57b7901SRyder Lee if (ret) 458e57b7901SRyder Lee return ret; 459e57b7901SRyder Lee 460e57b7901SRyder Lee /* event from WM */ 461e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 462cd4c314aSBo Jiao MT_RXQ_ID(MT_RXQ_MCU), 463cd4c314aSBo Jiao MT7915_RX_MCU_RING_SIZE, 464cd4c314aSBo Jiao MT_RX_BUF_SIZE, 465cd4c314aSBo Jiao MT_RXQ_RING_BASE(MT_RXQ_MCU)); 466e57b7901SRyder Lee if (ret) 467e57b7901SRyder Lee return ret; 468e57b7901SRyder Lee 469e57b7901SRyder Lee /* event from WA */ 470eebb7097SLorenzo Bianconi if (mtk_wed_device_active(&mdev->mmio.wed) && is_mt7915(mdev)) { 471f68d6762SFelix Fietkau wa_rx_base = MT_WED_RX_RING_BASE; 472f68d6762SFelix Fietkau wa_rx_idx = MT7915_RXQ_MCU_WA; 473f68d6762SFelix Fietkau dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE; 474f68d6762SFelix Fietkau } else { 475f68d6762SFelix Fietkau wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA); 476f68d6762SFelix Fietkau wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA); 477f68d6762SFelix Fietkau } 478e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 479f68d6762SFelix Fietkau wa_rx_idx, MT7915_RX_MCU_RING_SIZE, 480f68d6762SFelix Fietkau MT_RX_BUF_SIZE, wa_rx_base); 481e57b7901SRyder Lee if (ret) 482e57b7901SRyder Lee return ret; 483e57b7901SRyder Lee 484aa79fe87SBo Jiao /* rx data queue for band0 */ 4853eb50cc9SRyder Lee if (!dev->phy.mt76->band_idx) { 4864f831d18SLorenzo Bianconi if (mtk_wed_device_active(&mdev->mmio.wed) && 4874f831d18SLorenzo Bianconi mtk_wed_get_rx_capa(&mdev->mmio.wed)) { 4884f831d18SLorenzo Bianconi dev->mt76.q_rx[MT_RXQ_MAIN].flags = 4894f831d18SLorenzo Bianconi MT_WED_Q_RX(MT7915_RXQ_BAND0); 4904f831d18SLorenzo Bianconi dev->mt76.rx_token_size += MT7915_RX_RING_SIZE; 4914f831d18SLorenzo Bianconi } 4924f831d18SLorenzo Bianconi 4934c430774SLorenzo Bianconi ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 494cd4c314aSBo Jiao MT_RXQ_ID(MT_RXQ_MAIN), 495cd4c314aSBo Jiao MT7915_RX_RING_SIZE, 496cd4c314aSBo Jiao MT_RX_BUF_SIZE, 497cd4c314aSBo Jiao MT_RXQ_RING_BASE(MT_RXQ_MAIN)); 498e57b7901SRyder Lee if (ret) 499e57b7901SRyder Lee return ret; 500006b9d4aSBo Jiao } 501e57b7901SRyder Lee 502aa79fe87SBo Jiao /* tx free notify event from WA for band0 */ 503aa79fe87SBo Jiao if (!is_mt7915(mdev)) { 504eebb7097SLorenzo Bianconi wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA); 505eebb7097SLorenzo Bianconi wa_rx_idx = MT_RXQ_ID(MT_RXQ_MAIN_WA); 506eebb7097SLorenzo Bianconi 507eebb7097SLorenzo Bianconi if (mtk_wed_device_active(&mdev->mmio.wed)) { 508eebb7097SLorenzo Bianconi mdev->q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE; 509eebb7097SLorenzo Bianconi if (is_mt7916(mdev)) { 510eebb7097SLorenzo Bianconi wa_rx_base = MT_WED_RX_RING_BASE; 511eebb7097SLorenzo Bianconi wa_rx_idx = MT7915_RXQ_MCU_WA; 512eebb7097SLorenzo Bianconi } 513eebb7097SLorenzo Bianconi } 514eebb7097SLorenzo Bianconi 515aa79fe87SBo Jiao ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], 516eebb7097SLorenzo Bianconi wa_rx_idx, MT7915_RX_MCU_RING_SIZE, 517eebb7097SLorenzo Bianconi MT_RX_BUF_SIZE, wa_rx_base); 518aa79fe87SBo Jiao if (ret) 519aa79fe87SBo Jiao return ret; 520aa79fe87SBo Jiao } 521aa79fe87SBo Jiao 5223eb50cc9SRyder Lee if (dev->dbdc_support || dev->phy.mt76->band_idx) { 5234f831d18SLorenzo Bianconi if (mtk_wed_device_active(&mdev->mmio.wed) && 5244f831d18SLorenzo Bianconi mtk_wed_get_rx_capa(&mdev->mmio.wed)) { 5254f831d18SLorenzo Bianconi dev->mt76.q_rx[MT_RXQ_BAND1].flags = 5264f831d18SLorenzo Bianconi MT_WED_Q_RX(MT7915_RXQ_BAND1); 5274f831d18SLorenzo Bianconi dev->mt76.rx_token_size += MT7915_RX_RING_SIZE; 5284f831d18SLorenzo Bianconi } 5294f831d18SLorenzo Bianconi 530aa79fe87SBo Jiao /* rx data queue for band1 */ 531fc8f841bSLorenzo Bianconi ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1], 532fc8f841bSLorenzo Bianconi MT_RXQ_ID(MT_RXQ_BAND1), 533cd4c314aSBo Jiao MT7915_RX_RING_SIZE, 53449c9a263SLorenzo Bianconi MT_RX_BUF_SIZE, 535fc8f841bSLorenzo Bianconi MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs); 5364c430774SLorenzo Bianconi if (ret) 5374c430774SLorenzo Bianconi return ret; 53876027f40SFelix Fietkau 539aa79fe87SBo Jiao /* tx free notify event from WA for band1 */ 540fc8f841bSLorenzo Bianconi ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA], 541fc8f841bSLorenzo Bianconi MT_RXQ_ID(MT_RXQ_BAND1_WA), 54276027f40SFelix Fietkau MT7915_RX_MCU_RING_SIZE, 54349c9a263SLorenzo Bianconi MT_RX_BUF_SIZE, 544fc8f841bSLorenzo Bianconi MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs); 54576027f40SFelix Fietkau if (ret) 54676027f40SFelix Fietkau return ret; 5474c430774SLorenzo Bianconi } 5484c430774SLorenzo Bianconi 549cb8ed33dSLorenzo Bianconi ret = mt76_init_queues(dev, mt76_dma_rx_poll); 550e57b7901SRyder Lee if (ret < 0) 551e57b7901SRyder Lee return ret; 552e57b7901SRyder Lee 5533ed27b60SJakub Kicinski netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 5543ed27b60SJakub Kicinski mt7915_poll_tx); 555e57b7901SRyder Lee napi_enable(&dev->mt76.tx_napi); 556e57b7901SRyder Lee 557aa79fe87SBo Jiao mt7915_dma_enable(dev); 558e57b7901SRyder Lee 559e57b7901SRyder Lee return 0; 560e57b7901SRyder Lee } 561e57b7901SRyder Lee 56236b7fce1SLorenzo Bianconi static void mt7915_dma_wed_reset(struct mt7915_dev *dev) 56336b7fce1SLorenzo Bianconi { 56436b7fce1SLorenzo Bianconi struct mt76_dev *mdev = &dev->mt76; 56536b7fce1SLorenzo Bianconi 56636b7fce1SLorenzo Bianconi if (!test_bit(MT76_STATE_WED_RESET, &dev->mphy.state)) 56736b7fce1SLorenzo Bianconi return; 56836b7fce1SLorenzo Bianconi 56936b7fce1SLorenzo Bianconi complete(&mdev->mmio.wed_reset); 57036b7fce1SLorenzo Bianconi 57136b7fce1SLorenzo Bianconi if (!wait_for_completion_timeout(&dev->mt76.mmio.wed_reset_complete, 57236b7fce1SLorenzo Bianconi 3 * HZ)) 57336b7fce1SLorenzo Bianconi dev_err(dev->mt76.dev, "wed reset complete timeout\n"); 57436b7fce1SLorenzo Bianconi } 57536b7fce1SLorenzo Bianconi 576*c2b9fb63SLorenzo Bianconi static void 577*c2b9fb63SLorenzo Bianconi mt7915_dma_reset_tx_queue(struct mt7915_dev *dev, struct mt76_queue *q) 578*c2b9fb63SLorenzo Bianconi { 579*c2b9fb63SLorenzo Bianconi mt76_queue_reset(dev, q); 580*c2b9fb63SLorenzo Bianconi if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 581*c2b9fb63SLorenzo Bianconi mt76_dma_wed_setup(&dev->mt76, q, true); 582*c2b9fb63SLorenzo Bianconi } 583*c2b9fb63SLorenzo Bianconi 584d493bb5bSBo Jiao int mt7915_dma_reset(struct mt7915_dev *dev, bool force) 585d493bb5bSBo Jiao { 586d493bb5bSBo Jiao struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 587*c2b9fb63SLorenzo Bianconi struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 588d493bb5bSBo Jiao int i; 589d493bb5bSBo Jiao 590d493bb5bSBo Jiao /* clean up hw queues */ 591d493bb5bSBo Jiao for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++) { 592d493bb5bSBo Jiao mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 593d493bb5bSBo Jiao if (mphy_ext) 594d493bb5bSBo Jiao mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true); 595d493bb5bSBo Jiao } 596d493bb5bSBo Jiao 597d493bb5bSBo Jiao for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++) 598d493bb5bSBo Jiao mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); 599d493bb5bSBo Jiao 600d493bb5bSBo Jiao mt76_for_each_q_rx(&dev->mt76, i) 601d493bb5bSBo Jiao mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]); 602d493bb5bSBo Jiao 603d493bb5bSBo Jiao /* reset wfsys */ 604d493bb5bSBo Jiao if (force) 605d493bb5bSBo Jiao mt7915_wfsys_reset(dev); 606d493bb5bSBo Jiao 607*c2b9fb63SLorenzo Bianconi if (mtk_wed_device_active(wed)) 608*c2b9fb63SLorenzo Bianconi mtk_wed_device_dma_reset(wed); 609*c2b9fb63SLorenzo Bianconi 610d493bb5bSBo Jiao mt7915_dma_disable(dev, force); 61136b7fce1SLorenzo Bianconi mt7915_dma_wed_reset(dev); 612d493bb5bSBo Jiao 613d493bb5bSBo Jiao /* reset hw queues */ 614d493bb5bSBo Jiao for (i = 0; i < __MT_TXQ_MAX; i++) { 615*c2b9fb63SLorenzo Bianconi mt7915_dma_reset_tx_queue(dev, dev->mphy.q_tx[i]); 616d493bb5bSBo Jiao if (mphy_ext) 617*c2b9fb63SLorenzo Bianconi mt7915_dma_reset_tx_queue(dev, mphy_ext->q_tx[i]); 618d493bb5bSBo Jiao } 619d493bb5bSBo Jiao 620d493bb5bSBo Jiao for (i = 0; i < __MT_MCUQ_MAX; i++) 621d493bb5bSBo Jiao mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 622d493bb5bSBo Jiao 623*c2b9fb63SLorenzo Bianconi mt76_for_each_q_rx(&dev->mt76, i) { 624*c2b9fb63SLorenzo Bianconi if (dev->mt76.q_rx[i].flags == MT_WED_Q_TXFREE) 625*c2b9fb63SLorenzo Bianconi continue; 626*c2b9fb63SLorenzo Bianconi 627d493bb5bSBo Jiao mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 628*c2b9fb63SLorenzo Bianconi } 629d493bb5bSBo Jiao 630d493bb5bSBo Jiao mt76_tx_status_check(&dev->mt76, true); 631d493bb5bSBo Jiao 632d493bb5bSBo Jiao mt76_for_each_q_rx(&dev->mt76, i) 633d493bb5bSBo Jiao mt76_queue_rx_reset(dev, i); 634d493bb5bSBo Jiao 635*c2b9fb63SLorenzo Bianconi if (mtk_wed_device_active(wed) && is_mt7915(&dev->mt76)) 636*c2b9fb63SLorenzo Bianconi mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP, 637*c2b9fb63SLorenzo Bianconi MT_WFDMA0_EXT0_RXWB_KEEP); 638*c2b9fb63SLorenzo Bianconi 639*c2b9fb63SLorenzo Bianconi mt7915_dma_enable(dev); 640*c2b9fb63SLorenzo Bianconi 641d493bb5bSBo Jiao return 0; 642d493bb5bSBo Jiao } 643d493bb5bSBo Jiao 644e57b7901SRyder Lee void mt7915_dma_cleanup(struct mt7915_dev *dev) 645e57b7901SRyder Lee { 646aa79fe87SBo Jiao mt7915_dma_disable(dev, true); 647e57b7901SRyder Lee 648e57b7901SRyder Lee mt76_dma_cleanup(&dev->mt76); 649e57b7901SRyder Lee } 650