1e57b7901SRyder Lee // SPDX-License-Identifier: ISC 2e57b7901SRyder Lee /* Copyright (C) 2020 MediaTek Inc. */ 3e57b7901SRyder Lee 4e57b7901SRyder Lee #include "mt7915.h" 5e57b7901SRyder Lee #include "../dma.h" 6e57b7901SRyder Lee #include "mac.h" 7e57b7901SRyder Lee 8e57b7901SRyder Lee static int 9*b671da33SLorenzo Bianconi mt7915_init_tx_queues(struct mt7915_dev *dev, int idx, int n_desc) 10e57b7901SRyder Lee { 11*b671da33SLorenzo Bianconi int i, err; 12e57b7901SRyder Lee 13*b671da33SLorenzo Bianconi err = mt76_init_tx_queue(&dev->mt76, 0, idx, n_desc, MT_TX_RING_BASE); 14e57b7901SRyder Lee if (err < 0) 15e57b7901SRyder Lee return err; 16e57b7901SRyder Lee 17f099c2e5SFelix Fietkau for (i = 0; i < MT_TXQ_MCU; i++) 18*b671da33SLorenzo Bianconi dev->mt76.q_tx[i] = dev->mt76.q_tx[0]; 19e57b7901SRyder Lee 20e57b7901SRyder Lee return 0; 21e57b7901SRyder Lee } 22e57b7901SRyder Lee 23e57b7901SRyder Lee void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 24e57b7901SRyder Lee struct sk_buff *skb) 25e57b7901SRyder Lee { 26e57b7901SRyder Lee struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 27e57b7901SRyder Lee __le32 *rxd = (__le32 *)skb->data; 28e57b7901SRyder Lee enum rx_pkt_type type; 29e57b7901SRyder Lee 30e57b7901SRyder Lee type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 31e57b7901SRyder Lee 32e57b7901SRyder Lee switch (type) { 33e57b7901SRyder Lee case PKT_TYPE_TXRX_NOTIFY: 34e57b7901SRyder Lee mt7915_mac_tx_free(dev, skb); 35e57b7901SRyder Lee break; 36e57b7901SRyder Lee case PKT_TYPE_RX_EVENT: 37e57b7901SRyder Lee mt7915_mcu_rx_event(dev, skb); 38e57b7901SRyder Lee break; 395d8a83f0SShayne Chen #ifdef CONFIG_NL80211_TESTMODE 405d8a83f0SShayne Chen case PKT_TYPE_TXRXV: 415d8a83f0SShayne Chen mt7915_mac_fill_rx_vector(dev, skb); 425d8a83f0SShayne Chen break; 435d8a83f0SShayne Chen #endif 44e57b7901SRyder Lee case PKT_TYPE_NORMAL: 45e57b7901SRyder Lee if (!mt7915_mac_fill_rx(dev, skb)) { 46e57b7901SRyder Lee mt76_rx(&dev->mt76, q, skb); 47e57b7901SRyder Lee return; 48e57b7901SRyder Lee } 49aab662ccSGustavo A. R. Silva fallthrough; 50e57b7901SRyder Lee default: 51e57b7901SRyder Lee dev_kfree_skb(skb); 52e57b7901SRyder Lee break; 53e57b7901SRyder Lee } 54e57b7901SRyder Lee } 55e57b7901SRyder Lee 56dc076af5SRyder Lee static void 57dc076af5SRyder Lee mt7915_tx_cleanup(struct mt7915_dev *dev) 58dc076af5SRyder Lee { 59dc076af5SRyder Lee mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false); 60dc076af5SRyder Lee mt76_queue_tx_cleanup(dev, MT_TXQ_MCU_WA, false); 61dc076af5SRyder Lee } 62dc076af5SRyder Lee 63e57b7901SRyder Lee static int mt7915_poll_tx(struct napi_struct *napi, int budget) 64e57b7901SRyder Lee { 65e57b7901SRyder Lee struct mt7915_dev *dev; 66e57b7901SRyder Lee 67e57b7901SRyder Lee dev = container_of(napi, struct mt7915_dev, mt76.tx_napi); 68e57b7901SRyder Lee 69dc076af5SRyder Lee mt7915_tx_cleanup(dev); 70e57b7901SRyder Lee 7138b04398SFelix Fietkau if (napi_complete_done(napi, 0)) 72f8a667a9SFelix Fietkau mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU); 7338b04398SFelix Fietkau 74e57b7901SRyder Lee return 0; 75e57b7901SRyder Lee } 76e57b7901SRyder Lee 77e57b7901SRyder Lee void mt7915_dma_prefetch(struct mt7915_dev *dev) 78e57b7901SRyder Lee { 79e57b7901SRyder Lee #define PREFETCH(base, depth) ((base) << 16 | (depth)) 80e57b7901SRyder Lee 81e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4)); 82e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x40, 0x4)); 83e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x80, 0x0)); 84e57b7901SRyder Lee 85e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL, PREFETCH(0x80, 0x4)); 86e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL, PREFETCH(0xc0, 0x4)); 87e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL, PREFETCH(0x100, 0x4)); 88e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL, PREFETCH(0x140, 0x4)); 89e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL, PREFETCH(0x180, 0x4)); 90e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL, PREFETCH(0x1c0, 0x4)); 91e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL, PREFETCH(0x200, 0x4)); 92e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL, PREFETCH(0x240, 0x4)); 93e57b7901SRyder Lee 94e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL, PREFETCH(0x280, 0x4)); 95e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL, PREFETCH(0x2c0, 0x4)); 96e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL, PREFETCH(0x300, 0x4)); 97e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL, PREFETCH(0x340, 0x4)); 98e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL, PREFETCH(0x380, 0x4)); 99e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL, PREFETCH(0x3c0, 0x0)); 100e57b7901SRyder Lee 101e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL, PREFETCH(0x3c0, 0x4)); 102e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL, PREFETCH(0x400, 0x4)); 103e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL, PREFETCH(0x440, 0x4)); 104e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL, PREFETCH(0x480, 0x0)); 105e57b7901SRyder Lee } 106e57b7901SRyder Lee 107c32011bbSFelix Fietkau static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 108c32011bbSFelix Fietkau { 109c32011bbSFelix Fietkau static const struct { 110c32011bbSFelix Fietkau u32 phys; 111c32011bbSFelix Fietkau u32 mapped; 112c32011bbSFelix Fietkau u32 size; 113c32011bbSFelix Fietkau } fixed_map[] = { 114c32011bbSFelix Fietkau { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ 115c32011bbSFelix Fietkau { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ 116c32011bbSFelix Fietkau { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 117c32011bbSFelix Fietkau { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 118c32011bbSFelix Fietkau { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 119c32011bbSFelix Fietkau { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 120c32011bbSFelix Fietkau { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 121c32011bbSFelix Fietkau { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 122c32011bbSFelix Fietkau { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 123c32011bbSFelix Fietkau { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 124c32011bbSFelix Fietkau { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */ 125c32011bbSFelix Fietkau { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 126c32011bbSFelix Fietkau { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 127c32011bbSFelix Fietkau { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 128c32011bbSFelix Fietkau { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 129c32011bbSFelix Fietkau { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 130c32011bbSFelix Fietkau { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 131c32011bbSFelix Fietkau { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 132c32011bbSFelix Fietkau { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 133c32011bbSFelix Fietkau { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 134c32011bbSFelix Fietkau { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 135c32011bbSFelix Fietkau { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 136c32011bbSFelix Fietkau { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 137c32011bbSFelix Fietkau { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 138c32011bbSFelix Fietkau { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 139c32011bbSFelix Fietkau { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 140c32011bbSFelix Fietkau { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 141c32011bbSFelix Fietkau { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 142c32011bbSFelix Fietkau { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 143c32011bbSFelix Fietkau { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 144c32011bbSFelix Fietkau { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 145c32011bbSFelix Fietkau { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 146c32011bbSFelix Fietkau { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 147c32011bbSFelix Fietkau { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 148c32011bbSFelix Fietkau { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 149c32011bbSFelix Fietkau { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 150c32011bbSFelix Fietkau { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 151c32011bbSFelix Fietkau { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 152c32011bbSFelix Fietkau }; 153c32011bbSFelix Fietkau int i; 154c32011bbSFelix Fietkau 155c32011bbSFelix Fietkau if (addr < 0x100000) 156c32011bbSFelix Fietkau return addr; 157c32011bbSFelix Fietkau 158c32011bbSFelix Fietkau for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 159c32011bbSFelix Fietkau u32 ofs; 160c32011bbSFelix Fietkau 161c32011bbSFelix Fietkau if (addr < fixed_map[i].phys) 162c32011bbSFelix Fietkau continue; 163c32011bbSFelix Fietkau 164c32011bbSFelix Fietkau ofs = addr - fixed_map[i].phys; 165c32011bbSFelix Fietkau if (ofs > fixed_map[i].size) 166c32011bbSFelix Fietkau continue; 167c32011bbSFelix Fietkau 168c32011bbSFelix Fietkau return fixed_map[i].mapped + ofs; 169c32011bbSFelix Fietkau } 170c32011bbSFelix Fietkau 171c32011bbSFelix Fietkau if ((addr >= 0x18000000 && addr < 0x18c00000) || 172c32011bbSFelix Fietkau (addr >= 0x70000000 && addr < 0x78000000) || 173c32011bbSFelix Fietkau (addr >= 0x7c000000 && addr < 0x7c400000)) 174c32011bbSFelix Fietkau return mt7915_reg_map_l1(dev, addr); 175c32011bbSFelix Fietkau 176c32011bbSFelix Fietkau return mt7915_reg_map_l2(dev, addr); 177c32011bbSFelix Fietkau } 178c32011bbSFelix Fietkau 179c32011bbSFelix Fietkau static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 180c32011bbSFelix Fietkau { 181c32011bbSFelix Fietkau struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 182c32011bbSFelix Fietkau u32 addr = __mt7915_reg_addr(dev, offset); 183c32011bbSFelix Fietkau 184c32011bbSFelix Fietkau return dev->bus_ops->rr(mdev, addr); 185c32011bbSFelix Fietkau } 186c32011bbSFelix Fietkau 187c32011bbSFelix Fietkau static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 188c32011bbSFelix Fietkau { 189c32011bbSFelix Fietkau struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 190c32011bbSFelix Fietkau u32 addr = __mt7915_reg_addr(dev, offset); 191c32011bbSFelix Fietkau 192c32011bbSFelix Fietkau dev->bus_ops->wr(mdev, addr, val); 193c32011bbSFelix Fietkau } 194c32011bbSFelix Fietkau 195c32011bbSFelix Fietkau static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 196c32011bbSFelix Fietkau { 197c32011bbSFelix Fietkau struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 198c32011bbSFelix Fietkau u32 addr = __mt7915_reg_addr(dev, offset); 199c32011bbSFelix Fietkau 200c32011bbSFelix Fietkau return dev->bus_ops->rmw(mdev, addr, mask, val); 201c32011bbSFelix Fietkau } 202c32011bbSFelix Fietkau 203e57b7901SRyder Lee int mt7915_dma_init(struct mt7915_dev *dev) 204e57b7901SRyder Lee { 205e57b7901SRyder Lee /* Increase buffer size to receive large VHT/HE MPDUs */ 206c32011bbSFelix Fietkau struct mt76_bus_ops *bus_ops; 207e57b7901SRyder Lee int rx_buf_size = MT_RX_BUF_SIZE * 2; 208e57b7901SRyder Lee int ret; 209e57b7901SRyder Lee 210c32011bbSFelix Fietkau dev->bus_ops = dev->mt76.bus; 211c32011bbSFelix Fietkau bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 212c32011bbSFelix Fietkau GFP_KERNEL); 213c32011bbSFelix Fietkau if (!bus_ops) 214c32011bbSFelix Fietkau return -ENOMEM; 215c32011bbSFelix Fietkau 216c32011bbSFelix Fietkau bus_ops->rr = mt7915_rr; 217c32011bbSFelix Fietkau bus_ops->wr = mt7915_wr; 218c32011bbSFelix Fietkau bus_ops->rmw = mt7915_rmw; 219c32011bbSFelix Fietkau dev->mt76.bus = bus_ops; 220c32011bbSFelix Fietkau 221e57b7901SRyder Lee mt76_dma_attach(&dev->mt76); 222e57b7901SRyder Lee 223e57b7901SRyder Lee /* configure global setting */ 224e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_GLO_CFG, 225e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 226e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 227e57b7901SRyder Lee 228e57b7901SRyder Lee /* configure perfetch settings */ 229e57b7901SRyder Lee mt7915_dma_prefetch(dev); 230e57b7901SRyder Lee 231e57b7901SRyder Lee /* reset dma idx */ 232e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); 233e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0); 234e57b7901SRyder Lee 235e57b7901SRyder Lee /* configure delay interrupt */ 236e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); 237e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0); 238e57b7901SRyder Lee 239e57b7901SRyder Lee /* init tx queue */ 240*b671da33SLorenzo Bianconi ret = mt7915_init_tx_queues(dev, MT7915_TXQ_BAND0, 241*b671da33SLorenzo Bianconi MT7915_TX_RING_SIZE); 242e57b7901SRyder Lee if (ret) 243e57b7901SRyder Lee return ret; 244e57b7901SRyder Lee 245e57b7901SRyder Lee /* command to WM */ 246*b671da33SLorenzo Bianconi ret = mt76_init_tx_queue(&dev->mt76, MT_TXQ_MCU, MT7915_TXQ_MCU_WM, 247*b671da33SLorenzo Bianconi MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 248e57b7901SRyder Lee if (ret) 249e57b7901SRyder Lee return ret; 250e57b7901SRyder Lee 251e57b7901SRyder Lee /* command to WA */ 252*b671da33SLorenzo Bianconi ret = mt76_init_tx_queue(&dev->mt76, MT_TXQ_MCU_WA, MT7915_TXQ_MCU_WA, 253*b671da33SLorenzo Bianconi MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 254e57b7901SRyder Lee if (ret) 255e57b7901SRyder Lee return ret; 256e57b7901SRyder Lee 257e57b7901SRyder Lee /* firmware download */ 258*b671da33SLorenzo Bianconi ret = mt76_init_tx_queue(&dev->mt76, MT_TXQ_FWDL, MT7915_TXQ_FWDL, 259*b671da33SLorenzo Bianconi MT7915_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 260e57b7901SRyder Lee if (ret) 261e57b7901SRyder Lee return ret; 262e57b7901SRyder Lee 263e57b7901SRyder Lee /* event from WM */ 264e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 265e57b7901SRyder Lee MT7915_RXQ_MCU_WM, MT7915_RX_MCU_RING_SIZE, 266e57b7901SRyder Lee rx_buf_size, MT_RX_EVENT_RING_BASE); 267e57b7901SRyder Lee if (ret) 268e57b7901SRyder Lee return ret; 269e57b7901SRyder Lee 270e57b7901SRyder Lee /* event from WA */ 271e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 272e57b7901SRyder Lee MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE, 273e57b7901SRyder Lee rx_buf_size, MT_RX_EVENT_RING_BASE); 274e57b7901SRyder Lee if (ret) 275e57b7901SRyder Lee return ret; 276e57b7901SRyder Lee 277e57b7901SRyder Lee /* rx data */ 278e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 279e57b7901SRyder Lee MT7915_RX_RING_SIZE, rx_buf_size, 280e57b7901SRyder Lee MT_RX_DATA_RING_BASE); 281e57b7901SRyder Lee if (ret) 282e57b7901SRyder Lee return ret; 283e57b7901SRyder Lee 284e57b7901SRyder Lee ret = mt76_init_queues(dev); 285e57b7901SRyder Lee if (ret < 0) 286e57b7901SRyder Lee return ret; 287e57b7901SRyder Lee 288e57b7901SRyder Lee netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 289e57b7901SRyder Lee mt7915_poll_tx, NAPI_POLL_WEIGHT); 290e57b7901SRyder Lee napi_enable(&dev->mt76.tx_napi); 291e57b7901SRyder Lee 292e57b7901SRyder Lee /* hif wait WFDMA idle */ 293e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_BUSY_ENA, 294e57b7901SRyder Lee MT_WFDMA0_BUSY_ENA_TX_FIFO0 | 295e57b7901SRyder Lee MT_WFDMA0_BUSY_ENA_TX_FIFO1 | 296e57b7901SRyder Lee MT_WFDMA0_BUSY_ENA_RX_FIFO); 297e57b7901SRyder Lee 298e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_BUSY_ENA, 299e57b7901SRyder Lee MT_WFDMA1_BUSY_ENA_TX_FIFO0 | 300e57b7901SRyder Lee MT_WFDMA1_BUSY_ENA_TX_FIFO1 | 301e57b7901SRyder Lee MT_WFDMA1_BUSY_ENA_RX_FIFO); 302e57b7901SRyder Lee 303e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA, 304e57b7901SRyder Lee MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | 305e57b7901SRyder Lee MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | 306e57b7901SRyder Lee MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); 307e57b7901SRyder Lee 308e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA, 309e57b7901SRyder Lee MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 | 310e57b7901SRyder Lee MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 | 311e57b7901SRyder Lee MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO); 312e57b7901SRyder Lee 313e57b7901SRyder Lee mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, 314e57b7901SRyder Lee MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); 315e57b7901SRyder Lee 316e57b7901SRyder Lee /* set WFDMA Tx/Rx */ 317e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_GLO_CFG, 318e57b7901SRyder Lee MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 319e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_GLO_CFG, 320e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 321e57b7901SRyder Lee 322e57b7901SRyder Lee /* enable interrupts for TX/RX rings */ 323f8a667a9SFelix Fietkau mt7915_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_MCU | 324e57b7901SRyder Lee MT_INT_MCU_CMD); 325e57b7901SRyder Lee 326e57b7901SRyder Lee return 0; 327e57b7901SRyder Lee } 328e57b7901SRyder Lee 329e57b7901SRyder Lee void mt7915_dma_cleanup(struct mt7915_dev *dev) 330e57b7901SRyder Lee { 331e57b7901SRyder Lee /* disable */ 332e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA0_GLO_CFG, 333e57b7901SRyder Lee MT_WFDMA0_GLO_CFG_TX_DMA_EN | 334e57b7901SRyder Lee MT_WFDMA0_GLO_CFG_RX_DMA_EN); 335e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA1_GLO_CFG, 336e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_TX_DMA_EN | 337e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_RX_DMA_EN); 338e57b7901SRyder Lee 339e57b7901SRyder Lee /* reset */ 340e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA1_RST, 341e57b7901SRyder Lee MT_WFDMA1_RST_DMASHDL_ALL_RST | 342e57b7901SRyder Lee MT_WFDMA1_RST_LOGIC_RST); 343e57b7901SRyder Lee 344e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_RST, 345e57b7901SRyder Lee MT_WFDMA1_RST_DMASHDL_ALL_RST | 346e57b7901SRyder Lee MT_WFDMA1_RST_LOGIC_RST); 347e57b7901SRyder Lee 348e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA0_RST, 349e57b7901SRyder Lee MT_WFDMA0_RST_DMASHDL_ALL_RST | 350e57b7901SRyder Lee MT_WFDMA0_RST_LOGIC_RST); 351e57b7901SRyder Lee 352e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_RST, 353e57b7901SRyder Lee MT_WFDMA0_RST_DMASHDL_ALL_RST | 354e57b7901SRyder Lee MT_WFDMA0_RST_LOGIC_RST); 355e57b7901SRyder Lee 356e57b7901SRyder Lee mt76_dma_cleanup(&dev->mt76); 357e57b7901SRyder Lee } 358