1e57b7901SRyder Lee // SPDX-License-Identifier: ISC 2e57b7901SRyder Lee /* Copyright (C) 2020 MediaTek Inc. */ 3e57b7901SRyder Lee 4e57b7901SRyder Lee #include "mt7915.h" 5e57b7901SRyder Lee #include "../dma.h" 6e57b7901SRyder Lee #include "mac.h" 7e57b7901SRyder Lee 8e57b7901SRyder Lee static int 9e57b7901SRyder Lee mt7915_init_tx_queues(struct mt7915_dev *dev, int n_desc) 10e57b7901SRyder Lee { 11e57b7901SRyder Lee struct mt76_queue *hwq; 12e57b7901SRyder Lee int err, i; 13e57b7901SRyder Lee 14e57b7901SRyder Lee hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL); 15e57b7901SRyder Lee if (!hwq) 16e57b7901SRyder Lee return -ENOMEM; 17e57b7901SRyder Lee 18e57b7901SRyder Lee err = mt76_queue_alloc(dev, hwq, MT7915_TXQ_BAND0, n_desc, 0, 19e57b7901SRyder Lee MT_TX_RING_BASE); 20e57b7901SRyder Lee if (err < 0) 21e57b7901SRyder Lee return err; 22e57b7901SRyder Lee 23f099c2e5SFelix Fietkau for (i = 0; i < MT_TXQ_MCU; i++) 24f099c2e5SFelix Fietkau dev->mt76.q_tx[i] = hwq; 25e57b7901SRyder Lee 26e57b7901SRyder Lee return 0; 27e57b7901SRyder Lee } 28e57b7901SRyder Lee 29e57b7901SRyder Lee static int 30f099c2e5SFelix Fietkau mt7915_init_mcu_queue(struct mt7915_dev *dev, int qid, int idx, int n_desc) 31e57b7901SRyder Lee { 32e57b7901SRyder Lee struct mt76_queue *hwq; 33e57b7901SRyder Lee int err; 34e57b7901SRyder Lee 35e57b7901SRyder Lee hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL); 36e57b7901SRyder Lee if (!hwq) 37e57b7901SRyder Lee return -ENOMEM; 38e57b7901SRyder Lee 39e57b7901SRyder Lee err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE); 40e57b7901SRyder Lee if (err < 0) 41e57b7901SRyder Lee return err; 42e57b7901SRyder Lee 43f099c2e5SFelix Fietkau dev->mt76.q_tx[qid] = hwq; 44e57b7901SRyder Lee 45e57b7901SRyder Lee return 0; 46e57b7901SRyder Lee } 47e57b7901SRyder Lee 48e57b7901SRyder Lee void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 49e57b7901SRyder Lee struct sk_buff *skb) 50e57b7901SRyder Lee { 51e57b7901SRyder Lee struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 52e57b7901SRyder Lee __le32 *rxd = (__le32 *)skb->data; 53e57b7901SRyder Lee enum rx_pkt_type type; 54e57b7901SRyder Lee 55e57b7901SRyder Lee type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 56e57b7901SRyder Lee 57e57b7901SRyder Lee switch (type) { 58e57b7901SRyder Lee case PKT_TYPE_TXRX_NOTIFY: 59e57b7901SRyder Lee mt7915_mac_tx_free(dev, skb); 60e57b7901SRyder Lee break; 61e57b7901SRyder Lee case PKT_TYPE_RX_EVENT: 62e57b7901SRyder Lee mt7915_mcu_rx_event(dev, skb); 63e57b7901SRyder Lee break; 64e57b7901SRyder Lee case PKT_TYPE_NORMAL: 65e57b7901SRyder Lee if (!mt7915_mac_fill_rx(dev, skb)) { 66e57b7901SRyder Lee mt76_rx(&dev->mt76, q, skb); 67e57b7901SRyder Lee return; 68e57b7901SRyder Lee } 69aab662ccSGustavo A. R. Silva fallthrough; 70e57b7901SRyder Lee default: 71e57b7901SRyder Lee dev_kfree_skb(skb); 72e57b7901SRyder Lee break; 73e57b7901SRyder Lee } 74e57b7901SRyder Lee } 75e57b7901SRyder Lee 76dc076af5SRyder Lee static void 77dc076af5SRyder Lee mt7915_tx_cleanup(struct mt7915_dev *dev) 78dc076af5SRyder Lee { 79dc076af5SRyder Lee mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false); 80dc076af5SRyder Lee mt76_queue_tx_cleanup(dev, MT_TXQ_MCU_WA, false); 81dc076af5SRyder Lee } 82dc076af5SRyder Lee 83e57b7901SRyder Lee static int mt7915_poll_tx(struct napi_struct *napi, int budget) 84e57b7901SRyder Lee { 85e57b7901SRyder Lee struct mt7915_dev *dev; 86e57b7901SRyder Lee 87e57b7901SRyder Lee dev = container_of(napi, struct mt7915_dev, mt76.tx_napi); 88e57b7901SRyder Lee 89dc076af5SRyder Lee mt7915_tx_cleanup(dev); 90e57b7901SRyder Lee 9138b04398SFelix Fietkau if (napi_complete_done(napi, 0)) 92f8a667a9SFelix Fietkau mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU); 9338b04398SFelix Fietkau 94e57b7901SRyder Lee return 0; 95e57b7901SRyder Lee } 96e57b7901SRyder Lee 97e57b7901SRyder Lee void mt7915_dma_prefetch(struct mt7915_dev *dev) 98e57b7901SRyder Lee { 99e57b7901SRyder Lee #define PREFETCH(base, depth) ((base) << 16 | (depth)) 100e57b7901SRyder Lee 101e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4)); 102e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x40, 0x4)); 103e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x80, 0x0)); 104e57b7901SRyder Lee 105e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL, PREFETCH(0x80, 0x4)); 106e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL, PREFETCH(0xc0, 0x4)); 107e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL, PREFETCH(0x100, 0x4)); 108e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL, PREFETCH(0x140, 0x4)); 109e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL, PREFETCH(0x180, 0x4)); 110e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL, PREFETCH(0x1c0, 0x4)); 111e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL, PREFETCH(0x200, 0x4)); 112e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL, PREFETCH(0x240, 0x4)); 113e57b7901SRyder Lee 114e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL, PREFETCH(0x280, 0x4)); 115e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL, PREFETCH(0x2c0, 0x4)); 116e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL, PREFETCH(0x300, 0x4)); 117e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL, PREFETCH(0x340, 0x4)); 118e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL, PREFETCH(0x380, 0x4)); 119e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL, PREFETCH(0x3c0, 0x0)); 120e57b7901SRyder Lee 121e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL, PREFETCH(0x3c0, 0x4)); 122e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL, PREFETCH(0x400, 0x4)); 123e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL, PREFETCH(0x440, 0x4)); 124e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL, PREFETCH(0x480, 0x0)); 125e57b7901SRyder Lee } 126e57b7901SRyder Lee 127c32011bbSFelix Fietkau static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 128c32011bbSFelix Fietkau { 129c32011bbSFelix Fietkau static const struct { 130c32011bbSFelix Fietkau u32 phys; 131c32011bbSFelix Fietkau u32 mapped; 132c32011bbSFelix Fietkau u32 size; 133c32011bbSFelix Fietkau } fixed_map[] = { 134c32011bbSFelix Fietkau { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */ 135c32011bbSFelix Fietkau { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */ 136c32011bbSFelix Fietkau { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 137c32011bbSFelix Fietkau { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 138c32011bbSFelix Fietkau { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 139c32011bbSFelix Fietkau { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 140c32011bbSFelix Fietkau { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 141c32011bbSFelix Fietkau { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 142c32011bbSFelix Fietkau { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 143c32011bbSFelix Fietkau { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 144c32011bbSFelix Fietkau { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */ 145c32011bbSFelix Fietkau { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 146c32011bbSFelix Fietkau { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 147c32011bbSFelix Fietkau { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 148c32011bbSFelix Fietkau { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 149c32011bbSFelix Fietkau { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 150c32011bbSFelix Fietkau { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 151c32011bbSFelix Fietkau { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 152c32011bbSFelix Fietkau { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 153c32011bbSFelix Fietkau { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 154c32011bbSFelix Fietkau { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 155c32011bbSFelix Fietkau { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 156c32011bbSFelix Fietkau { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 157c32011bbSFelix Fietkau { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 158c32011bbSFelix Fietkau { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 159c32011bbSFelix Fietkau { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 160c32011bbSFelix Fietkau { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 161c32011bbSFelix Fietkau { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 162c32011bbSFelix Fietkau { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 163c32011bbSFelix Fietkau { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 164c32011bbSFelix Fietkau { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 165c32011bbSFelix Fietkau { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 166c32011bbSFelix Fietkau { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 167c32011bbSFelix Fietkau { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 168c32011bbSFelix Fietkau { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 169c32011bbSFelix Fietkau { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 170c32011bbSFelix Fietkau { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 171c32011bbSFelix Fietkau { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 172c32011bbSFelix Fietkau }; 173c32011bbSFelix Fietkau int i; 174c32011bbSFelix Fietkau 175c32011bbSFelix Fietkau if (addr < 0x100000) 176c32011bbSFelix Fietkau return addr; 177c32011bbSFelix Fietkau 178c32011bbSFelix Fietkau for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 179c32011bbSFelix Fietkau u32 ofs; 180c32011bbSFelix Fietkau 181c32011bbSFelix Fietkau if (addr < fixed_map[i].phys) 182c32011bbSFelix Fietkau continue; 183c32011bbSFelix Fietkau 184c32011bbSFelix Fietkau ofs = addr - fixed_map[i].phys; 185c32011bbSFelix Fietkau if (ofs > fixed_map[i].size) 186c32011bbSFelix Fietkau continue; 187c32011bbSFelix Fietkau 188c32011bbSFelix Fietkau return fixed_map[i].mapped + ofs; 189c32011bbSFelix Fietkau } 190c32011bbSFelix Fietkau 191c32011bbSFelix Fietkau if ((addr >= 0x18000000 && addr < 0x18c00000) || 192c32011bbSFelix Fietkau (addr >= 0x70000000 && addr < 0x78000000) || 193c32011bbSFelix Fietkau (addr >= 0x7c000000 && addr < 0x7c400000)) 194c32011bbSFelix Fietkau return mt7915_reg_map_l1(dev, addr); 195c32011bbSFelix Fietkau 196c32011bbSFelix Fietkau return mt7915_reg_map_l2(dev, addr); 197c32011bbSFelix Fietkau } 198c32011bbSFelix Fietkau 199c32011bbSFelix Fietkau static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 200c32011bbSFelix Fietkau { 201c32011bbSFelix Fietkau struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 202c32011bbSFelix Fietkau u32 addr = __mt7915_reg_addr(dev, offset); 203c32011bbSFelix Fietkau 204c32011bbSFelix Fietkau return dev->bus_ops->rr(mdev, addr); 205c32011bbSFelix Fietkau } 206c32011bbSFelix Fietkau 207c32011bbSFelix Fietkau static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 208c32011bbSFelix Fietkau { 209c32011bbSFelix Fietkau struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 210c32011bbSFelix Fietkau u32 addr = __mt7915_reg_addr(dev, offset); 211c32011bbSFelix Fietkau 212c32011bbSFelix Fietkau dev->bus_ops->wr(mdev, addr, val); 213c32011bbSFelix Fietkau } 214c32011bbSFelix Fietkau 215c32011bbSFelix Fietkau static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 216c32011bbSFelix Fietkau { 217c32011bbSFelix Fietkau struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 218c32011bbSFelix Fietkau u32 addr = __mt7915_reg_addr(dev, offset); 219c32011bbSFelix Fietkau 220c32011bbSFelix Fietkau return dev->bus_ops->rmw(mdev, addr, mask, val); 221c32011bbSFelix Fietkau } 222c32011bbSFelix Fietkau 223e57b7901SRyder Lee int mt7915_dma_init(struct mt7915_dev *dev) 224e57b7901SRyder Lee { 225e57b7901SRyder Lee /* Increase buffer size to receive large VHT/HE MPDUs */ 226c32011bbSFelix Fietkau struct mt76_bus_ops *bus_ops; 227e57b7901SRyder Lee int rx_buf_size = MT_RX_BUF_SIZE * 2; 228e57b7901SRyder Lee int ret; 229e57b7901SRyder Lee 230c32011bbSFelix Fietkau dev->bus_ops = dev->mt76.bus; 231c32011bbSFelix Fietkau bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 232c32011bbSFelix Fietkau GFP_KERNEL); 233c32011bbSFelix Fietkau if (!bus_ops) 234c32011bbSFelix Fietkau return -ENOMEM; 235c32011bbSFelix Fietkau 236c32011bbSFelix Fietkau bus_ops->rr = mt7915_rr; 237c32011bbSFelix Fietkau bus_ops->wr = mt7915_wr; 238c32011bbSFelix Fietkau bus_ops->rmw = mt7915_rmw; 239c32011bbSFelix Fietkau dev->mt76.bus = bus_ops; 240c32011bbSFelix Fietkau 241e57b7901SRyder Lee mt76_dma_attach(&dev->mt76); 242e57b7901SRyder Lee 243e57b7901SRyder Lee /* configure global setting */ 244e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_GLO_CFG, 245e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 246e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 247e57b7901SRyder Lee 248e57b7901SRyder Lee /* configure perfetch settings */ 249e57b7901SRyder Lee mt7915_dma_prefetch(dev); 250e57b7901SRyder Lee 251e57b7901SRyder Lee /* reset dma idx */ 252e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); 253e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0); 254e57b7901SRyder Lee 255e57b7901SRyder Lee /* configure delay interrupt */ 256e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); 257e57b7901SRyder Lee mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0); 258e57b7901SRyder Lee 259e57b7901SRyder Lee /* init tx queue */ 260e57b7901SRyder Lee ret = mt7915_init_tx_queues(dev, MT7915_TX_RING_SIZE); 261e57b7901SRyder Lee if (ret) 262e57b7901SRyder Lee return ret; 263e57b7901SRyder Lee 264e57b7901SRyder Lee /* command to WM */ 265f099c2e5SFelix Fietkau ret = mt7915_init_mcu_queue(dev, MT_TXQ_MCU, MT7915_TXQ_MCU_WM, 266e57b7901SRyder Lee MT7915_TX_MCU_RING_SIZE); 267e57b7901SRyder Lee if (ret) 268e57b7901SRyder Lee return ret; 269e57b7901SRyder Lee 270e57b7901SRyder Lee /* command to WA */ 271f099c2e5SFelix Fietkau ret = mt7915_init_mcu_queue(dev, MT_TXQ_MCU_WA, MT7915_TXQ_MCU_WA, 272e57b7901SRyder Lee MT7915_TX_MCU_RING_SIZE); 273e57b7901SRyder Lee if (ret) 274e57b7901SRyder Lee return ret; 275e57b7901SRyder Lee 276e57b7901SRyder Lee /* firmware download */ 277f099c2e5SFelix Fietkau ret = mt7915_init_mcu_queue(dev, MT_TXQ_FWDL, MT7915_TXQ_FWDL, 278e57b7901SRyder Lee MT7915_TX_FWDL_RING_SIZE); 279e57b7901SRyder Lee if (ret) 280e57b7901SRyder Lee return ret; 281e57b7901SRyder Lee 282e57b7901SRyder Lee /* event from WM */ 283e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 284e57b7901SRyder Lee MT7915_RXQ_MCU_WM, MT7915_RX_MCU_RING_SIZE, 285e57b7901SRyder Lee rx_buf_size, MT_RX_EVENT_RING_BASE); 286e57b7901SRyder Lee if (ret) 287e57b7901SRyder Lee return ret; 288e57b7901SRyder Lee 289e57b7901SRyder Lee /* event from WA */ 290e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 291e57b7901SRyder Lee MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE, 292e57b7901SRyder Lee rx_buf_size, MT_RX_EVENT_RING_BASE); 293e57b7901SRyder Lee if (ret) 294e57b7901SRyder Lee return ret; 295e57b7901SRyder Lee 296e57b7901SRyder Lee /* rx data */ 297e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 298e57b7901SRyder Lee MT7915_RX_RING_SIZE, rx_buf_size, 299e57b7901SRyder Lee MT_RX_DATA_RING_BASE); 300e57b7901SRyder Lee if (ret) 301e57b7901SRyder Lee return ret; 302e57b7901SRyder Lee 303e57b7901SRyder Lee ret = mt76_init_queues(dev); 304e57b7901SRyder Lee if (ret < 0) 305e57b7901SRyder Lee return ret; 306e57b7901SRyder Lee 307e57b7901SRyder Lee netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 308e57b7901SRyder Lee mt7915_poll_tx, NAPI_POLL_WEIGHT); 309e57b7901SRyder Lee napi_enable(&dev->mt76.tx_napi); 310e57b7901SRyder Lee 311e57b7901SRyder Lee /* hif wait WFDMA idle */ 312e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_BUSY_ENA, 313e57b7901SRyder Lee MT_WFDMA0_BUSY_ENA_TX_FIFO0 | 314e57b7901SRyder Lee MT_WFDMA0_BUSY_ENA_TX_FIFO1 | 315e57b7901SRyder Lee MT_WFDMA0_BUSY_ENA_RX_FIFO); 316e57b7901SRyder Lee 317e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_BUSY_ENA, 318e57b7901SRyder Lee MT_WFDMA1_BUSY_ENA_TX_FIFO0 | 319e57b7901SRyder Lee MT_WFDMA1_BUSY_ENA_TX_FIFO1 | 320e57b7901SRyder Lee MT_WFDMA1_BUSY_ENA_RX_FIFO); 321e57b7901SRyder Lee 322e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_PCIE1_BUSY_ENA, 323e57b7901SRyder Lee MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | 324e57b7901SRyder Lee MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | 325e57b7901SRyder Lee MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); 326e57b7901SRyder Lee 327e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_PCIE1_BUSY_ENA, 328e57b7901SRyder Lee MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 | 329e57b7901SRyder Lee MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 | 330e57b7901SRyder Lee MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO); 331e57b7901SRyder Lee 332e57b7901SRyder Lee mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, 333e57b7901SRyder Lee MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); 334e57b7901SRyder Lee 335e57b7901SRyder Lee /* set WFDMA Tx/Rx */ 336e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_GLO_CFG, 337e57b7901SRyder Lee MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 338e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_GLO_CFG, 339e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN); 340e57b7901SRyder Lee 341e57b7901SRyder Lee /* enable interrupts for TX/RX rings */ 342f8a667a9SFelix Fietkau mt7915_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_MCU | 343e57b7901SRyder Lee MT_INT_MCU_CMD); 344e57b7901SRyder Lee 345e57b7901SRyder Lee return 0; 346e57b7901SRyder Lee } 347e57b7901SRyder Lee 348e57b7901SRyder Lee void mt7915_dma_cleanup(struct mt7915_dev *dev) 349e57b7901SRyder Lee { 350e57b7901SRyder Lee /* disable */ 351e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA0_GLO_CFG, 352e57b7901SRyder Lee MT_WFDMA0_GLO_CFG_TX_DMA_EN | 353e57b7901SRyder Lee MT_WFDMA0_GLO_CFG_RX_DMA_EN); 354e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA1_GLO_CFG, 355e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_TX_DMA_EN | 356e57b7901SRyder Lee MT_WFDMA1_GLO_CFG_RX_DMA_EN); 357e57b7901SRyder Lee 358e57b7901SRyder Lee /* reset */ 359e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA1_RST, 360e57b7901SRyder Lee MT_WFDMA1_RST_DMASHDL_ALL_RST | 361e57b7901SRyder Lee MT_WFDMA1_RST_LOGIC_RST); 362e57b7901SRyder Lee 363e57b7901SRyder Lee mt76_set(dev, MT_WFDMA1_RST, 364e57b7901SRyder Lee MT_WFDMA1_RST_DMASHDL_ALL_RST | 365e57b7901SRyder Lee MT_WFDMA1_RST_LOGIC_RST); 366e57b7901SRyder Lee 367e57b7901SRyder Lee mt76_clear(dev, MT_WFDMA0_RST, 368e57b7901SRyder Lee MT_WFDMA0_RST_DMASHDL_ALL_RST | 369e57b7901SRyder Lee MT_WFDMA0_RST_LOGIC_RST); 370e57b7901SRyder Lee 371e57b7901SRyder Lee mt76_set(dev, MT_WFDMA0_RST, 372e57b7901SRyder Lee MT_WFDMA0_RST_DMASHDL_ALL_RST | 373e57b7901SRyder Lee MT_WFDMA0_RST_LOGIC_RST); 374e57b7901SRyder Lee 375e57b7901SRyder Lee mt76_dma_cleanup(&dev->mt76); 376e57b7901SRyder Lee } 377