1e57b7901SRyder Lee // SPDX-License-Identifier: ISC 2e57b7901SRyder Lee /* Copyright (C) 2020 MediaTek Inc. */ 3e57b7901SRyder Lee 4e57b7901SRyder Lee #include "mt7915.h" 5e57b7901SRyder Lee #include "../dma.h" 6e57b7901SRyder Lee #include "mac.h" 7e57b7901SRyder Lee 8cd4c314aSBo Jiao int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base) 9e57b7901SRyder Lee { 10b671da33SLorenzo Bianconi int i, err; 11e57b7901SRyder Lee 12cd4c314aSBo Jiao err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, ring_base); 13e57b7901SRyder Lee if (err < 0) 14e57b7901SRyder Lee return err; 15e57b7901SRyder Lee 16e637763bSLorenzo Bianconi for (i = 0; i <= MT_TXQ_PSD; i++) 1791990519SLorenzo Bianconi phy->mt76->q_tx[i] = phy->mt76->q_tx[0]; 18e57b7901SRyder Lee 19e57b7901SRyder Lee return 0; 20e57b7901SRyder Lee } 21e57b7901SRyder Lee 22dc076af5SRyder Lee static void 23dc076af5SRyder Lee mt7915_tx_cleanup(struct mt7915_dev *dev) 24dc076af5SRyder Lee { 25e637763bSLorenzo Bianconi mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); 26e637763bSLorenzo Bianconi mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], false); 27dc076af5SRyder Lee } 28dc076af5SRyder Lee 29e57b7901SRyder Lee static int mt7915_poll_tx(struct napi_struct *napi, int budget) 30e57b7901SRyder Lee { 31e57b7901SRyder Lee struct mt7915_dev *dev; 32e57b7901SRyder Lee 33e57b7901SRyder Lee dev = container_of(napi, struct mt7915_dev, mt76.tx_napi); 34e57b7901SRyder Lee 35dc076af5SRyder Lee mt7915_tx_cleanup(dev); 36e57b7901SRyder Lee 3738b04398SFelix Fietkau if (napi_complete_done(napi, 0)) 38f8a667a9SFelix Fietkau mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU); 3938b04398SFelix Fietkau 40e57b7901SRyder Lee return 0; 41e57b7901SRyder Lee } 42e57b7901SRyder Lee 43cd4c314aSBo Jiao static void mt7915_dma_config(struct mt7915_dev *dev) 44cd4c314aSBo Jiao { 45cd4c314aSBo Jiao #define Q_CONFIG(q, wfdma, int, id) do { \ 46cd4c314aSBo Jiao if (wfdma) \ 47cd4c314aSBo Jiao dev->wfdma_mask |= (1 << (q)); \ 48cd4c314aSBo Jiao dev->q_int_mask[(q)] = int; \ 49cd4c314aSBo Jiao dev->q_id[(q)] = id; \ 50cd4c314aSBo Jiao } while (0) 51cd4c314aSBo Jiao 52cd4c314aSBo Jiao #define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id)) 53cd4c314aSBo Jiao #define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id)) 54cd4c314aSBo Jiao #define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id)) 55cd4c314aSBo Jiao 56cd4c314aSBo Jiao if (is_mt7915(&dev->mt76)) { 57cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7915_RXQ_BAND0); 58cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_MCU, WFDMA1, MT_INT_RX_DONE_WM, MT7915_RXQ_MCU_WM); 59cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA1, MT_INT_RX_DONE_WA, MT7915_RXQ_MCU_WA); 60cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_EXT, WFDMA0, MT_INT_RX_DONE_BAND1, MT7915_RXQ_BAND1); 61cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_EXT_WA, WFDMA1, MT_INT_RX_DONE_WA_EXT, MT7915_RXQ_MCU_WA_EXT); 62*aa79fe87SBo Jiao RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA1, MT_INT_RX_DONE_WA_MAIN, MT7915_RXQ_MCU_WA); 63cd4c314aSBo Jiao TXQ_CONFIG(0, WFDMA1, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0); 64cd4c314aSBo Jiao TXQ_CONFIG(1, WFDMA1, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1); 65cd4c314aSBo Jiao MCUQ_CONFIG(MT_MCUQ_WM, WFDMA1, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM); 66cd4c314aSBo Jiao MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, MT7915_TXQ_MCU_WA); 67cd4c314aSBo Jiao MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL); 68cd4c314aSBo Jiao } else { 69cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0); 70cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7916_RXQ_MCU_WM); 71cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA); 72cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_EXT, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1); 73cd4c314aSBo Jiao RXQ_CONFIG(MT_RXQ_EXT_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, MT7916_RXQ_MCU_WA_EXT); 74*aa79fe87SBo Jiao RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN); 75cd4c314aSBo Jiao TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0); 76cd4c314aSBo Jiao TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1); 77cd4c314aSBo Jiao MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM); 78cd4c314aSBo Jiao MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, MT7915_TXQ_MCU_WA); 79cd4c314aSBo Jiao MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL); 80cd4c314aSBo Jiao } 81cd4c314aSBo Jiao } 82cd4c314aSBo Jiao 839093cfffSFelix Fietkau static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs) 84e57b7901SRyder Lee { 85cd4c314aSBo Jiao #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) 86*aa79fe87SBo Jiao u32 base = 0; 87e57b7901SRyder Lee 88cd4c314aSBo Jiao /* prefetch SRAM wrapping boundary for tx/rx ring. */ 89cd4c314aSBo Jiao mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x4)); 90cd4c314aSBo Jiao mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x40, 0x4)); 91cd4c314aSBo Jiao mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x80, 0x4)); 92cd4c314aSBo Jiao mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0xc0, 0x4)); 93cd4c314aSBo Jiao mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x100, 0x4)); 94e57b7901SRyder Lee 95cd4c314aSBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x140, 0x4)); 96cd4c314aSBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x180, 0x4)); 97*aa79fe87SBo Jiao if (!is_mt7915(&dev->mt76)) { 98*aa79fe87SBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x1c0, 0x4)); 99*aa79fe87SBo Jiao base = 0x40; 100*aa79fe87SBo Jiao } 101*aa79fe87SBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT_WA) + ofs, PREFETCH(0x1c0 + base, 0x4)); 102*aa79fe87SBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x200 + base, 0x4)); 103*aa79fe87SBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT) + ofs, PREFETCH(0x240 + base, 0x4)); 104e57b7901SRyder Lee 105cd4c314aSBo Jiao /* for mt7915, the ring which is next the last 106cd4c314aSBo Jiao * used ring must be initialized. 107cd4c314aSBo Jiao */ 108cd4c314aSBo Jiao if (is_mt7915(&dev->mt76)) { 109cd4c314aSBo Jiao ofs += 0x4; 110cd4c314aSBo Jiao mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x140, 0x0)); 111*aa79fe87SBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT_WA) + ofs, PREFETCH(0x200 + base, 0x0)); 112*aa79fe87SBo Jiao mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT) + ofs, PREFETCH(0x280 + base, 0x0)); 113cd4c314aSBo Jiao } 1149093cfffSFelix Fietkau } 1159093cfffSFelix Fietkau 1169093cfffSFelix Fietkau void mt7915_dma_prefetch(struct mt7915_dev *dev) 1179093cfffSFelix Fietkau { 1189093cfffSFelix Fietkau __mt7915_dma_prefetch(dev, 0); 1199093cfffSFelix Fietkau if (dev->hif2) 120cd4c314aSBo Jiao __mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); 121e57b7901SRyder Lee } 122e57b7901SRyder Lee 123*aa79fe87SBo Jiao static void mt7915_dma_disable(struct mt7915_dev *dev, bool rst) 124*aa79fe87SBo Jiao { 125*aa79fe87SBo Jiao struct mt76_dev *mdev = &dev->mt76; 126*aa79fe87SBo Jiao u32 hif1_ofs = 0; 127*aa79fe87SBo Jiao 128*aa79fe87SBo Jiao if (dev->hif2) 129*aa79fe87SBo Jiao hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 130*aa79fe87SBo Jiao 131*aa79fe87SBo Jiao /* reset */ 132*aa79fe87SBo Jiao if (rst) { 133*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_RST, 134*aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 135*aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 136*aa79fe87SBo Jiao 137*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_RST, 138*aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 139*aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 140*aa79fe87SBo Jiao 141*aa79fe87SBo Jiao if (is_mt7915(mdev)) { 142*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_RST, 143*aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 144*aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 145*aa79fe87SBo Jiao 146*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_RST, 147*aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 148*aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 149*aa79fe87SBo Jiao } 150*aa79fe87SBo Jiao 151*aa79fe87SBo Jiao if (dev->hif2) { 152*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs, 153*aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 154*aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 155*aa79fe87SBo Jiao 156*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_RST + hif1_ofs, 157*aa79fe87SBo Jiao MT_WFDMA0_RST_DMASHDL_ALL_RST | 158*aa79fe87SBo Jiao MT_WFDMA0_RST_LOGIC_RST); 159*aa79fe87SBo Jiao 160*aa79fe87SBo Jiao if (is_mt7915(mdev)) { 161*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_RST + hif1_ofs, 162*aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 163*aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 164*aa79fe87SBo Jiao 165*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_RST + hif1_ofs, 166*aa79fe87SBo Jiao MT_WFDMA1_RST_DMASHDL_ALL_RST | 167*aa79fe87SBo Jiao MT_WFDMA1_RST_LOGIC_RST); 168*aa79fe87SBo Jiao } 169*aa79fe87SBo Jiao } 170*aa79fe87SBo Jiao } 171*aa79fe87SBo Jiao 172*aa79fe87SBo Jiao /* disable */ 173*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_GLO_CFG, 174*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 175*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 176*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 177*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | 178*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 179*aa79fe87SBo Jiao 180*aa79fe87SBo Jiao if (is_mt7915(mdev)) 181*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_GLO_CFG, 182*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 183*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 184*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 185*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO | 186*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2); 187*aa79fe87SBo Jiao 188*aa79fe87SBo Jiao if (dev->hif2) { 189*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 190*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 191*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 192*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 193*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | 194*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 195*aa79fe87SBo Jiao 196*aa79fe87SBo Jiao if (is_mt7915(mdev)) 197*aa79fe87SBo Jiao mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 198*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 199*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 200*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 201*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO | 202*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2); 203*aa79fe87SBo Jiao } 204*aa79fe87SBo Jiao } 205*aa79fe87SBo Jiao 206*aa79fe87SBo Jiao static int mt7915_dma_enable(struct mt7915_dev *dev) 207*aa79fe87SBo Jiao { 208*aa79fe87SBo Jiao struct mt76_dev *mdev = &dev->mt76; 209*aa79fe87SBo Jiao u32 hif1_ofs = 0; 210*aa79fe87SBo Jiao u32 irq_mask; 211*aa79fe87SBo Jiao 212*aa79fe87SBo Jiao if (dev->hif2) 213*aa79fe87SBo Jiao hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 214*aa79fe87SBo Jiao 215*aa79fe87SBo Jiao /* reset dma idx */ 216*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); 217*aa79fe87SBo Jiao if (is_mt7915(mdev)) 218*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0); 219*aa79fe87SBo Jiao if (dev->hif2) { 220*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0); 221*aa79fe87SBo Jiao if (is_mt7915(mdev)) 222*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0); 223*aa79fe87SBo Jiao } 224*aa79fe87SBo Jiao 225*aa79fe87SBo Jiao /* configure delay interrupt off */ 226*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); 227*aa79fe87SBo Jiao if (is_mt7915(mdev)) { 228*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0); 229*aa79fe87SBo Jiao } else { 230*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0); 231*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0); 232*aa79fe87SBo Jiao } 233*aa79fe87SBo Jiao 234*aa79fe87SBo Jiao if (dev->hif2) { 235*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0); 236*aa79fe87SBo Jiao if (is_mt7915(mdev)) { 237*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0 + 238*aa79fe87SBo Jiao hif1_ofs, 0); 239*aa79fe87SBo Jiao } else { 240*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + 241*aa79fe87SBo Jiao hif1_ofs, 0); 242*aa79fe87SBo Jiao mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + 243*aa79fe87SBo Jiao hif1_ofs, 0); 244*aa79fe87SBo Jiao } 245*aa79fe87SBo Jiao } 246*aa79fe87SBo Jiao 247*aa79fe87SBo Jiao /* configure perfetch settings */ 248*aa79fe87SBo Jiao mt7915_dma_prefetch(dev); 249*aa79fe87SBo Jiao 250*aa79fe87SBo Jiao /* hif wait WFDMA idle */ 251*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_BUSY_ENA, 252*aa79fe87SBo Jiao MT_WFDMA0_BUSY_ENA_TX_FIFO0 | 253*aa79fe87SBo Jiao MT_WFDMA0_BUSY_ENA_TX_FIFO1 | 254*aa79fe87SBo Jiao MT_WFDMA0_BUSY_ENA_RX_FIFO); 255*aa79fe87SBo Jiao 256*aa79fe87SBo Jiao if (is_mt7915(mdev)) 257*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_BUSY_ENA, 258*aa79fe87SBo Jiao MT_WFDMA1_BUSY_ENA_TX_FIFO0 | 259*aa79fe87SBo Jiao MT_WFDMA1_BUSY_ENA_TX_FIFO1 | 260*aa79fe87SBo Jiao MT_WFDMA1_BUSY_ENA_RX_FIFO); 261*aa79fe87SBo Jiao 262*aa79fe87SBo Jiao if (dev->hif2) { 263*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs, 264*aa79fe87SBo Jiao MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | 265*aa79fe87SBo Jiao MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | 266*aa79fe87SBo Jiao MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); 267*aa79fe87SBo Jiao 268*aa79fe87SBo Jiao if (is_mt7915(mdev)) 269*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_BUSY_ENA + hif1_ofs, 270*aa79fe87SBo Jiao MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 | 271*aa79fe87SBo Jiao MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 | 272*aa79fe87SBo Jiao MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO); 273*aa79fe87SBo Jiao } 274*aa79fe87SBo Jiao 275*aa79fe87SBo Jiao mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, 276*aa79fe87SBo Jiao MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); 277*aa79fe87SBo Jiao 278*aa79fe87SBo Jiao /* set WFDMA Tx/Rx */ 279*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_GLO_CFG, 280*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 281*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 282*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 283*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 284*aa79fe87SBo Jiao 285*aa79fe87SBo Jiao if (is_mt7915(mdev)) 286*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_GLO_CFG, 287*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 288*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 289*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 290*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 291*aa79fe87SBo Jiao 292*aa79fe87SBo Jiao if (dev->hif2) { 293*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, 294*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_TX_DMA_EN | 295*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_RX_DMA_EN | 296*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | 297*aa79fe87SBo Jiao MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); 298*aa79fe87SBo Jiao 299*aa79fe87SBo Jiao if (is_mt7915(mdev)) 300*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs, 301*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_TX_DMA_EN | 302*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_RX_DMA_EN | 303*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_TX_INFO | 304*aa79fe87SBo Jiao MT_WFDMA1_GLO_CFG_OMIT_RX_INFO); 305*aa79fe87SBo Jiao 306*aa79fe87SBo Jiao mt76_set(dev, MT_WFDMA_HOST_CONFIG, 307*aa79fe87SBo Jiao MT_WFDMA_HOST_CONFIG_PDMA_BAND); 308*aa79fe87SBo Jiao } 309*aa79fe87SBo Jiao 310*aa79fe87SBo Jiao /* enable interrupts for TX/RX rings */ 311*aa79fe87SBo Jiao irq_mask = MT_INT_RX_DONE_MCU | 312*aa79fe87SBo Jiao MT_INT_TX_DONE_MCU | 313*aa79fe87SBo Jiao MT_INT_MCU_CMD | 314*aa79fe87SBo Jiao MT_INT_BAND0_RX_DONE; 315*aa79fe87SBo Jiao 316*aa79fe87SBo Jiao if (dev->dbdc_support) 317*aa79fe87SBo Jiao irq_mask |= MT_INT_BAND1_RX_DONE; 318*aa79fe87SBo Jiao 319*aa79fe87SBo Jiao mt7915_irq_enable(dev, irq_mask); 320*aa79fe87SBo Jiao 321*aa79fe87SBo Jiao return 0; 322*aa79fe87SBo Jiao } 323*aa79fe87SBo Jiao 324e57b7901SRyder Lee int mt7915_dma_init(struct mt7915_dev *dev) 325e57b7901SRyder Lee { 326*aa79fe87SBo Jiao struct mt76_dev *mdev = &dev->mt76; 3279093cfffSFelix Fietkau u32 hif1_ofs = 0; 328e57b7901SRyder Lee int ret; 329e57b7901SRyder Lee 330cd4c314aSBo Jiao mt7915_dma_config(dev); 331cd4c314aSBo Jiao 332e57b7901SRyder Lee mt76_dma_attach(&dev->mt76); 333e57b7901SRyder Lee 3349093cfffSFelix Fietkau if (dev->hif2) 335cd4c314aSBo Jiao hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 3369093cfffSFelix Fietkau 337*aa79fe87SBo Jiao mt7915_dma_disable(dev, true); 3389093cfffSFelix Fietkau 339e57b7901SRyder Lee /* init tx queue */ 340cd4c314aSBo Jiao ret = mt7915_init_tx_queues(&dev->phy, 341cd4c314aSBo Jiao MT_TXQ_ID(0), 342cd4c314aSBo Jiao MT7915_TX_RING_SIZE, 343cd4c314aSBo Jiao MT_TXQ_RING_BASE(0)); 344e57b7901SRyder Lee if (ret) 345e57b7901SRyder Lee return ret; 346e57b7901SRyder Lee 347e57b7901SRyder Lee /* command to WM */ 348cd4c314aSBo Jiao ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, 349cd4c314aSBo Jiao MT_MCUQ_ID(MT_MCUQ_WM), 350cd4c314aSBo Jiao MT7915_TX_MCU_RING_SIZE, 351cd4c314aSBo Jiao MT_MCUQ_RING_BASE(MT_MCUQ_WM)); 352e57b7901SRyder Lee if (ret) 353e57b7901SRyder Lee return ret; 354e57b7901SRyder Lee 355e57b7901SRyder Lee /* command to WA */ 356cd4c314aSBo Jiao ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, 357cd4c314aSBo Jiao MT_MCUQ_ID(MT_MCUQ_WA), 358cd4c314aSBo Jiao MT7915_TX_MCU_RING_SIZE, 359cd4c314aSBo Jiao MT_MCUQ_RING_BASE(MT_MCUQ_WA)); 360e57b7901SRyder Lee if (ret) 361e57b7901SRyder Lee return ret; 362e57b7901SRyder Lee 363e57b7901SRyder Lee /* firmware download */ 364cd4c314aSBo Jiao ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, 365cd4c314aSBo Jiao MT_MCUQ_ID(MT_MCUQ_FWDL), 366cd4c314aSBo Jiao MT7915_TX_FWDL_RING_SIZE, 367cd4c314aSBo Jiao MT_MCUQ_RING_BASE(MT_MCUQ_FWDL)); 368e57b7901SRyder Lee if (ret) 369e57b7901SRyder Lee return ret; 370e57b7901SRyder Lee 371e57b7901SRyder Lee /* event from WM */ 372e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 373cd4c314aSBo Jiao MT_RXQ_ID(MT_RXQ_MCU), 374cd4c314aSBo Jiao MT7915_RX_MCU_RING_SIZE, 375cd4c314aSBo Jiao MT_RX_BUF_SIZE, 376cd4c314aSBo Jiao MT_RXQ_RING_BASE(MT_RXQ_MCU)); 377e57b7901SRyder Lee if (ret) 378e57b7901SRyder Lee return ret; 379e57b7901SRyder Lee 380e57b7901SRyder Lee /* event from WA */ 381e57b7901SRyder Lee ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 382cd4c314aSBo Jiao MT_RXQ_ID(MT_RXQ_MCU_WA), 383cd4c314aSBo Jiao MT7915_RX_MCU_RING_SIZE, 384cd4c314aSBo Jiao MT_RX_BUF_SIZE, 385cd4c314aSBo Jiao MT_RXQ_RING_BASE(MT_RXQ_MCU_WA)); 386e57b7901SRyder Lee if (ret) 387e57b7901SRyder Lee return ret; 388e57b7901SRyder Lee 389*aa79fe87SBo Jiao /* rx data queue for band0 */ 3904c430774SLorenzo Bianconi ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 391cd4c314aSBo Jiao MT_RXQ_ID(MT_RXQ_MAIN), 392cd4c314aSBo Jiao MT7915_RX_RING_SIZE, 393cd4c314aSBo Jiao MT_RX_BUF_SIZE, 394cd4c314aSBo Jiao MT_RXQ_RING_BASE(MT_RXQ_MAIN)); 395e57b7901SRyder Lee if (ret) 396e57b7901SRyder Lee return ret; 397e57b7901SRyder Lee 398*aa79fe87SBo Jiao /* tx free notify event from WA for band0 */ 399*aa79fe87SBo Jiao if (!is_mt7915(mdev)) { 400*aa79fe87SBo Jiao ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], 401*aa79fe87SBo Jiao MT_RXQ_ID(MT_RXQ_MAIN_WA), 402*aa79fe87SBo Jiao MT7915_RX_MCU_RING_SIZE, 403*aa79fe87SBo Jiao MT_RX_BUF_SIZE, 404*aa79fe87SBo Jiao MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA)); 405*aa79fe87SBo Jiao if (ret) 406*aa79fe87SBo Jiao return ret; 407*aa79fe87SBo Jiao } 408*aa79fe87SBo Jiao 4094c430774SLorenzo Bianconi if (dev->dbdc_support) { 410*aa79fe87SBo Jiao /* rx data queue for band1 */ 4114c430774SLorenzo Bianconi ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT], 412cd4c314aSBo Jiao MT_RXQ_ID(MT_RXQ_EXT), 413cd4c314aSBo Jiao MT7915_RX_RING_SIZE, 41449c9a263SLorenzo Bianconi MT_RX_BUF_SIZE, 415cd4c314aSBo Jiao MT_RXQ_RING_BASE(MT_RXQ_EXT) + hif1_ofs); 4164c430774SLorenzo Bianconi if (ret) 4174c430774SLorenzo Bianconi return ret; 41876027f40SFelix Fietkau 419*aa79fe87SBo Jiao /* tx free notify event from WA for band1 */ 42076027f40SFelix Fietkau ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT_WA], 421cd4c314aSBo Jiao MT_RXQ_ID(MT_RXQ_EXT_WA), 42276027f40SFelix Fietkau MT7915_RX_MCU_RING_SIZE, 42349c9a263SLorenzo Bianconi MT_RX_BUF_SIZE, 424cd4c314aSBo Jiao MT_RXQ_RING_BASE(MT_RXQ_EXT_WA) + hif1_ofs); 42576027f40SFelix Fietkau if (ret) 42676027f40SFelix Fietkau return ret; 4274c430774SLorenzo Bianconi } 4284c430774SLorenzo Bianconi 429cb8ed33dSLorenzo Bianconi ret = mt76_init_queues(dev, mt76_dma_rx_poll); 430e57b7901SRyder Lee if (ret < 0) 431e57b7901SRyder Lee return ret; 432e57b7901SRyder Lee 433aa40528aSFelix Fietkau netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 434e57b7901SRyder Lee mt7915_poll_tx, NAPI_POLL_WEIGHT); 435e57b7901SRyder Lee napi_enable(&dev->mt76.tx_napi); 436e57b7901SRyder Lee 437*aa79fe87SBo Jiao mt7915_dma_enable(dev); 438e57b7901SRyder Lee 439e57b7901SRyder Lee return 0; 440e57b7901SRyder Lee } 441e57b7901SRyder Lee 442e57b7901SRyder Lee void mt7915_dma_cleanup(struct mt7915_dev *dev) 443e57b7901SRyder Lee { 444*aa79fe87SBo Jiao mt7915_dma_disable(dev, true); 445e57b7901SRyder Lee 446e57b7901SRyder Lee mt76_dma_cleanup(&dev->mt76); 447e57b7901SRyder Lee } 448