1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/relay.h> 5 #include "mt7915.h" 6 #include "eeprom.h" 7 #include "mcu.h" 8 #include "mac.h" 9 10 #define FW_BIN_LOG_MAGIC 0x44e98caf 11 12 /** global debugfs **/ 13 14 struct hw_queue_map { 15 const char *name; 16 u8 index; 17 u8 pid; 18 u8 qid; 19 }; 20 21 static int 22 mt7915_implicit_txbf_set(void *data, u64 val) 23 { 24 struct mt7915_dev *dev = data; 25 26 /* The existing connected stations shall reconnect to apply 27 * new implicit txbf configuration. 28 */ 29 dev->ibf = !!val; 30 31 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 32 } 33 34 static int 35 mt7915_implicit_txbf_get(void *data, u64 *val) 36 { 37 struct mt7915_dev *dev = data; 38 39 *val = dev->ibf; 40 41 return 0; 42 } 43 44 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get, 45 mt7915_implicit_txbf_set, "%lld\n"); 46 47 /* test knob of system error recovery */ 48 static ssize_t 49 mt7915_sys_recovery_set(struct file *file, const char __user *user_buf, 50 size_t count, loff_t *ppos) 51 { 52 struct mt7915_phy *phy = file->private_data; 53 struct mt7915_dev *dev = phy->dev; 54 bool band = phy->mt76->band_idx; 55 char buf[16]; 56 int ret = 0; 57 u16 val; 58 59 if (count >= sizeof(buf)) 60 return -EINVAL; 61 62 if (copy_from_user(buf, user_buf, count)) 63 return -EFAULT; 64 65 if (count && buf[count - 1] == '\n') 66 buf[count - 1] = '\0'; 67 else 68 buf[count] = '\0'; 69 70 if (kstrtou16(buf, 0, &val)) 71 return -EINVAL; 72 73 switch (val) { 74 /* 75 * 0: grab firmware current SER state. 76 * 1: trigger & enable system error L1 recovery. 77 * 2: trigger & enable system error L2 recovery. 78 * 3: trigger & enable system error L3 rx abort. 79 * 4: trigger & enable system error L3 tx abort 80 * 5: trigger & enable system error L3 tx disable. 81 * 6: trigger & enable system error L3 bf recovery. 82 * 7: trigger & enable system error full recovery. 83 * 8: trigger firmware crash. 84 */ 85 case SER_QUERY: 86 ret = mt7915_mcu_set_ser(dev, 0, 0, band); 87 break; 88 case SER_SET_RECOVER_L1: 89 case SER_SET_RECOVER_L2: 90 case SER_SET_RECOVER_L3_RX_ABORT: 91 case SER_SET_RECOVER_L3_TX_ABORT: 92 case SER_SET_RECOVER_L3_TX_DISABLE: 93 case SER_SET_RECOVER_L3_BF: 94 ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), band); 95 if (ret) 96 return ret; 97 98 ret = mt7915_mcu_set_ser(dev, SER_RECOVER, val, band); 99 break; 100 101 /* enable full chip reset */ 102 case SER_SET_RECOVER_FULL: 103 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 104 ret = mt7915_mcu_set_ser(dev, 1, 3, band); 105 if (ret) 106 return ret; 107 108 dev->recovery.state |= MT_MCU_CMD_WDT_MASK; 109 mt7915_reset(dev); 110 break; 111 112 /* WARNING: trigger firmware crash */ 113 case SER_SET_SYSTEM_ASSERT: 114 mt76_wr(dev, MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR, BIT(18)); 115 mt76_wr(dev, MT_MCU_WM_CIRQ_EINT_SOFT_ADDR, BIT(18)); 116 break; 117 default: 118 break; 119 } 120 121 return ret ? ret : count; 122 } 123 124 static ssize_t 125 mt7915_sys_recovery_get(struct file *file, char __user *user_buf, 126 size_t count, loff_t *ppos) 127 { 128 struct mt7915_phy *phy = file->private_data; 129 struct mt7915_dev *dev = phy->dev; 130 char *buff; 131 int desc = 0; 132 ssize_t ret; 133 static const size_t bufsz = 1024; 134 135 buff = kmalloc(bufsz, GFP_KERNEL); 136 if (!buff) 137 return -ENOMEM; 138 139 /* HELP */ 140 desc += scnprintf(buff + desc, bufsz - desc, 141 "Please echo the correct value ...\n"); 142 desc += scnprintf(buff + desc, bufsz - desc, 143 "0: grab firmware transient SER state\n"); 144 desc += scnprintf(buff + desc, bufsz - desc, 145 "1: trigger system error L1 recovery\n"); 146 desc += scnprintf(buff + desc, bufsz - desc, 147 "2: trigger system error L2 recovery\n"); 148 desc += scnprintf(buff + desc, bufsz - desc, 149 "3: trigger system error L3 rx abort\n"); 150 desc += scnprintf(buff + desc, bufsz - desc, 151 "4: trigger system error L3 tx abort\n"); 152 desc += scnprintf(buff + desc, bufsz - desc, 153 "5: trigger system error L3 tx disable\n"); 154 desc += scnprintf(buff + desc, bufsz - desc, 155 "6: trigger system error L3 bf recovery\n"); 156 desc += scnprintf(buff + desc, bufsz - desc, 157 "7: trigger system error full recovery\n"); 158 desc += scnprintf(buff + desc, bufsz - desc, 159 "8: trigger firmware crash\n"); 160 161 /* SER statistics */ 162 desc += scnprintf(buff + desc, bufsz - desc, 163 "\nlet's dump firmware SER statistics...\n"); 164 desc += scnprintf(buff + desc, bufsz - desc, 165 "::E R , SER_STATUS = 0x%08x\n", 166 mt76_rr(dev, MT_SWDEF_SER_STATS)); 167 desc += scnprintf(buff + desc, bufsz - desc, 168 "::E R , SER_PLE_ERR = 0x%08x\n", 169 mt76_rr(dev, MT_SWDEF_PLE_STATS)); 170 desc += scnprintf(buff + desc, bufsz - desc, 171 "::E R , SER_PLE_ERR_1 = 0x%08x\n", 172 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); 173 desc += scnprintf(buff + desc, bufsz - desc, 174 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n", 175 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); 176 desc += scnprintf(buff + desc, bufsz - desc, 177 "::E R , SER_PSE_ERR = 0x%08x\n", 178 mt76_rr(dev, MT_SWDEF_PSE_STATS)); 179 desc += scnprintf(buff + desc, bufsz - desc, 180 "::E R , SER_PSE_ERR_1 = 0x%08x\n", 181 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); 182 desc += scnprintf(buff + desc, bufsz - desc, 183 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n", 184 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); 185 desc += scnprintf(buff + desc, bufsz - desc, 186 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n", 187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); 188 desc += scnprintf(buff + desc, bufsz - desc, 189 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n", 190 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); 191 desc += scnprintf(buff + desc, bufsz - desc, 192 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n", 193 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); 194 desc += scnprintf(buff + desc, bufsz - desc, 195 "\nSYS_RESET_COUNT: WM %d, WA %d\n", 196 dev->recovery.wm_reset_count, 197 dev->recovery.wa_reset_count); 198 199 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); 200 kfree(buff); 201 return ret; 202 } 203 204 static const struct file_operations mt7915_sys_recovery_ops = { 205 .write = mt7915_sys_recovery_set, 206 .read = mt7915_sys_recovery_get, 207 .open = simple_open, 208 .llseek = default_llseek, 209 }; 210 211 static int 212 mt7915_radar_trigger(void *data, u64 val) 213 { 214 struct mt7915_dev *dev = data; 215 216 if (val > MT_RX_SEL2) 217 return -EINVAL; 218 219 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_RADAR_EMULATE, 220 val, 0, 0); 221 } 222 223 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, 224 mt7915_radar_trigger, "%lld\n"); 225 226 static int 227 mt7915_muru_debug_set(void *data, u64 val) 228 { 229 struct mt7915_dev *dev = data; 230 231 dev->muru_debug = val; 232 mt7915_mcu_muru_debug_set(dev, dev->muru_debug); 233 234 return 0; 235 } 236 237 static int 238 mt7915_muru_debug_get(void *data, u64 *val) 239 { 240 struct mt7915_dev *dev = data; 241 242 *val = dev->muru_debug; 243 244 return 0; 245 } 246 247 DEFINE_DEBUGFS_ATTRIBUTE(fops_muru_debug, mt7915_muru_debug_get, 248 mt7915_muru_debug_set, "%lld\n"); 249 250 static int mt7915_muru_stats_show(struct seq_file *file, void *data) 251 { 252 struct mt7915_phy *phy = file->private; 253 struct mt7915_dev *dev = phy->dev; 254 struct mt7915_mcu_muru_stats mu_stats = {}; 255 static const char * const dl_non_he_type[] = { 256 "CCK", "OFDM", "HT MIX", "HT GF", 257 "VHT SU", "VHT 2MU", "VHT 3MU", "VHT 4MU" 258 }; 259 static const char * const dl_he_type[] = { 260 "HE SU", "HE EXT", "HE 2MU", "HE 3MU", "HE 4MU", 261 "HE 2RU", "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", 262 "HE >16RU" 263 }; 264 static const char * const ul_he_type[] = { 265 "HE 2MU", "HE 3MU", "HE 4MU", "HE SU", "HE 2RU", 266 "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", "HE >16RU" 267 }; 268 int ret, i; 269 u64 total_ppdu_cnt, sub_total_cnt; 270 271 if (!dev->muru_debug) { 272 seq_puts(file, "Please enable muru_debug first.\n"); 273 return 0; 274 } 275 276 mutex_lock(&dev->mt76.mutex); 277 278 ret = mt7915_mcu_muru_debug_get(phy, &mu_stats); 279 if (ret) 280 goto exit; 281 282 /* Non-HE Downlink*/ 283 seq_puts(file, "[Non-HE]\nDownlink\nData Type: "); 284 285 for (i = 0; i < 5; i++) 286 seq_printf(file, "%8s | ", dl_non_he_type[i]); 287 288 #define __dl_u32(s) le32_to_cpu(mu_stats.dl.s) 289 seq_puts(file, "\nTotal Count:"); 290 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | ", 291 __dl_u32(cck_cnt), 292 __dl_u32(ofdm_cnt), 293 __dl_u32(htmix_cnt), 294 __dl_u32(htgf_cnt), 295 __dl_u32(vht_su_cnt)); 296 297 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); 298 299 for (i = 5; i < 8; i++) 300 seq_printf(file, "%8s | ", dl_non_he_type[i]); 301 302 seq_puts(file, "\nTotal Count:"); 303 seq_printf(file, "%8u | %8u | %8u | ", 304 __dl_u32(vht_2mu_cnt), 305 __dl_u32(vht_3mu_cnt), 306 __dl_u32(vht_4mu_cnt)); 307 308 sub_total_cnt = __dl_u32(vht_2mu_cnt) + 309 __dl_u32(vht_3mu_cnt) + 310 __dl_u32(vht_4mu_cnt); 311 312 seq_printf(file, "\nTotal non-HE MU-MIMO DL PPDU count: %lld", 313 sub_total_cnt); 314 315 total_ppdu_cnt = sub_total_cnt + 316 __dl_u32(cck_cnt) + 317 __dl_u32(ofdm_cnt) + 318 __dl_u32(htmix_cnt) + 319 __dl_u32(htgf_cnt) + 320 __dl_u32(vht_su_cnt); 321 322 seq_printf(file, "\nAll non-HE DL PPDU count: %lld", total_ppdu_cnt); 323 324 /* HE Downlink */ 325 seq_puts(file, "\n\n[HE]\nDownlink\nData Type: "); 326 327 for (i = 0; i < 2; i++) 328 seq_printf(file, "%8s | ", dl_he_type[i]); 329 330 seq_puts(file, "\nTotal Count:"); 331 seq_printf(file, "%8u | %8u | ", 332 __dl_u32(he_su_cnt), 333 __dl_u32(he_ext_su_cnt)); 334 335 seq_puts(file, "\nDownlink MU-MIMO\nData Type: "); 336 337 for (i = 2; i < 5; i++) 338 seq_printf(file, "%8s | ", dl_he_type[i]); 339 340 seq_puts(file, "\nTotal Count:"); 341 seq_printf(file, "%8u | %8u | %8u | ", 342 __dl_u32(he_2mu_cnt), 343 __dl_u32(he_3mu_cnt), 344 __dl_u32(he_4mu_cnt)); 345 346 seq_puts(file, "\nDownlink OFDMA\nData Type: "); 347 348 for (i = 5; i < 11; i++) 349 seq_printf(file, "%8s | ", dl_he_type[i]); 350 351 seq_puts(file, "\nTotal Count:"); 352 seq_printf(file, "%8u | %8u | %8u | %8u | %9u | %8u | ", 353 __dl_u32(he_2ru_cnt), 354 __dl_u32(he_3ru_cnt), 355 __dl_u32(he_4ru_cnt), 356 __dl_u32(he_5to8ru_cnt), 357 __dl_u32(he_9to16ru_cnt), 358 __dl_u32(he_gtr16ru_cnt)); 359 360 sub_total_cnt = __dl_u32(he_2mu_cnt) + 361 __dl_u32(he_3mu_cnt) + 362 __dl_u32(he_4mu_cnt); 363 total_ppdu_cnt = sub_total_cnt; 364 365 seq_printf(file, "\nTotal HE MU-MIMO DL PPDU count: %lld", 366 sub_total_cnt); 367 368 sub_total_cnt = __dl_u32(he_2ru_cnt) + 369 __dl_u32(he_3ru_cnt) + 370 __dl_u32(he_4ru_cnt) + 371 __dl_u32(he_5to8ru_cnt) + 372 __dl_u32(he_9to16ru_cnt) + 373 __dl_u32(he_gtr16ru_cnt); 374 total_ppdu_cnt += sub_total_cnt; 375 376 seq_printf(file, "\nTotal HE OFDMA DL PPDU count: %lld", 377 sub_total_cnt); 378 379 total_ppdu_cnt += __dl_u32(he_su_cnt) + 380 __dl_u32(he_ext_su_cnt); 381 382 seq_printf(file, "\nAll HE DL PPDU count: %lld", total_ppdu_cnt); 383 #undef __dl_u32 384 385 /* HE Uplink */ 386 seq_puts(file, "\n\nUplink"); 387 seq_puts(file, "\nTrigger-based Uplink MU-MIMO\nData Type: "); 388 389 for (i = 0; i < 3; i++) 390 seq_printf(file, "%8s | ", ul_he_type[i]); 391 392 #define __ul_u32(s) le32_to_cpu(mu_stats.ul.s) 393 seq_puts(file, "\nTotal Count:"); 394 seq_printf(file, "%8u | %8u | %8u | ", 395 __ul_u32(hetrig_2mu_cnt), 396 __ul_u32(hetrig_3mu_cnt), 397 __ul_u32(hetrig_4mu_cnt)); 398 399 seq_puts(file, "\nTrigger-based Uplink OFDMA\nData Type: "); 400 401 for (i = 3; i < 10; i++) 402 seq_printf(file, "%8s | ", ul_he_type[i]); 403 404 seq_puts(file, "\nTotal Count:"); 405 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | %9u | %7u | ", 406 __ul_u32(hetrig_su_cnt), 407 __ul_u32(hetrig_2ru_cnt), 408 __ul_u32(hetrig_3ru_cnt), 409 __ul_u32(hetrig_4ru_cnt), 410 __ul_u32(hetrig_5to8ru_cnt), 411 __ul_u32(hetrig_9to16ru_cnt), 412 __ul_u32(hetrig_gtr16ru_cnt)); 413 414 sub_total_cnt = __ul_u32(hetrig_2mu_cnt) + 415 __ul_u32(hetrig_3mu_cnt) + 416 __ul_u32(hetrig_4mu_cnt); 417 total_ppdu_cnt = sub_total_cnt; 418 419 seq_printf(file, "\nTotal HE MU-MIMO UL TB PPDU count: %lld", 420 sub_total_cnt); 421 422 sub_total_cnt = __ul_u32(hetrig_2ru_cnt) + 423 __ul_u32(hetrig_3ru_cnt) + 424 __ul_u32(hetrig_4ru_cnt) + 425 __ul_u32(hetrig_5to8ru_cnt) + 426 __ul_u32(hetrig_9to16ru_cnt) + 427 __ul_u32(hetrig_gtr16ru_cnt); 428 total_ppdu_cnt += sub_total_cnt; 429 430 seq_printf(file, "\nTotal HE OFDMA UL TB PPDU count: %lld", 431 sub_total_cnt); 432 433 total_ppdu_cnt += __ul_u32(hetrig_su_cnt); 434 435 seq_printf(file, "\nAll HE UL TB PPDU count: %lld\n", total_ppdu_cnt); 436 #undef __ul_u32 437 438 exit: 439 mutex_unlock(&dev->mt76.mutex); 440 441 return ret; 442 } 443 DEFINE_SHOW_ATTRIBUTE(mt7915_muru_stats); 444 445 static int 446 mt7915_rdd_monitor(struct seq_file *s, void *data) 447 { 448 struct mt7915_dev *dev = dev_get_drvdata(s->private); 449 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; 450 const char *bw; 451 int ret = 0; 452 453 mutex_lock(&dev->mt76.mutex); 454 455 if (!cfg80211_chandef_valid(chandef)) { 456 ret = -EINVAL; 457 goto out; 458 } 459 460 if (!dev->rdd2_phy) { 461 seq_puts(s, "not running\n"); 462 goto out; 463 } 464 465 switch (chandef->width) { 466 case NL80211_CHAN_WIDTH_40: 467 bw = "40"; 468 break; 469 case NL80211_CHAN_WIDTH_80: 470 bw = "80"; 471 break; 472 case NL80211_CHAN_WIDTH_160: 473 bw = "160"; 474 break; 475 case NL80211_CHAN_WIDTH_80P80: 476 bw = "80P80"; 477 break; 478 default: 479 bw = "20"; 480 break; 481 } 482 483 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", 484 chandef->chan->hw_value, chandef->chan->center_freq, 485 bw, chandef->center_freq1); 486 out: 487 mutex_unlock(&dev->mt76.mutex); 488 489 return ret; 490 } 491 492 static int 493 mt7915_fw_debug_wm_set(void *data, u64 val) 494 { 495 struct mt7915_dev *dev = data; 496 enum { 497 DEBUG_TXCMD = 62, 498 DEBUG_CMD_RPT_TX, 499 DEBUG_CMD_RPT_TRIG, 500 DEBUG_SPL, 501 DEBUG_RPT_RX, 502 } debug; 503 bool tx, rx, en; 504 int ret; 505 506 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; 507 508 if (dev->fw.debug_bin) 509 val = 16; 510 else 511 val = dev->fw.debug_wm; 512 513 tx = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(1)); 514 rx = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(2)); 515 en = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(0)); 516 517 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); 518 if (ret) 519 goto out; 520 521 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RX; debug++) { 522 if (debug == DEBUG_RPT_RX) 523 val = en && rx; 524 else 525 val = en && tx; 526 527 ret = mt7915_mcu_fw_dbg_ctrl(dev, debug, val); 528 if (ret) 529 goto out; 530 } 531 532 /* WM CPU info record control */ 533 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0)); 534 mt76_wr(dev, MT_DIC_CMD_REG_CMD, BIT(2) | BIT(13) | !dev->fw.debug_wm); 535 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5)); 536 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5)); 537 538 out: 539 if (ret) 540 dev->fw.debug_wm = 0; 541 542 return ret; 543 } 544 545 static int 546 mt7915_fw_debug_wm_get(void *data, u64 *val) 547 { 548 struct mt7915_dev *dev = data; 549 550 *val = dev->fw.debug_wm; 551 552 return 0; 553 } 554 555 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7915_fw_debug_wm_get, 556 mt7915_fw_debug_wm_set, "%lld\n"); 557 558 static int 559 mt7915_fw_debug_wa_set(void *data, u64 val) 560 { 561 struct mt7915_dev *dev = data; 562 int ret; 563 564 dev->fw.debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; 565 566 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw.debug_wa); 567 if (ret) 568 goto out; 569 570 ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 571 MCU_WA_PARAM_PDMA_RX, !!dev->fw.debug_wa, 0); 572 out: 573 if (ret) 574 dev->fw.debug_wa = 0; 575 576 return ret; 577 } 578 579 static int 580 mt7915_fw_debug_wa_get(void *data, u64 *val) 581 { 582 struct mt7915_dev *dev = data; 583 584 *val = dev->fw.debug_wa; 585 586 return 0; 587 } 588 589 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7915_fw_debug_wa_get, 590 mt7915_fw_debug_wa_set, "%lld\n"); 591 592 static struct dentry * 593 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, 594 struct rchan_buf *buf, int *is_global) 595 { 596 struct dentry *f; 597 598 f = debugfs_create_file("fwlog_data", mode, parent, buf, 599 &relay_file_operations); 600 if (IS_ERR(f)) 601 return NULL; 602 603 *is_global = 1; 604 605 return f; 606 } 607 608 static int 609 remove_buf_file_cb(struct dentry *f) 610 { 611 debugfs_remove(f); 612 613 return 0; 614 } 615 616 static int 617 mt7915_fw_debug_bin_set(void *data, u64 val) 618 { 619 static struct rchan_callbacks relay_cb = { 620 .create_buf_file = create_buf_file_cb, 621 .remove_buf_file = remove_buf_file_cb, 622 }; 623 struct mt7915_dev *dev = data; 624 625 if (!dev->relay_fwlog) 626 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, 627 1500, 512, &relay_cb, NULL); 628 if (!dev->relay_fwlog) 629 return -ENOMEM; 630 631 dev->fw.debug_bin = val; 632 633 relay_reset(dev->relay_fwlog); 634 635 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm); 636 } 637 638 static int 639 mt7915_fw_debug_bin_get(void *data, u64 *val) 640 { 641 struct mt7915_dev *dev = data; 642 643 *val = dev->fw.debug_bin; 644 645 return 0; 646 } 647 648 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7915_fw_debug_bin_get, 649 mt7915_fw_debug_bin_set, "%lld\n"); 650 651 static int 652 mt7915_fw_util_wm_show(struct seq_file *file, void *data) 653 { 654 struct mt7915_dev *dev = file->private; 655 656 seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WM_MCU_PC)); 657 658 if (dev->fw.debug_wm) { 659 seq_printf(file, "Busy: %u%% Peak busy: %u%%\n", 660 mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT), 661 mt76_rr(dev, MT_CPU_UTIL_PEAK_BUSY_PCT)); 662 seq_printf(file, "Idle count: %u Peak idle count: %u\n", 663 mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT), 664 mt76_rr(dev, MT_CPU_UTIL_PEAK_IDLE_CNT)); 665 } 666 667 return 0; 668 } 669 670 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wm); 671 672 static int 673 mt7915_fw_util_wa_show(struct seq_file *file, void *data) 674 { 675 struct mt7915_dev *dev = file->private; 676 677 seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WA_MCU_PC)); 678 679 if (dev->fw.debug_wa) 680 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), 681 MCU_WA_PARAM_CPU_UTIL, 0, 0); 682 683 return 0; 684 } 685 686 DEFINE_SHOW_ATTRIBUTE(mt7915_fw_util_wa); 687 688 static void 689 mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy, 690 struct seq_file *file) 691 { 692 struct mt7915_dev *dev = phy->dev; 693 bool ext_phy = phy != &dev->phy; 694 int bound[15], range[4], i; 695 u8 band = phy->mt76->band_idx; 696 697 /* Tx ampdu stat */ 698 for (i = 0; i < ARRAY_SIZE(range); i++) 699 range[i] = mt76_rr(dev, MT_MIB_ARNG(band, i)); 700 701 for (i = 0; i < ARRAY_SIZE(bound); i++) 702 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 4], i % 4) + 1; 703 704 seq_printf(file, "\nPhy %d, Phy band %d\n", ext_phy, band); 705 706 seq_printf(file, "Length: %8d | ", bound[0]); 707 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) 708 seq_printf(file, "%3d -%3d | ", 709 bound[i] + 1, bound[i + 1]); 710 711 seq_puts(file, "\nCount: "); 712 for (i = 0; i < ARRAY_SIZE(bound); i++) 713 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]); 714 seq_puts(file, "\n"); 715 716 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); 717 } 718 719 static void 720 mt7915_txbf_stat_read_phy(struct mt7915_phy *phy, struct seq_file *s) 721 { 722 static const char * const bw[] = { 723 "BW20", "BW40", "BW80", "BW160" 724 }; 725 struct mib_stats *mib = &phy->mib; 726 727 /* Tx Beamformer monitor */ 728 seq_puts(s, "\nTx Beamformer applied PPDU counts: "); 729 730 seq_printf(s, "iBF: %d, eBF: %d\n", 731 mib->tx_bf_ibf_ppdu_cnt, 732 mib->tx_bf_ebf_ppdu_cnt); 733 734 /* Tx Beamformer Rx feedback monitor */ 735 seq_puts(s, "Tx Beamformer Rx feedback statistics: "); 736 737 seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ", 738 mib->tx_bf_rx_fb_all_cnt, 739 mib->tx_bf_rx_fb_he_cnt, 740 mib->tx_bf_rx_fb_vht_cnt, 741 mib->tx_bf_rx_fb_ht_cnt); 742 743 seq_printf(s, "%s, NC: %d, NR: %d\n", 744 bw[mib->tx_bf_rx_fb_bw], 745 mib->tx_bf_rx_fb_nc_cnt, 746 mib->tx_bf_rx_fb_nr_cnt); 747 748 /* Tx Beamformee Rx NDPA & Tx feedback report */ 749 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", 750 mib->tx_bf_fb_cpl_cnt); 751 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", 752 mib->tx_bf_fb_trig_cnt); 753 754 /* Tx SU & MU counters */ 755 seq_printf(s, "Tx multi-user Beamforming counts: %d\n", 756 mib->tx_bf_cnt); 757 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); 758 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", 759 mib->tx_mu_acked_mpdu_cnt); 760 seq_printf(s, "Tx single-user successful MPDU counts: %d\n", 761 mib->tx_su_acked_mpdu_cnt); 762 763 seq_puts(s, "\n"); 764 } 765 766 static int 767 mt7915_tx_stats_show(struct seq_file *file, void *data) 768 { 769 struct mt7915_phy *phy = file->private; 770 struct mt7915_dev *dev = phy->dev; 771 struct mib_stats *mib = &phy->mib; 772 int i; 773 774 mutex_lock(&dev->mt76.mutex); 775 776 mt7915_ampdu_stat_read_phy(phy, file); 777 mt7915_mac_update_stats(phy); 778 mt7915_txbf_stat_read_phy(phy, file); 779 780 /* Tx amsdu info */ 781 seq_puts(file, "Tx MSDU statistics:\n"); 782 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 783 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", 784 i + 1, mib->tx_amsdu[i]); 785 if (mib->tx_amsdu_cnt) 786 seq_printf(file, "(%3d%%)\n", 787 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); 788 else 789 seq_puts(file, "\n"); 790 } 791 792 mutex_unlock(&dev->mt76.mutex); 793 794 return 0; 795 } 796 797 DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats); 798 799 static void 800 mt7915_hw_queue_read(struct seq_file *s, u32 size, 801 const struct hw_queue_map *map) 802 { 803 struct mt7915_phy *phy = s->private; 804 struct mt7915_dev *dev = phy->dev; 805 u32 i, val; 806 807 val = mt76_rr(dev, MT_FL_Q_EMPTY); 808 for (i = 0; i < size; i++) { 809 u32 ctrl, head, tail, queued; 810 811 if (val & BIT(map[i].index)) 812 continue; 813 814 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24); 815 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); 816 817 head = mt76_get_field(dev, MT_FL_Q2_CTRL, 818 GENMASK(11, 0)); 819 tail = mt76_get_field(dev, MT_FL_Q2_CTRL, 820 GENMASK(27, 16)); 821 queued = mt76_get_field(dev, MT_FL_Q3_CTRL, 822 GENMASK(11, 0)); 823 824 seq_printf(s, "\t%s: ", map[i].name); 825 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", 826 queued, head, tail); 827 } 828 } 829 830 static void 831 mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) 832 { 833 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 834 struct mt7915_dev *dev = msta->vif->phy->dev; 835 struct seq_file *s = data; 836 u8 ac; 837 838 for (ac = 0; ac < 4; ac++) { 839 u32 qlen, ctrl, val; 840 u32 idx = msta->wcid.idx >> 5; 841 u8 offs = msta->wcid.idx & GENMASK(4, 0); 842 843 ctrl = BIT(31) | BIT(11) | (ac << 24); 844 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); 845 846 if (val & BIT(offs)) 847 continue; 848 849 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx); 850 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, 851 GENMASK(11, 0)); 852 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", 853 sta->addr, msta->wcid.idx, 854 msta->vif->mt76.wmm_idx, ac, qlen); 855 } 856 } 857 858 static int 859 mt7915_hw_queues_show(struct seq_file *file, void *data) 860 { 861 struct mt7915_phy *phy = file->private; 862 struct mt7915_dev *dev = phy->dev; 863 static const struct hw_queue_map ple_queue_map[] = { 864 { "CPU_Q0", 0, 1, MT_CTX0 }, 865 { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, 866 { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, 867 { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, 868 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, 869 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, 870 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, 871 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, 872 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, 873 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, 874 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, 875 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, 876 }; 877 static const struct hw_queue_map pse_queue_map[] = { 878 { "CPU Q0", 0, 1, MT_CTX0 }, 879 { "CPU Q1", 1, 1, MT_CTX0 + 1 }, 880 { "CPU Q2", 2, 1, MT_CTX0 + 2 }, 881 { "CPU Q3", 3, 1, MT_CTX0 + 3 }, 882 { "HIF_Q0", 8, 0, MT_HIF0 }, 883 { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, 884 { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, 885 { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, 886 { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, 887 { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, 888 { "LMAC_Q", 16, 2, 0 }, 889 { "MDP_TXQ", 17, 2, 1 }, 890 { "MDP_RXQ", 18, 2, 2 }, 891 { "SEC_TXQ", 19, 2, 3 }, 892 { "SEC_RXQ", 20, 2, 4 }, 893 }; 894 u32 val, head, tail; 895 896 /* ple queue */ 897 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); 898 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); 899 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); 900 seq_puts(file, "PLE page info:\n"); 901 seq_printf(file, 902 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", 903 val, head, tail); 904 905 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); 906 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); 907 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); 908 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", 909 val, head, tail); 910 911 seq_puts(file, "PLE non-empty queue info:\n"); 912 mt7915_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), 913 &ple_queue_map[0]); 914 915 /* iterate per-sta ple queue */ 916 ieee80211_iterate_stations_atomic(phy->mt76->hw, 917 mt7915_sta_hw_queue_read, file); 918 /* pse queue */ 919 seq_puts(file, "PSE non-empty queue info:\n"); 920 mt7915_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), 921 &pse_queue_map[0]); 922 923 return 0; 924 } 925 926 DEFINE_SHOW_ATTRIBUTE(mt7915_hw_queues); 927 928 static int 929 mt7915_xmit_queues_show(struct seq_file *file, void *data) 930 { 931 struct mt7915_phy *phy = file->private; 932 struct mt7915_dev *dev = phy->dev; 933 struct { 934 struct mt76_queue *q; 935 char *queue; 936 } queue_map[] = { 937 { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" }, 938 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, 939 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, 940 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, 941 }; 942 int i; 943 944 seq_puts(file, " queue | hw-queued | head | tail |\n"); 945 for (i = 0; i < ARRAY_SIZE(queue_map); i++) { 946 struct mt76_queue *q = queue_map[i].q; 947 948 if (!q) 949 continue; 950 951 seq_printf(file, " %s | %9d | %9d | %9d |\n", 952 queue_map[i].queue, q->queued, q->head, 953 q->tail); 954 } 955 956 return 0; 957 } 958 959 DEFINE_SHOW_ATTRIBUTE(mt7915_xmit_queues); 960 961 #define mt7915_txpower_puts(prefix, rate) \ 962 ({ \ 963 len += scnprintf(buf + len, sz - len, "%-16s:", #prefix " (tmac)"); \ 964 for (i = 0; i < mt7915_sku_group_len[rate]; i++, offs++) \ 965 len += scnprintf(buf + len, sz - len, " %6d", txpwr[offs]); \ 966 len += scnprintf(buf + len, sz - len, "\n"); \ 967 }) 968 969 #define mt7915_txpower_sets(rate, pwr, flag) \ 970 ({ \ 971 offs += len; \ 972 len = mt7915_sku_group_len[rate]; \ 973 if (mode == flag) { \ 974 for (i = 0; i < len; i++) \ 975 req.txpower_sku[offs + i] = pwr; \ 976 } \ 977 }) 978 979 static ssize_t 980 mt7915_rate_txpower_get(struct file *file, char __user *user_buf, 981 size_t count, loff_t *ppos) 982 { 983 struct mt7915_phy *phy = file->private_data; 984 struct mt7915_dev *dev = phy->dev; 985 s8 txpwr[MT7915_SKU_RATE_NUM]; 986 static const size_t sz = 2048; 987 u8 band = phy->mt76->band_idx; 988 int i, offs = 0, len = 0; 989 ssize_t ret; 990 char *buf; 991 u32 reg; 992 993 buf = kzalloc(sz, GFP_KERNEL); 994 if (!buf) 995 return -ENOMEM; 996 997 ret = mt7915_mcu_get_txpower_sku(phy, txpwr, sizeof(txpwr)); 998 if (ret) 999 goto out; 1000 1001 /* Txpower propagation path: TMAC -> TXV -> BBP */ 1002 len += scnprintf(buf + len, sz - len, 1003 "\nPhy%d Tx power table (channel %d)\n", 1004 phy != &dev->phy, phy->mt76->chandef.chan->hw_value); 1005 len += scnprintf(buf + len, sz - len, "%-16s %6s %6s %6s %6s\n", 1006 " ", "1m", "2m", "5m", "11m"); 1007 mt7915_txpower_puts(CCK, SKU_CCK); 1008 1009 len += scnprintf(buf + len, sz - len, 1010 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1011 " ", "6m", "9m", "12m", "18m", "24m", "36m", "48m", 1012 "54m"); 1013 mt7915_txpower_puts(OFDM, SKU_OFDM); 1014 1015 len += scnprintf(buf + len, sz - len, 1016 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1017 " ", "mcs0", "mcs1", "mcs2", "mcs3", "mcs4", 1018 "mcs5", "mcs6", "mcs7"); 1019 mt7915_txpower_puts(HT20, SKU_HT_BW20); 1020 1021 len += scnprintf(buf + len, sz - len, 1022 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1023 " ", "mcs0", "mcs1", "mcs2", "mcs3", "mcs4", "mcs5", 1024 "mcs6", "mcs7", "mcs32"); 1025 mt7915_txpower_puts(HT40, SKU_HT_BW40); 1026 1027 len += scnprintf(buf + len, sz - len, 1028 "%-16s %6s %6s %6s %6s %6s %6s %6s %6s %6s %6s %6s %6s\n", 1029 " ", "mcs0", "mcs1", "mcs2", "mcs3", "mcs4", "mcs5", 1030 "mcs6", "mcs7", "mcs8", "mcs9", "mcs10", "mcs11"); 1031 mt7915_txpower_puts(VHT20, SKU_VHT_BW20); 1032 mt7915_txpower_puts(VHT40, SKU_VHT_BW40); 1033 mt7915_txpower_puts(VHT80, SKU_VHT_BW80); 1034 mt7915_txpower_puts(VHT160, SKU_VHT_BW160); 1035 mt7915_txpower_puts(HE26, SKU_HE_RU26); 1036 mt7915_txpower_puts(HE52, SKU_HE_RU52); 1037 mt7915_txpower_puts(HE106, SKU_HE_RU106); 1038 mt7915_txpower_puts(HE242, SKU_HE_RU242); 1039 mt7915_txpower_puts(HE484, SKU_HE_RU484); 1040 mt7915_txpower_puts(HE996, SKU_HE_RU996); 1041 mt7915_txpower_puts(HE996x2, SKU_HE_RU2x996); 1042 1043 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_TPC_CTRL_STAT(band) : 1044 MT_WF_PHY_TPC_CTRL_STAT_MT7916(band); 1045 1046 len += scnprintf(buf + len, sz - len, "\nTx power (bbp) : %6ld\n", 1047 mt76_get_field(dev, reg, MT_WF_PHY_TPC_POWER)); 1048 1049 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 1050 1051 out: 1052 kfree(buf); 1053 return ret; 1054 } 1055 1056 static ssize_t 1057 mt7915_rate_txpower_set(struct file *file, const char __user *user_buf, 1058 size_t count, loff_t *ppos) 1059 { 1060 struct mt7915_phy *phy = file->private_data; 1061 struct mt7915_dev *dev = phy->dev; 1062 struct mt76_phy *mphy = phy->mt76; 1063 struct mt7915_mcu_txpower_sku req = { 1064 .format_id = TX_POWER_LIMIT_TABLE, 1065 .band_idx = phy->mt76->band_idx, 1066 }; 1067 char buf[100]; 1068 int i, ret, pwr160 = 0, pwr80 = 0, pwr40 = 0, pwr20 = 0; 1069 enum mac80211_rx_encoding mode; 1070 u32 offs = 0, len = 0; 1071 1072 if (count >= sizeof(buf)) 1073 return -EINVAL; 1074 1075 if (copy_from_user(buf, user_buf, count)) 1076 return -EFAULT; 1077 1078 if (count && buf[count - 1] == '\n') 1079 buf[count - 1] = '\0'; 1080 else 1081 buf[count] = '\0'; 1082 1083 if (sscanf(buf, "%u %u %u %u %u", 1084 &mode, &pwr160, &pwr80, &pwr40, &pwr20) != 5) { 1085 dev_warn(dev->mt76.dev, 1086 "per bandwidth power limit: Mode BW160 BW80 BW40 BW20"); 1087 return -EINVAL; 1088 } 1089 1090 if (mode > RX_ENC_HE) 1091 return -EINVAL; 1092 1093 if (pwr160) 1094 pwr160 = mt7915_get_power_bound(phy, pwr160); 1095 if (pwr80) 1096 pwr80 = mt7915_get_power_bound(phy, pwr80); 1097 if (pwr40) 1098 pwr40 = mt7915_get_power_bound(phy, pwr40); 1099 if (pwr20) 1100 pwr20 = mt7915_get_power_bound(phy, pwr20); 1101 1102 if (pwr160 < 0 || pwr80 < 0 || pwr40 < 0 || pwr20 < 0) 1103 return -EINVAL; 1104 1105 mutex_lock(&dev->mt76.mutex); 1106 ret = mt7915_mcu_get_txpower_sku(phy, req.txpower_sku, 1107 sizeof(req.txpower_sku)); 1108 if (ret) 1109 goto out; 1110 1111 mt7915_txpower_sets(SKU_CCK, pwr20, RX_ENC_LEGACY); 1112 mt7915_txpower_sets(SKU_OFDM, pwr20, RX_ENC_LEGACY); 1113 if (mode == RX_ENC_LEGACY) 1114 goto skip; 1115 1116 mt7915_txpower_sets(SKU_HT_BW20, pwr20, RX_ENC_HT); 1117 mt7915_txpower_sets(SKU_HT_BW40, pwr40, RX_ENC_HT); 1118 if (mode == RX_ENC_HT) 1119 goto skip; 1120 1121 mt7915_txpower_sets(SKU_VHT_BW20, pwr20, RX_ENC_VHT); 1122 mt7915_txpower_sets(SKU_VHT_BW40, pwr40, RX_ENC_VHT); 1123 mt7915_txpower_sets(SKU_VHT_BW80, pwr80, RX_ENC_VHT); 1124 mt7915_txpower_sets(SKU_VHT_BW160, pwr160, RX_ENC_VHT); 1125 if (mode == RX_ENC_VHT) 1126 goto skip; 1127 1128 mt7915_txpower_sets(SKU_HE_RU26, pwr20, RX_ENC_HE + 1); 1129 mt7915_txpower_sets(SKU_HE_RU52, pwr20, RX_ENC_HE + 1); 1130 mt7915_txpower_sets(SKU_HE_RU106, pwr20, RX_ENC_HE + 1); 1131 mt7915_txpower_sets(SKU_HE_RU242, pwr20, RX_ENC_HE); 1132 mt7915_txpower_sets(SKU_HE_RU484, pwr40, RX_ENC_HE); 1133 mt7915_txpower_sets(SKU_HE_RU996, pwr80, RX_ENC_HE); 1134 mt7915_txpower_sets(SKU_HE_RU2x996, pwr160, RX_ENC_HE); 1135 skip: 1136 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 1137 &req, sizeof(req), true); 1138 if (ret) 1139 goto out; 1140 1141 mphy->txpower_cur = max(mphy->txpower_cur, 1142 max(pwr160, max(pwr80, max(pwr40, pwr20)))); 1143 out: 1144 mutex_unlock(&dev->mt76.mutex); 1145 1146 return ret ? ret : count; 1147 } 1148 1149 static const struct file_operations mt7915_rate_txpower_fops = { 1150 .write = mt7915_rate_txpower_set, 1151 .read = mt7915_rate_txpower_get, 1152 .open = simple_open, 1153 .owner = THIS_MODULE, 1154 .llseek = default_llseek, 1155 }; 1156 1157 static int 1158 mt7915_twt_stats(struct seq_file *s, void *data) 1159 { 1160 struct mt7915_dev *dev = dev_get_drvdata(s->private); 1161 struct mt7915_twt_flow *iter; 1162 1163 rcu_read_lock(); 1164 1165 seq_puts(s, " wcid | id | flags | exp | mantissa"); 1166 seq_puts(s, " | duration | tsf |\n"); 1167 list_for_each_entry_rcu(iter, &dev->twt_list, list) 1168 seq_printf(s, 1169 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", 1170 iter->wcid, iter->id, 1171 iter->sched ? 's' : 'u', 1172 iter->protection ? 'p' : '-', 1173 iter->trigger ? 't' : '-', 1174 iter->flowtype ? '-' : 'a', 1175 iter->exp, iter->mantissa, 1176 iter->duration, iter->tsf); 1177 1178 rcu_read_unlock(); 1179 1180 return 0; 1181 } 1182 1183 /* The index of RF registers use the generic regidx, combined with two parts: 1184 * WF selection [31:24] and offset [23:0]. 1185 */ 1186 static int 1187 mt7915_rf_regval_get(void *data, u64 *val) 1188 { 1189 struct mt7915_dev *dev = data; 1190 u32 regval; 1191 int ret; 1192 1193 ret = mt7915_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false); 1194 if (ret) 1195 return ret; 1196 1197 *val = regval; 1198 1199 return 0; 1200 } 1201 1202 static int 1203 mt7915_rf_regval_set(void *data, u64 val) 1204 { 1205 struct mt7915_dev *dev = data; 1206 u32 val32 = val; 1207 1208 return mt7915_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true); 1209 } 1210 1211 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7915_rf_regval_get, 1212 mt7915_rf_regval_set, "0x%08llx\n"); 1213 1214 int mt7915_init_debugfs(struct mt7915_phy *phy) 1215 { 1216 struct mt7915_dev *dev = phy->dev; 1217 bool ext_phy = phy != &dev->phy; 1218 struct dentry *dir; 1219 1220 dir = mt76_register_debugfs_fops(phy->mt76, NULL); 1221 if (!dir) 1222 return -ENOMEM; 1223 debugfs_create_file("muru_debug", 0600, dir, dev, &fops_muru_debug); 1224 debugfs_create_file("muru_stats", 0400, dir, phy, 1225 &mt7915_muru_stats_fops); 1226 debugfs_create_file("hw-queues", 0400, dir, phy, 1227 &mt7915_hw_queues_fops); 1228 debugfs_create_file("xmit-queues", 0400, dir, phy, 1229 &mt7915_xmit_queues_fops); 1230 debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops); 1231 debugfs_create_file("sys_recovery", 0600, dir, phy, 1232 &mt7915_sys_recovery_ops); 1233 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); 1234 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); 1235 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); 1236 debugfs_create_file("fw_util_wm", 0400, dir, dev, 1237 &mt7915_fw_util_wm_fops); 1238 debugfs_create_file("fw_util_wa", 0400, dir, dev, 1239 &mt7915_fw_util_wa_fops); 1240 debugfs_create_file("implicit_txbf", 0600, dir, dev, 1241 &fops_implicit_txbf); 1242 debugfs_create_file("txpower_sku", 0400, dir, phy, 1243 &mt7915_rate_txpower_fops); 1244 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, 1245 mt7915_twt_stats); 1246 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); 1247 1248 if (!dev->dbdc_support || phy->mt76->band_idx) { 1249 debugfs_create_u32("dfs_hw_pattern", 0400, dir, 1250 &dev->hw_pattern); 1251 debugfs_create_file("radar_trigger", 0200, dir, dev, 1252 &fops_radar_trigger); 1253 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, 1254 mt7915_rdd_monitor); 1255 } 1256 1257 if (!ext_phy) 1258 dev->debugfs_dir = dir; 1259 1260 return 0; 1261 } 1262 1263 static void 1264 mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen, 1265 const void *data, int len) 1266 { 1267 static DEFINE_SPINLOCK(lock); 1268 unsigned long flags; 1269 void *dest; 1270 1271 spin_lock_irqsave(&lock, flags); 1272 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); 1273 if (dest) { 1274 *(u32 *)dest = hdrlen + len; 1275 dest += 4; 1276 1277 if (hdrlen) { 1278 memcpy(dest, hdr, hdrlen); 1279 dest += hdrlen; 1280 } 1281 1282 memcpy(dest, data, len); 1283 relay_flush(dev->relay_fwlog); 1284 } 1285 spin_unlock_irqrestore(&lock, flags); 1286 } 1287 1288 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len) 1289 { 1290 struct { 1291 __le32 magic; 1292 __le32 timestamp; 1293 __le16 msg_type; 1294 __le16 len; 1295 } hdr = { 1296 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), 1297 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), 1298 }; 1299 1300 if (!dev->relay_fwlog) 1301 return; 1302 1303 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); 1304 hdr.len = *(__le16 *)data; 1305 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); 1306 } 1307 1308 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len) 1309 { 1310 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) 1311 return false; 1312 1313 if (dev->relay_fwlog) 1314 mt7915_debugfs_write_fwlog(dev, NULL, 0, data, len); 1315 1316 return true; 1317 } 1318 1319 #ifdef CONFIG_MAC80211_DEBUGFS 1320 /** per-station debugfs **/ 1321 1322 static ssize_t mt7915_sta_fixed_rate_set(struct file *file, 1323 const char __user *user_buf, 1324 size_t count, loff_t *ppos) 1325 { 1326 struct ieee80211_sta *sta = file->private_data; 1327 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 1328 struct mt7915_dev *dev = msta->vif->phy->dev; 1329 struct ieee80211_vif *vif; 1330 struct sta_phy phy = {}; 1331 char buf[100]; 1332 int ret; 1333 u32 field; 1334 u8 i, gi, he_ltf; 1335 1336 if (count >= sizeof(buf)) 1337 return -EINVAL; 1338 1339 if (copy_from_user(buf, user_buf, count)) 1340 return -EFAULT; 1341 1342 if (count && buf[count - 1] == '\n') 1343 buf[count - 1] = '\0'; 1344 else 1345 buf[count] = '\0'; 1346 1347 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 1348 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3 1349 * nss - vht: 1~4, he: 1~4, others: ignore 1350 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2 1351 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 1352 * ldpc - off: 0, on: 1 1353 * stbc - off: 0, on: 1 1354 * he_ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 1355 */ 1356 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hhu %hhu %hhu %hhu", 1357 &phy.type, &phy.bw, &phy.nss, &phy.mcs, &gi, 1358 &phy.ldpc, &phy.stbc, &he_ltf) != 8) { 1359 dev_warn(dev->mt76.dev, 1360 "format: Mode BW NSS MCS (HE)GI LDPC STBC HE_LTF\n"); 1361 field = RATE_PARAM_AUTO; 1362 goto out; 1363 } 1364 1365 phy.ldpc = (phy.bw || phy.ldpc) * GENMASK(2, 0); 1366 for (i = 0; i <= phy.bw; i++) { 1367 phy.sgi |= gi << (i << sta->deflink.he_cap.has_he); 1368 phy.he_ltf |= he_ltf << (i << sta->deflink.he_cap.has_he); 1369 } 1370 field = RATE_PARAM_FIXED; 1371 1372 out: 1373 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 1374 ret = mt7915_mcu_set_fixed_rate_ctrl(dev, vif, sta, &phy, field); 1375 if (ret) 1376 return -EFAULT; 1377 1378 return count; 1379 } 1380 1381 static const struct file_operations fops_fixed_rate = { 1382 .write = mt7915_sta_fixed_rate_set, 1383 .open = simple_open, 1384 .owner = THIS_MODULE, 1385 .llseek = default_llseek, 1386 }; 1387 1388 static int 1389 mt7915_queues_show(struct seq_file *s, void *data) 1390 { 1391 struct ieee80211_sta *sta = s->private; 1392 1393 mt7915_sta_hw_queue_read(s, sta); 1394 1395 return 0; 1396 } 1397 1398 DEFINE_SHOW_ATTRIBUTE(mt7915_queues); 1399 1400 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1401 struct ieee80211_sta *sta, struct dentry *dir) 1402 { 1403 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate); 1404 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7915_queues_fops); 1405 } 1406 1407 #endif 1408