1 /* 2 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "mt76x2u.h" 18 #include "eeprom.h" 19 20 static void mt76x2u_mac_reset_counters(struct mt76x02_dev *dev) 21 { 22 mt76_rr(dev, MT_RX_STAT_0); 23 mt76_rr(dev, MT_RX_STAT_1); 24 mt76_rr(dev, MT_RX_STAT_2); 25 mt76_rr(dev, MT_TX_STA_0); 26 mt76_rr(dev, MT_TX_STA_1); 27 mt76_rr(dev, MT_TX_STA_2); 28 } 29 30 static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev) 31 { 32 s8 offset = 0; 33 u16 eep_val; 34 35 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); 36 37 offset = eep_val & 0x7f; 38 if ((eep_val & 0xff) == 0xff) 39 offset = 0; 40 else if (eep_val & 0x80) 41 offset = 0 - offset; 42 43 eep_val >>= 8; 44 if (eep_val == 0x00 || eep_val == 0xff) { 45 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); 46 eep_val &= 0xff; 47 48 if (eep_val == 0x00 || eep_val == 0xff) 49 eep_val = 0x14; 50 } 51 52 eep_val &= 0x7f; 53 mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5), 54 MT_XO_CTRL5_C2_VAL, eep_val + offset); 55 mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL); 56 57 mt76_wr(dev, 0x504, 0x06000000); 58 mt76_wr(dev, 0x50c, 0x08800000); 59 mdelay(5); 60 mt76_wr(dev, 0x504, 0x0); 61 62 /* decrease SIFS from 16us to 13us */ 63 mt76_rmw_field(dev, MT_XIFS_TIME_CFG, 64 MT_XIFS_TIME_CFG_OFDM_SIFS, 0xd); 65 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, MT_BKOFF_SLOT_CFG_CC_DELAY, 1); 66 67 /* init fce */ 68 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 69 70 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); 71 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 72 case 0: 73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 74 break; 75 case 1: 76 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); 77 break; 78 default: 79 break; 80 } 81 } 82 83 int mt76x2u_mac_reset(struct mt76x02_dev *dev) 84 { 85 mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5)); 86 87 /* init pbf regs */ 88 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); 89 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); 90 91 mt76_write_mac_initvals(dev); 92 93 mt76_wr(dev, MT_TX_LINK_CFG, 0x1020); 94 mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13); 95 mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00); 96 97 mt76_wr(dev, MT_WMM_AIFSN, 0x2273); 98 mt76_wr(dev, MT_WMM_CWMIN, 0x2344); 99 mt76_wr(dev, MT_WMM_CWMAX, 0x34aa); 100 101 mt76_clear(dev, MT_MAC_SYS_CTRL, 102 MT_MAC_SYS_CTRL_RESET_CSR | 103 MT_MAC_SYS_CTRL_RESET_BBP); 104 105 if (is_mt7612(dev)) 106 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); 107 108 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); 109 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); 110 111 mt76x2u_mac_fixup_xtal(dev); 112 113 return 0; 114 } 115 116 int mt76x2u_mac_start(struct mt76x02_dev *dev) 117 { 118 mt76x2u_mac_reset_counters(dev); 119 120 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 121 mt76x02_wait_for_wpdma(&dev->mt76, 1000); 122 usleep_range(50, 100); 123 124 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); 125 126 mt76_wr(dev, MT_MAC_SYS_CTRL, 127 MT_MAC_SYS_CTRL_ENABLE_TX | 128 MT_MAC_SYS_CTRL_ENABLE_RX); 129 130 return 0; 131 } 132 133 int mt76x2u_mac_stop(struct mt76x02_dev *dev) 134 { 135 int i, count = 0, val; 136 bool stopped = false; 137 u32 rts_cfg; 138 139 if (test_bit(MT76_REMOVED, &dev->mt76.state)) 140 return -EIO; 141 142 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG); 143 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT); 144 145 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 146 mt76_clear(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); 147 148 /* wait tx dma to stop */ 149 for (i = 0; i < 2000; i++) { 150 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); 151 if (!(val & MT_USB_DMA_CFG_TX_BUSY) && i > 10) 152 break; 153 usleep_range(50, 100); 154 } 155 156 /* page count on TxQ */ 157 for (i = 0; i < 200; i++) { 158 if (!(mt76_rr(dev, 0x0438) & 0xffffffff) && 159 !(mt76_rr(dev, 0x0a30) & 0x000000ff) && 160 !(mt76_rr(dev, 0x0a34) & 0xff00ff00)) 161 break; 162 usleep_range(10, 20); 163 } 164 165 /* disable tx-rx */ 166 mt76_clear(dev, MT_MAC_SYS_CTRL, 167 MT_MAC_SYS_CTRL_ENABLE_RX | 168 MT_MAC_SYS_CTRL_ENABLE_TX); 169 170 /* Wait for MAC to become idle */ 171 for (i = 0; i < 1000; i++) { 172 if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) && 173 !mt76_rr(dev, MT_BBP(IBI, 12))) { 174 stopped = true; 175 break; 176 } 177 usleep_range(10, 20); 178 } 179 180 if (!stopped) { 181 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); 182 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); 183 184 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); 185 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); 186 } 187 188 /* page count on RxQ */ 189 for (i = 0; i < 200; i++) { 190 if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) && 191 !(mt76_rr(dev, 0x0a30) & 0xffffffff) && 192 !(mt76_rr(dev, 0x0a34) & 0xffffffff) && 193 ++count > 10) 194 break; 195 msleep(50); 196 } 197 198 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 2000)) 199 dev_warn(dev->mt76.dev, "MAC RX failed to stop\n"); 200 201 /* wait rx dma to stop */ 202 for (i = 0; i < 2000; i++) { 203 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); 204 if (!(val & MT_USB_DMA_CFG_RX_BUSY) && i > 10) 205 break; 206 usleep_range(50, 100); 207 } 208 209 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg); 210 211 return 0; 212 } 213