1 /* 2 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/delay.h> 18 19 #include "mt76x2u.h" 20 #include "../mt76x02_util.h" 21 #include "../mt76x02_phy.h" 22 #include "eeprom.h" 23 #include "../mt76x02_usb.h" 24 25 static void mt76x2u_init_dma(struct mt76x02_dev *dev) 26 { 27 u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); 28 29 val |= MT_USB_DMA_CFG_RX_DROP_OR_PAD | 30 MT_USB_DMA_CFG_RX_BULK_EN | 31 MT_USB_DMA_CFG_TX_BULK_EN; 32 33 /* disable AGGR_BULK_RX in order to receive one 34 * frame in each rx urb and avoid copies 35 */ 36 val &= ~MT_USB_DMA_CFG_RX_BULK_AGG_EN; 37 mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val); 38 } 39 40 static void mt76x2u_power_on_rf_patch(struct mt76x02_dev *dev) 41 { 42 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); 43 udelay(1); 44 45 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff); 46 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30); 47 48 mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f); 49 udelay(1); 50 51 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); 52 usleep_range(150, 200); 53 54 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16)); 55 usleep_range(50, 100); 56 57 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); 58 } 59 60 static void mt76x2u_power_on_rf(struct mt76x02_dev *dev, int unit) 61 { 62 int shift = unit ? 8 : 0; 63 u32 val = (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift; 64 65 /* Enable RF BG */ 66 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); 67 usleep_range(10, 20); 68 69 /* Enable RFDIG LDO/AFE/ABB/ADDA */ 70 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); 71 usleep_range(10, 20); 72 73 /* Switch RFDIG power to internal LDO */ 74 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift); 75 usleep_range(10, 20); 76 77 mt76x2u_power_on_rf_patch(dev); 78 79 mt76_set(dev, 0x530, 0xf); 80 } 81 82 static void mt76x2u_power_on(struct mt76x02_dev *dev) 83 { 84 u32 val; 85 86 /* Turn on WL MTCMOS */ 87 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 88 MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP); 89 90 val = MT_WLAN_MTC_CTRL_STATE_UP | 91 MT_WLAN_MTC_CTRL_PWR_ACK | 92 MT_WLAN_MTC_CTRL_PWR_ACK_S; 93 94 mt76_poll(dev, MT_VEND_ADDR(CFG, 0x148), val, val, 1000); 95 96 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0x7f << 16); 97 usleep_range(10, 20); 98 99 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24); 100 usleep_range(10, 20); 101 102 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24); 103 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xfff); 104 105 /* Turn on AD/DA power down */ 106 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3)); 107 108 /* WLAN function enable */ 109 mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0)); 110 111 /* Release BBP software reset */ 112 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18)); 113 114 mt76x2u_power_on_rf(dev, 0); 115 mt76x2u_power_on_rf(dev, 1); 116 } 117 118 static int mt76x2u_init_eeprom(struct mt76x02_dev *dev) 119 { 120 u32 val, i; 121 122 dev->mt76.eeprom.data = devm_kzalloc(dev->mt76.dev, 123 MT7612U_EEPROM_SIZE, 124 GFP_KERNEL); 125 dev->mt76.eeprom.size = MT7612U_EEPROM_SIZE; 126 if (!dev->mt76.eeprom.data) 127 return -ENOMEM; 128 129 for (i = 0; i + 4 <= MT7612U_EEPROM_SIZE; i += 4) { 130 val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i)); 131 put_unaligned_le32(val, dev->mt76.eeprom.data + i); 132 } 133 134 mt76x02_eeprom_parse_hw_cap(&dev->mt76); 135 return 0; 136 } 137 138 struct mt76x02_dev *mt76x2u_alloc_device(struct device *pdev) 139 { 140 static const struct mt76_driver_ops drv_ops = { 141 .tx_prepare_skb = mt76x02u_tx_prepare_skb, 142 .tx_complete_skb = mt76x02_tx_complete_skb, 143 .tx_status_data = mt76x02_tx_status_data, 144 .rx_skb = mt76x02_queue_rx_skb, 145 }; 146 struct mt76x02_dev *dev; 147 struct mt76_dev *mdev; 148 149 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2u_ops); 150 if (!mdev) 151 return NULL; 152 153 dev = container_of(mdev, struct mt76x02_dev, mt76); 154 mdev->dev = pdev; 155 mdev->drv = &drv_ops; 156 157 return dev; 158 } 159 160 static void mt76x2u_init_beacon_offsets(struct mt76x02_dev *dev) 161 { 162 mt76_wr(dev, MT_BCN_OFFSET(0), 0x18100800); 163 mt76_wr(dev, MT_BCN_OFFSET(1), 0x38302820); 164 mt76_wr(dev, MT_BCN_OFFSET(2), 0x58504840); 165 mt76_wr(dev, MT_BCN_OFFSET(3), 0x78706860); 166 } 167 168 int mt76x2u_init_hardware(struct mt76x02_dev *dev) 169 { 170 const struct mt76_wcid_addr addr = { 171 .macaddr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, 172 .ba_mask = 0, 173 }; 174 int i, err; 175 176 mt76x2_reset_wlan(dev, true); 177 mt76x2u_power_on(dev); 178 179 if (!mt76x02_wait_for_mac(&dev->mt76)) 180 return -ETIMEDOUT; 181 182 err = mt76x2u_mcu_fw_init(dev); 183 if (err < 0) 184 return err; 185 186 if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG, 187 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 188 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) 189 return -EIO; 190 191 /* wait for asic ready after fw load. */ 192 if (!mt76x02_wait_for_mac(&dev->mt76)) 193 return -ETIMEDOUT; 194 195 mt76_wr(dev, MT_HEADER_TRANS_CTRL_REG, 0); 196 mt76_wr(dev, MT_TSO_CTRL, 0); 197 198 mt76x2u_init_dma(dev); 199 200 err = mt76x2u_mcu_init(dev); 201 if (err < 0) 202 return err; 203 204 err = mt76x2u_mac_reset(dev); 205 if (err < 0) 206 return err; 207 208 mt76x02_mac_setaddr(&dev->mt76, 209 dev->mt76.eeprom.data + MT_EE_MAC_ADDR); 210 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 211 212 mt76x2u_init_beacon_offsets(dev); 213 214 if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) 215 return -ETIMEDOUT; 216 217 /* reset wcid table */ 218 for (i = 0; i < 254; i++) 219 mt76_wr_copy(dev, MT_WCID_ADDR(i), &addr, 220 sizeof(struct mt76_wcid_addr)); 221 222 /* reset shared key table and pairwise key table */ 223 for (i = 0; i < 4; i++) 224 mt76_wr(dev, MT_SKEY_MODE_BASE_0 + 4 * i, 0); 225 for (i = 0; i < 256; i++) 226 mt76_wr(dev, MT_WCID_ATTR(i), 1); 227 228 mt76_clear(dev, MT_BEACON_TIME_CFG, 229 MT_BEACON_TIME_CFG_TIMER_EN | 230 MT_BEACON_TIME_CFG_SYNC_MODE | 231 MT_BEACON_TIME_CFG_TBTT_EN | 232 MT_BEACON_TIME_CFG_BEACON_TX); 233 234 mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e); 235 mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x583f); 236 237 err = mt76x2_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0); 238 if (err < 0) 239 return err; 240 241 mt76x02_phy_set_rxpath(&dev->mt76); 242 mt76x02_phy_set_txdac(&dev->mt76); 243 244 return mt76x2u_mac_stop(dev); 245 } 246 247 int mt76x2u_register_device(struct mt76x02_dev *dev) 248 { 249 struct ieee80211_hw *hw = mt76_hw(dev); 250 struct wiphy *wiphy = hw->wiphy; 251 int err; 252 253 INIT_DELAYED_WORK(&dev->cal_work, mt76x2u_phy_calibrate); 254 mt76x2_init_device(dev); 255 256 err = mt76x2u_init_eeprom(dev); 257 if (err < 0) 258 return err; 259 260 err = mt76u_alloc_queues(&dev->mt76); 261 if (err < 0) 262 goto fail; 263 264 err = mt76u_mcu_init_rx(&dev->mt76); 265 if (err < 0) 266 goto fail; 267 268 err = mt76x2u_init_hardware(dev); 269 if (err < 0) 270 goto fail; 271 272 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 273 274 err = mt76_register_device(&dev->mt76, true, mt76x02_rates, 275 ARRAY_SIZE(mt76x02_rates)); 276 if (err) 277 goto fail; 278 279 /* check hw sg support in order to enable AMSDU */ 280 if (mt76u_check_sg(&dev->mt76)) 281 hw->max_tx_fragments = MT_SG_MAX_SIZE; 282 else 283 hw->max_tx_fragments = 1; 284 285 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); 286 287 mt76x2_init_debugfs(dev); 288 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband); 289 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband); 290 291 return 0; 292 293 fail: 294 mt76x2u_cleanup(dev); 295 return err; 296 } 297 298 void mt76x2u_stop_hw(struct mt76x02_dev *dev) 299 { 300 mt76u_stop_stat_wk(&dev->mt76); 301 cancel_delayed_work_sync(&dev->cal_work); 302 mt76x2u_mac_stop(dev); 303 } 304 305 void mt76x2u_cleanup(struct mt76x02_dev *dev) 306 { 307 mt76x02_mcu_set_radio_state(&dev->mt76, false, false); 308 mt76x2u_stop_hw(dev); 309 mt76u_queues_deinit(&dev->mt76); 310 mt76u_mcu_deinit(&dev->mt76); 311 } 312