1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/delay.h> 18 #include "mt76x2.h" 19 #include "eeprom.h" 20 #include "mcu.h" 21 22 static void 23 mt76x2_mac_pbf_init(struct mt76x02_dev *dev) 24 { 25 u32 val; 26 27 val = MT_PBF_SYS_CTRL_MCU_RESET | 28 MT_PBF_SYS_CTRL_DMA_RESET | 29 MT_PBF_SYS_CTRL_MAC_RESET | 30 MT_PBF_SYS_CTRL_PBF_RESET | 31 MT_PBF_SYS_CTRL_ASY_RESET; 32 33 mt76_set(dev, MT_PBF_SYS_CTRL, val); 34 mt76_clear(dev, MT_PBF_SYS_CTRL, val); 35 36 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); 37 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); 38 } 39 40 static void 41 mt76x2_fixup_xtal(struct mt76x02_dev *dev) 42 { 43 u16 eep_val; 44 s8 offset = 0; 45 46 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); 47 48 offset = eep_val & 0x7f; 49 if ((eep_val & 0xff) == 0xff) 50 offset = 0; 51 else if (eep_val & 0x80) 52 offset = 0 - offset; 53 54 eep_val >>= 8; 55 if (eep_val == 0x00 || eep_val == 0xff) { 56 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); 57 eep_val &= 0xff; 58 59 if (eep_val == 0x00 || eep_val == 0xff) 60 eep_val = 0x14; 61 } 62 63 eep_val &= 0x7f; 64 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset); 65 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); 66 67 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); 68 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 69 case 0: 70 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 71 break; 72 case 1: 73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); 74 break; 75 default: 76 break; 77 } 78 } 79 80 static int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard) 81 { 82 static const u8 null_addr[ETH_ALEN] = {}; 83 const u8 *macaddr = dev->mt76.macaddr; 84 u32 val; 85 int i, k; 86 87 if (!mt76x02_wait_for_mac(&dev->mt76)) 88 return -ETIMEDOUT; 89 90 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); 91 92 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | 93 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 94 MT_WPDMA_GLO_CFG_RX_DMA_EN | 95 MT_WPDMA_GLO_CFG_RX_DMA_BUSY | 96 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE); 97 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); 98 99 mt76_wr(dev, MT_WPDMA_GLO_CFG, val); 100 101 mt76x2_mac_pbf_init(dev); 102 mt76_write_mac_initvals(dev); 103 mt76x2_fixup_xtal(dev); 104 105 mt76_clear(dev, MT_MAC_SYS_CTRL, 106 MT_MAC_SYS_CTRL_RESET_CSR | 107 MT_MAC_SYS_CTRL_RESET_BBP); 108 109 if (is_mt7612(dev)) 110 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); 111 112 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); 113 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); 114 115 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); 116 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); 117 usleep_range(5000, 10000); 118 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); 119 120 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); 121 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 122 123 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr)); 124 mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4)); 125 126 mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(macaddr)); 127 mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(macaddr + 4) | 128 FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */ 129 MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT); 130 131 /* Fire a pre-TBTT interrupt 8 ms before TBTT */ 132 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT, 133 8 << 4); 134 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER, 135 MT_DFS_GP_INTERVAL); 136 mt76_wr(dev, MT_INT_TIMER_EN, 0); 137 138 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff); 139 if (!hard) 140 return 0; 141 142 for (i = 0; i < 256 / 32; i++) 143 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); 144 145 for (i = 0; i < 256; i++) 146 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 147 148 for (i = 0; i < MT_MAX_VIFS; i++) 149 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL); 150 151 for (i = 0; i < 16; i++) 152 for (k = 0; k < 4; k++) 153 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 154 155 for (i = 0; i < 8; i++) { 156 mt76x2_mac_set_bssid(dev, i, null_addr); 157 mt76x2_mac_set_beacon(dev, i, NULL); 158 } 159 160 for (i = 0; i < 16; i++) 161 mt76_rr(dev, MT_TX_STAT_FIFO); 162 163 mt76_wr(dev, MT_CH_TIME_CFG, 164 MT_CH_TIME_CFG_TIMER_EN | 165 MT_CH_TIME_CFG_TX_AS_BUSY | 166 MT_CH_TIME_CFG_RX_AS_BUSY | 167 MT_CH_TIME_CFG_NAV_AS_BUSY | 168 MT_CH_TIME_CFG_EIFS_AS_BUSY | 169 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1)); 170 171 mt76x02_set_beacon_offsets(dev); 172 173 mt76x2_set_tx_ackto(dev); 174 175 return 0; 176 } 177 178 int mt76x2_mac_start(struct mt76x02_dev *dev) 179 { 180 int i; 181 182 for (i = 0; i < 16; i++) 183 mt76_rr(dev, MT_TX_AGG_CNT(i)); 184 185 for (i = 0; i < 16; i++) 186 mt76_rr(dev, MT_TX_STAT_FIFO); 187 188 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats)); 189 mt76x02_mac_start(dev); 190 191 return 0; 192 } 193 194 void mt76x2_mac_resume(struct mt76x02_dev *dev) 195 { 196 mt76_wr(dev, MT_MAC_SYS_CTRL, 197 MT_MAC_SYS_CTRL_ENABLE_TX | 198 MT_MAC_SYS_CTRL_ENABLE_RX); 199 } 200 201 static void 202 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev) 203 { 204 mt76_set(dev, 0x10130, BIT(0) | BIT(16)); 205 udelay(1); 206 207 mt76_clear(dev, 0x1001c, 0xff); 208 mt76_set(dev, 0x1001c, 0x30); 209 210 mt76_wr(dev, 0x10014, 0x484f); 211 udelay(1); 212 213 mt76_set(dev, 0x10130, BIT(17)); 214 udelay(125); 215 216 mt76_clear(dev, 0x10130, BIT(16)); 217 udelay(50); 218 219 mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); 220 } 221 222 static void 223 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit) 224 { 225 int shift = unit ? 8 : 0; 226 227 /* Enable RF BG */ 228 mt76_set(dev, 0x10130, BIT(0) << shift); 229 udelay(10); 230 231 /* Enable RFDIG LDO/AFE/ABB/ADDA */ 232 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift); 233 udelay(10); 234 235 /* Switch RFDIG power to internal LDO */ 236 mt76_clear(dev, 0x10130, BIT(2) << shift); 237 udelay(10); 238 239 mt76x2_power_on_rf_patch(dev); 240 241 mt76_set(dev, 0x530, 0xf); 242 } 243 244 static void 245 mt76x2_power_on(struct mt76x02_dev *dev) 246 { 247 u32 val; 248 249 /* Turn on WL MTCMOS */ 250 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP); 251 252 val = MT_WLAN_MTC_CTRL_STATE_UP | 253 MT_WLAN_MTC_CTRL_PWR_ACK | 254 MT_WLAN_MTC_CTRL_PWR_ACK_S; 255 256 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000); 257 258 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16); 259 udelay(10); 260 261 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 262 udelay(10); 263 264 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 265 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff); 266 267 /* Turn on AD/DA power down */ 268 mt76_clear(dev, 0x11204, BIT(3)); 269 270 /* WLAN function enable */ 271 mt76_set(dev, 0x10080, BIT(0)); 272 273 /* Release BBP software reset */ 274 mt76_clear(dev, 0x10064, BIT(18)); 275 276 mt76x2_power_on_rf(dev, 0); 277 mt76x2_power_on_rf(dev, 1); 278 } 279 280 void mt76x2_set_tx_ackto(struct mt76x02_dev *dev) 281 { 282 u8 ackto, sifs, slottime = dev->slottime; 283 284 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 285 slottime += 3 * dev->coverage_class; 286 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, 287 MT_BKOFF_SLOT_CFG_SLOTTIME, slottime); 288 289 sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG, 290 MT_XIFS_TIME_CFG_OFDM_SIFS); 291 292 ackto = slottime + sifs; 293 mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG, 294 MT_TX_TIMEOUT_CFG_ACKTO, ackto); 295 } 296 297 int mt76x2_init_hardware(struct mt76x02_dev *dev) 298 { 299 int ret; 300 301 tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet, 302 (unsigned long) dev); 303 304 mt76x02_dma_disable(dev); 305 mt76x2_reset_wlan(dev, true); 306 mt76x2_power_on(dev); 307 308 ret = mt76x2_eeprom_init(dev); 309 if (ret) 310 return ret; 311 312 ret = mt76x2_mac_reset(dev, true); 313 if (ret) 314 return ret; 315 316 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 317 318 ret = mt76x02_dma_init(dev); 319 if (ret) 320 return ret; 321 322 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); 323 ret = mt76x2_mac_start(dev); 324 if (ret) 325 return ret; 326 327 ret = mt76x2_mcu_init(dev); 328 if (ret) 329 return ret; 330 331 mt76x2_mac_stop(dev, false); 332 333 return 0; 334 } 335 336 void mt76x2_stop_hardware(struct mt76x02_dev *dev) 337 { 338 cancel_delayed_work_sync(&dev->cal_work); 339 cancel_delayed_work_sync(&dev->mac_work); 340 mt76x02_mcu_set_radio_state(dev, false, true); 341 mt76x2_mac_stop(dev, false); 342 } 343 344 void mt76x2_cleanup(struct mt76x02_dev *dev) 345 { 346 tasklet_disable(&dev->dfs_pd.dfs_tasklet); 347 tasklet_disable(&dev->pre_tbtt_tasklet); 348 mt76x2_stop_hardware(dev); 349 mt76x02_dma_cleanup(dev); 350 mt76x02_mcu_cleanup(dev); 351 } 352 353 struct mt76x02_dev *mt76x2_alloc_device(struct device *pdev) 354 { 355 static const struct mt76_driver_ops drv_ops = { 356 .txwi_size = sizeof(struct mt76x02_txwi), 357 .update_survey = mt76x2_update_channel, 358 .tx_prepare_skb = mt76x02_tx_prepare_skb, 359 .tx_complete_skb = mt76x02_tx_complete_skb, 360 .rx_skb = mt76x02_queue_rx_skb, 361 .rx_poll_complete = mt76x02_rx_poll_complete, 362 .sta_ps = mt76x2_sta_ps, 363 }; 364 struct mt76x02_dev *dev; 365 struct mt76_dev *mdev; 366 367 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2_ops); 368 if (!mdev) 369 return NULL; 370 371 dev = container_of(mdev, struct mt76x02_dev, mt76); 372 mdev->dev = pdev; 373 mdev->drv = &drv_ops; 374 375 return dev; 376 } 377 378 static void mt76x2_regd_notifier(struct wiphy *wiphy, 379 struct regulatory_request *request) 380 { 381 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 382 struct mt76x02_dev *dev = hw->priv; 383 384 mt76x2_dfs_set_domain(dev, request->dfs_region); 385 } 386 387 static const struct ieee80211_iface_limit if_limits[] = { 388 { 389 .max = 1, 390 .types = BIT(NL80211_IFTYPE_ADHOC) 391 }, { 392 .max = 8, 393 .types = BIT(NL80211_IFTYPE_STATION) | 394 #ifdef CONFIG_MAC80211_MESH 395 BIT(NL80211_IFTYPE_MESH_POINT) | 396 #endif 397 BIT(NL80211_IFTYPE_AP) 398 }, 399 }; 400 401 static const struct ieee80211_iface_combination if_comb[] = { 402 { 403 .limits = if_limits, 404 .n_limits = ARRAY_SIZE(if_limits), 405 .max_interfaces = 8, 406 .num_different_channels = 1, 407 .beacon_int_infra_match = true, 408 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 409 BIT(NL80211_CHAN_WIDTH_20) | 410 BIT(NL80211_CHAN_WIDTH_40) | 411 BIT(NL80211_CHAN_WIDTH_80), 412 } 413 }; 414 415 static void mt76x2_led_set_config(struct mt76_dev *mt76, u8 delay_on, 416 u8 delay_off) 417 { 418 struct mt76x02_dev *dev = container_of(mt76, struct mt76x02_dev, 419 mt76); 420 u32 val; 421 422 val = MT_LED_STATUS_DURATION(0xff) | 423 MT_LED_STATUS_OFF(delay_off) | 424 MT_LED_STATUS_ON(delay_on); 425 426 mt76_wr(dev, MT_LED_S0(mt76->led_pin), val); 427 mt76_wr(dev, MT_LED_S1(mt76->led_pin), val); 428 429 val = MT_LED_CTRL_REPLAY(mt76->led_pin) | 430 MT_LED_CTRL_KICK(mt76->led_pin); 431 if (mt76->led_al) 432 val |= MT_LED_CTRL_POLARITY(mt76->led_pin); 433 mt76_wr(dev, MT_LED_CTRL, val); 434 } 435 436 static int mt76x2_led_set_blink(struct led_classdev *led_cdev, 437 unsigned long *delay_on, 438 unsigned long *delay_off) 439 { 440 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, 441 led_cdev); 442 u8 delta_on, delta_off; 443 444 delta_off = max_t(u8, *delay_off / 10, 1); 445 delta_on = max_t(u8, *delay_on / 10, 1); 446 447 mt76x2_led_set_config(mt76, delta_on, delta_off); 448 return 0; 449 } 450 451 static void mt76x2_led_set_brightness(struct led_classdev *led_cdev, 452 enum led_brightness brightness) 453 { 454 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, 455 led_cdev); 456 457 if (!brightness) 458 mt76x2_led_set_config(mt76, 0, 0xff); 459 else 460 mt76x2_led_set_config(mt76, 0xff, 0); 461 } 462 463 int mt76x2_register_device(struct mt76x02_dev *dev) 464 { 465 struct ieee80211_hw *hw = mt76_hw(dev); 466 struct wiphy *wiphy = hw->wiphy; 467 int i, ret; 468 469 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate); 470 INIT_DELAYED_WORK(&dev->mac_work, mt76x2_mac_work); 471 472 mt76x2_init_device(dev); 473 474 ret = mt76x2_init_hardware(dev); 475 if (ret) 476 return ret; 477 478 for (i = 0; i < ARRAY_SIZE(dev->macaddr_list); i++) { 479 u8 *addr = dev->macaddr_list[i].addr; 480 481 memcpy(addr, dev->mt76.macaddr, ETH_ALEN); 482 483 if (!i) 484 continue; 485 486 addr[0] |= BIT(1); 487 addr[0] ^= ((i - 1) << 2); 488 } 489 wiphy->addresses = dev->macaddr_list; 490 wiphy->n_addresses = ARRAY_SIZE(dev->macaddr_list); 491 492 wiphy->iface_combinations = if_comb; 493 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 494 495 wiphy->reg_notifier = mt76x2_regd_notifier; 496 497 wiphy->interface_modes = 498 BIT(NL80211_IFTYPE_STATION) | 499 BIT(NL80211_IFTYPE_AP) | 500 #ifdef CONFIG_MAC80211_MESH 501 BIT(NL80211_IFTYPE_MESH_POINT) | 502 #endif 503 BIT(NL80211_IFTYPE_ADHOC); 504 505 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 506 507 mt76x2_dfs_init_detector(dev); 508 509 /* init led callbacks */ 510 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 511 dev->mt76.led_cdev.brightness_set = mt76x2_led_set_brightness; 512 dev->mt76.led_cdev.blink_set = mt76x2_led_set_blink; 513 } 514 515 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 516 ARRAY_SIZE(mt76x02_rates)); 517 if (ret) 518 goto fail; 519 520 mt76x2_init_debugfs(dev); 521 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband); 522 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband); 523 524 return 0; 525 526 fail: 527 mt76x2_stop_hardware(dev); 528 return ret; 529 } 530 531 532