1 /*
2  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/delay.h>
18 #include "mt76x2.h"
19 #include "eeprom.h"
20 #include "mcu.h"
21 
22 static void
23 mt76x2_mac_pbf_init(struct mt76x02_dev *dev)
24 {
25 	u32 val;
26 
27 	val = MT_PBF_SYS_CTRL_MCU_RESET |
28 	      MT_PBF_SYS_CTRL_DMA_RESET |
29 	      MT_PBF_SYS_CTRL_MAC_RESET |
30 	      MT_PBF_SYS_CTRL_PBF_RESET |
31 	      MT_PBF_SYS_CTRL_ASY_RESET;
32 
33 	mt76_set(dev, MT_PBF_SYS_CTRL, val);
34 	mt76_clear(dev, MT_PBF_SYS_CTRL, val);
35 
36 	mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
37 	mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
38 }
39 
40 static void
41 mt76x2_fixup_xtal(struct mt76x02_dev *dev)
42 {
43 	u16 eep_val;
44 	s8 offset = 0;
45 
46 	eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
47 
48 	offset = eep_val & 0x7f;
49 	if ((eep_val & 0xff) == 0xff)
50 		offset = 0;
51 	else if (eep_val & 0x80)
52 		offset = 0 - offset;
53 
54 	eep_val >>= 8;
55 	if (eep_val == 0x00 || eep_val == 0xff) {
56 		eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
57 		eep_val &= 0xff;
58 
59 		if (eep_val == 0x00 || eep_val == 0xff)
60 			eep_val = 0x14;
61 	}
62 
63 	eep_val &= 0x7f;
64 	mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
65 	mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
66 
67 	eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
68 	switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
69 	case 0:
70 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
71 		break;
72 	case 1:
73 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
74 		break;
75 	default:
76 		break;
77 	}
78 }
79 
80 int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
81 {
82 	const u8 *macaddr = dev->mt76.macaddr;
83 	u32 val;
84 	int i, k;
85 
86 	if (!mt76x02_wait_for_mac(&dev->mt76))
87 		return -ETIMEDOUT;
88 
89 	val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
90 
91 	val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
92 		 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
93 		 MT_WPDMA_GLO_CFG_RX_DMA_EN |
94 		 MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
95 		 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
96 	val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
97 
98 	mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
99 
100 	mt76x2_mac_pbf_init(dev);
101 	mt76_write_mac_initvals(dev);
102 	mt76x2_fixup_xtal(dev);
103 
104 	mt76_clear(dev, MT_MAC_SYS_CTRL,
105 		   MT_MAC_SYS_CTRL_RESET_CSR |
106 		   MT_MAC_SYS_CTRL_RESET_BBP);
107 
108 	if (is_mt7612(dev))
109 		mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
110 
111 	mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
112 	mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
113 
114 	mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
115 	mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
116 	usleep_range(5000, 10000);
117 	mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
118 
119 	mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
120 	mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
121 
122 	mt76x02_mac_setaddr(dev, macaddr);
123 	mt76x02e_init_beacon_config(dev);
124 	if (!hard)
125 		return 0;
126 
127 	for (i = 0; i < 256 / 32; i++)
128 		mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
129 
130 	for (i = 0; i < 256; i++) {
131 		mt76x02_mac_wcid_setup(dev, i, 0, NULL);
132 		mt76_wr(dev, MT_WCID_TX_RATE(i), 0);
133 		mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0);
134 	}
135 
136 	for (i = 0; i < MT_MAX_VIFS; i++)
137 		mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
138 
139 	for (i = 0; i < 16; i++)
140 		for (k = 0; k < 4; k++)
141 			mt76x02_mac_shared_key_setup(dev, i, k, NULL);
142 
143 	for (i = 0; i < 16; i++)
144 		mt76_rr(dev, MT_TX_STAT_FIFO);
145 
146 	mt76_wr(dev, MT_CH_TIME_CFG,
147 		MT_CH_TIME_CFG_TIMER_EN |
148 		MT_CH_TIME_CFG_TX_AS_BUSY |
149 		MT_CH_TIME_CFG_RX_AS_BUSY |
150 		MT_CH_TIME_CFG_NAV_AS_BUSY |
151 		MT_CH_TIME_CFG_EIFS_AS_BUSY |
152 		MT_CH_CCA_RC_EN |
153 		FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
154 
155 	mt76x02_set_tx_ackto(dev);
156 
157 	return 0;
158 }
159 
160 int mt76x2_mac_start(struct mt76x02_dev *dev)
161 {
162 	int i;
163 
164 	for (i = 0; i < 16; i++)
165 		mt76_rr(dev, MT_TX_AGG_CNT(i));
166 
167 	for (i = 0; i < 16; i++)
168 		mt76_rr(dev, MT_TX_STAT_FIFO);
169 
170 	memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
171 	mt76x02_mac_start(dev);
172 
173 	return 0;
174 }
175 
176 static void
177 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev)
178 {
179 	mt76_set(dev, 0x10130, BIT(0) | BIT(16));
180 	udelay(1);
181 
182 	mt76_clear(dev, 0x1001c, 0xff);
183 	mt76_set(dev, 0x1001c, 0x30);
184 
185 	mt76_wr(dev, 0x10014, 0x484f);
186 	udelay(1);
187 
188 	mt76_set(dev, 0x10130, BIT(17));
189 	udelay(125);
190 
191 	mt76_clear(dev, 0x10130, BIT(16));
192 	udelay(50);
193 
194 	mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
195 }
196 
197 static void
198 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit)
199 {
200 	int shift = unit ? 8 : 0;
201 
202 	/* Enable RF BG */
203 	mt76_set(dev, 0x10130, BIT(0) << shift);
204 	udelay(10);
205 
206 	/* Enable RFDIG LDO/AFE/ABB/ADDA */
207 	mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
208 	udelay(10);
209 
210 	/* Switch RFDIG power to internal LDO */
211 	mt76_clear(dev, 0x10130, BIT(2) << shift);
212 	udelay(10);
213 
214 	mt76x2_power_on_rf_patch(dev);
215 
216 	mt76_set(dev, 0x530, 0xf);
217 }
218 
219 static void
220 mt76x2_power_on(struct mt76x02_dev *dev)
221 {
222 	u32 val;
223 
224 	/* Turn on WL MTCMOS */
225 	mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
226 
227 	val = MT_WLAN_MTC_CTRL_STATE_UP |
228 	      MT_WLAN_MTC_CTRL_PWR_ACK |
229 	      MT_WLAN_MTC_CTRL_PWR_ACK_S;
230 
231 	mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
232 
233 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
234 	udelay(10);
235 
236 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
237 	udelay(10);
238 
239 	mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
240 	mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
241 
242 	/* Turn on AD/DA power down */
243 	mt76_clear(dev, 0x11204, BIT(3));
244 
245 	/* WLAN function enable */
246 	mt76_set(dev, 0x10080, BIT(0));
247 
248 	/* Release BBP software reset */
249 	mt76_clear(dev, 0x10064, BIT(18));
250 
251 	mt76x2_power_on_rf(dev, 0);
252 	mt76x2_power_on_rf(dev, 1);
253 }
254 
255 static int mt76x2_init_hardware(struct mt76x02_dev *dev)
256 {
257 	int ret;
258 
259 	mt76x02_dma_disable(dev);
260 	mt76x2_reset_wlan(dev, true);
261 	mt76x2_power_on(dev);
262 
263 	ret = mt76x2_eeprom_init(dev);
264 	if (ret)
265 		return ret;
266 
267 	ret = mt76x2_mac_reset(dev, true);
268 	if (ret)
269 		return ret;
270 
271 	dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
272 
273 	ret = mt76x02_dma_init(dev);
274 	if (ret)
275 		return ret;
276 
277 	set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
278 	ret = mt76x2_mac_start(dev);
279 	if (ret)
280 		return ret;
281 
282 	ret = mt76x2_mcu_init(dev);
283 	if (ret)
284 		return ret;
285 
286 	mt76x2_mac_stop(dev, false);
287 
288 	return 0;
289 }
290 
291 void mt76x2_stop_hardware(struct mt76x02_dev *dev)
292 {
293 	cancel_delayed_work_sync(&dev->cal_work);
294 	cancel_delayed_work_sync(&dev->mt76.mac_work);
295 	cancel_delayed_work_sync(&dev->wdt_work);
296 	mt76x02_mcu_set_radio_state(dev, false);
297 	mt76x2_mac_stop(dev, false);
298 }
299 
300 void mt76x2_cleanup(struct mt76x02_dev *dev)
301 {
302 	tasklet_disable(&dev->dfs_pd.dfs_tasklet);
303 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
304 	mt76x2_stop_hardware(dev);
305 	mt76x02_dma_cleanup(dev);
306 	mt76x02_mcu_cleanup(dev);
307 }
308 
309 int mt76x2_register_device(struct mt76x02_dev *dev)
310 {
311 	int ret;
312 
313 	INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
314 
315 	mt76x02_init_device(dev);
316 
317 	ret = mt76x2_init_hardware(dev);
318 	if (ret)
319 		return ret;
320 
321 	mt76x02_config_mac_addr_list(dev);
322 
323 	ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
324 				   ARRAY_SIZE(mt76x02_rates));
325 	if (ret)
326 		goto fail;
327 
328 	mt76x02_init_debugfs(dev);
329 	mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
330 	mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
331 
332 	return 0;
333 
334 fail:
335 	mt76x2_stop_hardware(dev);
336 	return ret;
337 }
338 
339 
340