1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/delay.h> 18 #include "mt76x2.h" 19 #include "eeprom.h" 20 #include "mcu.h" 21 22 static void 23 mt76x2_mac_pbf_init(struct mt76x02_dev *dev) 24 { 25 u32 val; 26 27 val = MT_PBF_SYS_CTRL_MCU_RESET | 28 MT_PBF_SYS_CTRL_DMA_RESET | 29 MT_PBF_SYS_CTRL_MAC_RESET | 30 MT_PBF_SYS_CTRL_PBF_RESET | 31 MT_PBF_SYS_CTRL_ASY_RESET; 32 33 mt76_set(dev, MT_PBF_SYS_CTRL, val); 34 mt76_clear(dev, MT_PBF_SYS_CTRL, val); 35 36 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); 37 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); 38 } 39 40 static void 41 mt76x2_fixup_xtal(struct mt76x02_dev *dev) 42 { 43 u16 eep_val; 44 s8 offset = 0; 45 46 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); 47 48 offset = eep_val & 0x7f; 49 if ((eep_val & 0xff) == 0xff) 50 offset = 0; 51 else if (eep_val & 0x80) 52 offset = 0 - offset; 53 54 eep_val >>= 8; 55 if (eep_val == 0x00 || eep_val == 0xff) { 56 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); 57 eep_val &= 0xff; 58 59 if (eep_val == 0x00 || eep_val == 0xff) 60 eep_val = 0x14; 61 } 62 63 eep_val &= 0x7f; 64 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset); 65 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); 66 67 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); 68 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 69 case 0: 70 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 71 break; 72 case 1: 73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); 74 break; 75 default: 76 break; 77 } 78 } 79 80 static int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard) 81 { 82 const u8 *macaddr = dev->mt76.macaddr; 83 u32 val; 84 int i, k; 85 86 if (!mt76x02_wait_for_mac(&dev->mt76)) 87 return -ETIMEDOUT; 88 89 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); 90 91 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | 92 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 93 MT_WPDMA_GLO_CFG_RX_DMA_EN | 94 MT_WPDMA_GLO_CFG_RX_DMA_BUSY | 95 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE); 96 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); 97 98 mt76_wr(dev, MT_WPDMA_GLO_CFG, val); 99 100 mt76x2_mac_pbf_init(dev); 101 mt76_write_mac_initvals(dev); 102 mt76x2_fixup_xtal(dev); 103 104 mt76_clear(dev, MT_MAC_SYS_CTRL, 105 MT_MAC_SYS_CTRL_RESET_CSR | 106 MT_MAC_SYS_CTRL_RESET_BBP); 107 108 if (is_mt7612(dev)) 109 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); 110 111 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); 112 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); 113 114 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); 115 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); 116 usleep_range(5000, 10000); 117 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); 118 119 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); 120 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 121 122 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr)); 123 mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4)); 124 125 mt76x02_init_beacon_config(dev); 126 if (!hard) 127 return 0; 128 129 for (i = 0; i < 256 / 32; i++) 130 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); 131 132 for (i = 0; i < 256; i++) { 133 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 134 mt76_wr(dev, MT_WCID_TX_RATE(i), 0); 135 mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0); 136 } 137 138 for (i = 0; i < MT_MAX_VIFS; i++) 139 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL); 140 141 for (i = 0; i < 16; i++) 142 for (k = 0; k < 4; k++) 143 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 144 145 for (i = 0; i < 16; i++) 146 mt76_rr(dev, MT_TX_STAT_FIFO); 147 148 mt76_wr(dev, MT_CH_TIME_CFG, 149 MT_CH_TIME_CFG_TIMER_EN | 150 MT_CH_TIME_CFG_TX_AS_BUSY | 151 MT_CH_TIME_CFG_RX_AS_BUSY | 152 MT_CH_TIME_CFG_NAV_AS_BUSY | 153 MT_CH_TIME_CFG_EIFS_AS_BUSY | 154 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1)); 155 156 mt76x02_set_tx_ackto(dev); 157 158 return 0; 159 } 160 161 int mt76x2_mac_start(struct mt76x02_dev *dev) 162 { 163 int i; 164 165 for (i = 0; i < 16; i++) 166 mt76_rr(dev, MT_TX_AGG_CNT(i)); 167 168 for (i = 0; i < 16; i++) 169 mt76_rr(dev, MT_TX_STAT_FIFO); 170 171 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats)); 172 mt76x02_mac_start(dev); 173 174 return 0; 175 } 176 177 void mt76x2_mac_resume(struct mt76x02_dev *dev) 178 { 179 mt76_wr(dev, MT_MAC_SYS_CTRL, 180 MT_MAC_SYS_CTRL_ENABLE_TX | 181 MT_MAC_SYS_CTRL_ENABLE_RX); 182 } 183 184 static void 185 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev) 186 { 187 mt76_set(dev, 0x10130, BIT(0) | BIT(16)); 188 udelay(1); 189 190 mt76_clear(dev, 0x1001c, 0xff); 191 mt76_set(dev, 0x1001c, 0x30); 192 193 mt76_wr(dev, 0x10014, 0x484f); 194 udelay(1); 195 196 mt76_set(dev, 0x10130, BIT(17)); 197 udelay(125); 198 199 mt76_clear(dev, 0x10130, BIT(16)); 200 udelay(50); 201 202 mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); 203 } 204 205 static void 206 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit) 207 { 208 int shift = unit ? 8 : 0; 209 210 /* Enable RF BG */ 211 mt76_set(dev, 0x10130, BIT(0) << shift); 212 udelay(10); 213 214 /* Enable RFDIG LDO/AFE/ABB/ADDA */ 215 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift); 216 udelay(10); 217 218 /* Switch RFDIG power to internal LDO */ 219 mt76_clear(dev, 0x10130, BIT(2) << shift); 220 udelay(10); 221 222 mt76x2_power_on_rf_patch(dev); 223 224 mt76_set(dev, 0x530, 0xf); 225 } 226 227 static void 228 mt76x2_power_on(struct mt76x02_dev *dev) 229 { 230 u32 val; 231 232 /* Turn on WL MTCMOS */ 233 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP); 234 235 val = MT_WLAN_MTC_CTRL_STATE_UP | 236 MT_WLAN_MTC_CTRL_PWR_ACK | 237 MT_WLAN_MTC_CTRL_PWR_ACK_S; 238 239 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000); 240 241 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16); 242 udelay(10); 243 244 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 245 udelay(10); 246 247 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 248 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff); 249 250 /* Turn on AD/DA power down */ 251 mt76_clear(dev, 0x11204, BIT(3)); 252 253 /* WLAN function enable */ 254 mt76_set(dev, 0x10080, BIT(0)); 255 256 /* Release BBP software reset */ 257 mt76_clear(dev, 0x10064, BIT(18)); 258 259 mt76x2_power_on_rf(dev, 0); 260 mt76x2_power_on_rf(dev, 1); 261 } 262 263 int mt76x2_init_hardware(struct mt76x02_dev *dev) 264 { 265 int ret; 266 267 mt76x02_dma_disable(dev); 268 mt76x2_reset_wlan(dev, true); 269 mt76x2_power_on(dev); 270 271 ret = mt76x2_eeprom_init(dev); 272 if (ret) 273 return ret; 274 275 ret = mt76x2_mac_reset(dev, true); 276 if (ret) 277 return ret; 278 279 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 280 281 ret = mt76x02_dma_init(dev); 282 if (ret) 283 return ret; 284 285 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); 286 ret = mt76x2_mac_start(dev); 287 if (ret) 288 return ret; 289 290 ret = mt76x2_mcu_init(dev); 291 if (ret) 292 return ret; 293 294 mt76x2_mac_stop(dev, false); 295 296 return 0; 297 } 298 299 void mt76x2_stop_hardware(struct mt76x02_dev *dev) 300 { 301 cancel_delayed_work_sync(&dev->cal_work); 302 cancel_delayed_work_sync(&dev->mac_work); 303 mt76x02_mcu_set_radio_state(dev, false); 304 mt76x2_mac_stop(dev, false); 305 } 306 307 void mt76x2_cleanup(struct mt76x02_dev *dev) 308 { 309 tasklet_disable(&dev->dfs_pd.dfs_tasklet); 310 tasklet_disable(&dev->pre_tbtt_tasklet); 311 mt76x2_stop_hardware(dev); 312 mt76x02_dma_cleanup(dev); 313 mt76x02_mcu_cleanup(dev); 314 } 315 316 struct mt76x02_dev *mt76x2_alloc_device(struct device *pdev) 317 { 318 static const struct mt76_driver_ops drv_ops = { 319 .txwi_size = sizeof(struct mt76x02_txwi), 320 .update_survey = mt76x02_update_channel, 321 .tx_prepare_skb = mt76x02_tx_prepare_skb, 322 .tx_complete_skb = mt76x02_tx_complete_skb, 323 .rx_skb = mt76x02_queue_rx_skb, 324 .rx_poll_complete = mt76x02_rx_poll_complete, 325 .sta_ps = mt76x02_sta_ps, 326 .sta_add = mt76x02_sta_add, 327 .sta_remove = mt76x02_sta_remove, 328 }; 329 struct mt76x02_dev *dev; 330 struct mt76_dev *mdev; 331 332 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2_ops); 333 if (!mdev) 334 return NULL; 335 336 dev = container_of(mdev, struct mt76x02_dev, mt76); 337 mdev->dev = pdev; 338 mdev->drv = &drv_ops; 339 340 return dev; 341 } 342 343 static void mt76x2_led_set_config(struct mt76_dev *mt76, u8 delay_on, 344 u8 delay_off) 345 { 346 struct mt76x02_dev *dev = container_of(mt76, struct mt76x02_dev, 347 mt76); 348 u32 val; 349 350 val = MT_LED_STATUS_DURATION(0xff) | 351 MT_LED_STATUS_OFF(delay_off) | 352 MT_LED_STATUS_ON(delay_on); 353 354 mt76_wr(dev, MT_LED_S0(mt76->led_pin), val); 355 mt76_wr(dev, MT_LED_S1(mt76->led_pin), val); 356 357 val = MT_LED_CTRL_REPLAY(mt76->led_pin) | 358 MT_LED_CTRL_KICK(mt76->led_pin); 359 if (mt76->led_al) 360 val |= MT_LED_CTRL_POLARITY(mt76->led_pin); 361 mt76_wr(dev, MT_LED_CTRL, val); 362 } 363 364 static int mt76x2_led_set_blink(struct led_classdev *led_cdev, 365 unsigned long *delay_on, 366 unsigned long *delay_off) 367 { 368 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, 369 led_cdev); 370 u8 delta_on, delta_off; 371 372 delta_off = max_t(u8, *delay_off / 10, 1); 373 delta_on = max_t(u8, *delay_on / 10, 1); 374 375 mt76x2_led_set_config(mt76, delta_on, delta_off); 376 return 0; 377 } 378 379 static void mt76x2_led_set_brightness(struct led_classdev *led_cdev, 380 enum led_brightness brightness) 381 { 382 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, 383 led_cdev); 384 385 if (!brightness) 386 mt76x2_led_set_config(mt76, 0, 0xff); 387 else 388 mt76x2_led_set_config(mt76, 0xff, 0); 389 } 390 391 int mt76x2_register_device(struct mt76x02_dev *dev) 392 { 393 int ret; 394 395 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate); 396 397 mt76x02_init_device(dev); 398 399 ret = mt76x2_init_hardware(dev); 400 if (ret) 401 return ret; 402 403 mt76x02_config_mac_addr_list(dev); 404 405 /* init led callbacks */ 406 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 407 dev->mt76.led_cdev.brightness_set = mt76x2_led_set_brightness; 408 dev->mt76.led_cdev.blink_set = mt76x2_led_set_blink; 409 } 410 411 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 412 ARRAY_SIZE(mt76x02_rates)); 413 if (ret) 414 goto fail; 415 416 mt76x02_init_debugfs(dev); 417 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband); 418 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband); 419 420 return 0; 421 422 fail: 423 mt76x2_stop_hardware(dev); 424 return ret; 425 } 426 427 428