1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/kernel.h> 19 20 #include "mt76x02.h" 21 #include "mt76x02_phy.h" 22 23 void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev) 24 { 25 u32 val; 26 27 val = mt76_rr(dev, MT_BBP(AGC, 0)); 28 val &= ~BIT(4); 29 30 switch (dev->mt76.chainmask & 0xf) { 31 case 2: 32 val |= BIT(3); 33 break; 34 default: 35 val &= ~BIT(3); 36 break; 37 } 38 39 mt76_wr(dev, MT_BBP(AGC, 0), val); 40 mb(); 41 val = mt76_rr(dev, MT_BBP(AGC, 0)); 42 } 43 EXPORT_SYMBOL_GPL(mt76x02_phy_set_rxpath); 44 45 void mt76x02_phy_set_txdac(struct mt76x02_dev *dev) 46 { 47 int txpath; 48 49 txpath = (dev->mt76.chainmask >> 8) & 0xf; 50 switch (txpath) { 51 case 2: 52 mt76_set(dev, MT_BBP(TXBE, 5), 0x3); 53 break; 54 default: 55 mt76_clear(dev, MT_BBP(TXBE, 5), 0x3); 56 break; 57 } 58 } 59 EXPORT_SYMBOL_GPL(mt76x02_phy_set_txdac); 60 61 static u32 62 mt76x02_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4) 63 { 64 u32 val = 0; 65 66 val |= (v1 & (BIT(6) - 1)) << 0; 67 val |= (v2 & (BIT(6) - 1)) << 8; 68 val |= (v3 & (BIT(6) - 1)) << 16; 69 val |= (v4 & (BIT(6) - 1)) << 24; 70 return val; 71 } 72 73 int mt76x02_get_max_rate_power(struct mt76_rate_power *r) 74 { 75 s8 ret = 0; 76 int i; 77 78 for (i = 0; i < sizeof(r->all); i++) 79 ret = max(ret, r->all[i]); 80 81 return ret; 82 } 83 EXPORT_SYMBOL_GPL(mt76x02_get_max_rate_power); 84 85 void mt76x02_limit_rate_power(struct mt76_rate_power *r, int limit) 86 { 87 int i; 88 89 for (i = 0; i < sizeof(r->all); i++) 90 if (r->all[i] > limit) 91 r->all[i] = limit; 92 } 93 EXPORT_SYMBOL_GPL(mt76x02_limit_rate_power); 94 95 void mt76x02_add_rate_power_offset(struct mt76_rate_power *r, int offset) 96 { 97 int i; 98 99 for (i = 0; i < sizeof(r->all); i++) 100 r->all[i] += offset; 101 } 102 EXPORT_SYMBOL_GPL(mt76x02_add_rate_power_offset); 103 104 void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1) 105 { 106 struct mt76_rate_power *t = &dev->mt76.rate_power; 107 108 mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0); 109 mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1); 110 111 mt76_wr(dev, MT_TX_PWR_CFG_0, 112 mt76x02_tx_power_mask(t->cck[0], t->cck[2], t->ofdm[0], 113 t->ofdm[2])); 114 mt76_wr(dev, MT_TX_PWR_CFG_1, 115 mt76x02_tx_power_mask(t->ofdm[4], t->ofdm[6], t->ht[0], 116 t->ht[2])); 117 mt76_wr(dev, MT_TX_PWR_CFG_2, 118 mt76x02_tx_power_mask(t->ht[4], t->ht[6], t->ht[8], 119 t->ht[10])); 120 mt76_wr(dev, MT_TX_PWR_CFG_3, 121 mt76x02_tx_power_mask(t->ht[12], t->ht[14], t->stbc[0], 122 t->stbc[2])); 123 mt76_wr(dev, MT_TX_PWR_CFG_4, 124 mt76x02_tx_power_mask(t->stbc[4], t->stbc[6], 0, 0)); 125 mt76_wr(dev, MT_TX_PWR_CFG_7, 126 mt76x02_tx_power_mask(t->ofdm[7], t->vht[8], t->ht[7], 127 t->vht[9])); 128 mt76_wr(dev, MT_TX_PWR_CFG_8, 129 mt76x02_tx_power_mask(t->ht[14], 0, t->vht[8], t->vht[9])); 130 mt76_wr(dev, MT_TX_PWR_CFG_9, 131 mt76x02_tx_power_mask(t->ht[7], 0, t->stbc[8], t->stbc[9])); 132 } 133 EXPORT_SYMBOL_GPL(mt76x02_phy_set_txpower); 134 135 int mt76x02_phy_get_min_avg_rssi(struct mt76x02_dev *dev) 136 { 137 struct mt76x02_sta *sta; 138 struct mt76_wcid *wcid; 139 int i, j, min_rssi = 0; 140 s8 cur_rssi; 141 142 local_bh_disable(); 143 rcu_read_lock(); 144 145 for (i = 0; i < ARRAY_SIZE(dev->mt76.wcid_mask); i++) { 146 unsigned long mask = dev->mt76.wcid_mask[i]; 147 148 if (!mask) 149 continue; 150 151 for (j = i * BITS_PER_LONG; mask; j++, mask >>= 1) { 152 if (!(mask & 1)) 153 continue; 154 155 wcid = rcu_dereference(dev->mt76.wcid[j]); 156 if (!wcid) 157 continue; 158 159 sta = container_of(wcid, struct mt76x02_sta, wcid); 160 spin_lock(&dev->mt76.rx_lock); 161 if (sta->inactive_count++ < 5) 162 cur_rssi = ewma_signal_read(&sta->rssi); 163 else 164 cur_rssi = 0; 165 spin_unlock(&dev->mt76.rx_lock); 166 167 if (cur_rssi < min_rssi) 168 min_rssi = cur_rssi; 169 } 170 } 171 172 rcu_read_unlock(); 173 local_bh_enable(); 174 175 if (!min_rssi) 176 return -75; 177 178 return min_rssi; 179 } 180 EXPORT_SYMBOL_GPL(mt76x02_phy_get_min_avg_rssi); 181 182 void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl) 183 { 184 int core_val, agc_val; 185 186 switch (width) { 187 case NL80211_CHAN_WIDTH_80: 188 core_val = 3; 189 agc_val = 7; 190 break; 191 case NL80211_CHAN_WIDTH_40: 192 core_val = 2; 193 agc_val = 3; 194 break; 195 default: 196 core_val = 0; 197 agc_val = 1; 198 break; 199 } 200 201 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val); 202 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val); 203 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl); 204 mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl); 205 } 206 EXPORT_SYMBOL_GPL(mt76x02_phy_set_bw); 207 208 void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band, 209 bool primary_upper) 210 { 211 switch (band) { 212 case NL80211_BAND_2GHZ: 213 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G); 214 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G); 215 break; 216 case NL80211_BAND_5GHZ: 217 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G); 218 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G); 219 break; 220 } 221 222 mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M, 223 primary_upper); 224 } 225 EXPORT_SYMBOL_GPL(mt76x02_phy_set_band); 226 227 bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev) 228 { 229 u8 limit = dev->cal.low_gain > 0 ? 16 : 4; 230 bool ret = false; 231 u32 false_cca; 232 233 false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS, mt76_rr(dev, MT_RX_STAT_1)); 234 dev->cal.false_cca = false_cca; 235 if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) { 236 dev->cal.agc_gain_adjust += 2; 237 ret = true; 238 } else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) || 239 (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) { 240 dev->cal.agc_gain_adjust -= 2; 241 ret = true; 242 } 243 244 return ret; 245 } 246 EXPORT_SYMBOL_GPL(mt76x02_phy_adjust_vga_gain); 247 248 void mt76x02_init_agc_gain(struct mt76x02_dev *dev) 249 { 250 dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8), 251 MT_BBP_AGC_GAIN); 252 dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9), 253 MT_BBP_AGC_GAIN); 254 memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init, 255 sizeof(dev->cal.agc_gain_cur)); 256 dev->cal.low_gain = -1; 257 dev->cal.gain_init_done = true; 258 } 259 EXPORT_SYMBOL_GPL(mt76x02_init_agc_gain); 260