1b9f192b8SLorenzo Bianconi /* 2b9f192b8SLorenzo Bianconi * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3b9f192b8SLorenzo Bianconi * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 4b9f192b8SLorenzo Bianconi * 5b9f192b8SLorenzo Bianconi * Permission to use, copy, modify, and/or distribute this software for any 6b9f192b8SLorenzo Bianconi * purpose with or without fee is hereby granted, provided that the above 7b9f192b8SLorenzo Bianconi * copyright notice and this permission notice appear in all copies. 8b9f192b8SLorenzo Bianconi * 9b9f192b8SLorenzo Bianconi * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10b9f192b8SLorenzo Bianconi * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11b9f192b8SLorenzo Bianconi * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12b9f192b8SLorenzo Bianconi * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13b9f192b8SLorenzo Bianconi * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14b9f192b8SLorenzo Bianconi * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15b9f192b8SLorenzo Bianconi * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16b9f192b8SLorenzo Bianconi */ 17b9f192b8SLorenzo Bianconi 18b9f192b8SLorenzo Bianconi #include <linux/kernel.h> 19b9f192b8SLorenzo Bianconi 20bfdff5d0SLorenzo Bianconi #include "mt76x02.h" 21b9f192b8SLorenzo Bianconi #include "mt76x02_phy.h" 22b9f192b8SLorenzo Bianconi 23bfdff5d0SLorenzo Bianconi void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev) 246034b2b0SLorenzo Bianconi { 256034b2b0SLorenzo Bianconi u32 val; 266034b2b0SLorenzo Bianconi 27bfdff5d0SLorenzo Bianconi val = mt76_rr(dev, MT_BBP(AGC, 0)); 286034b2b0SLorenzo Bianconi val &= ~BIT(4); 296034b2b0SLorenzo Bianconi 30bfdff5d0SLorenzo Bianconi switch (dev->mt76.chainmask & 0xf) { 316034b2b0SLorenzo Bianconi case 2: 326034b2b0SLorenzo Bianconi val |= BIT(3); 336034b2b0SLorenzo Bianconi break; 346034b2b0SLorenzo Bianconi default: 356034b2b0SLorenzo Bianconi val &= ~BIT(3); 366034b2b0SLorenzo Bianconi break; 376034b2b0SLorenzo Bianconi } 386034b2b0SLorenzo Bianconi 39bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_BBP(AGC, 0), val); 406034b2b0SLorenzo Bianconi mb(); 41bfdff5d0SLorenzo Bianconi val = mt76_rr(dev, MT_BBP(AGC, 0)); 426034b2b0SLorenzo Bianconi } 436034b2b0SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_phy_set_rxpath); 446034b2b0SLorenzo Bianconi 45bfdff5d0SLorenzo Bianconi void mt76x02_phy_set_txdac(struct mt76x02_dev *dev) 466034b2b0SLorenzo Bianconi { 476034b2b0SLorenzo Bianconi int txpath; 486034b2b0SLorenzo Bianconi 49bfdff5d0SLorenzo Bianconi txpath = (dev->mt76.chainmask >> 8) & 0xf; 506034b2b0SLorenzo Bianconi switch (txpath) { 516034b2b0SLorenzo Bianconi case 2: 52bfdff5d0SLorenzo Bianconi mt76_set(dev, MT_BBP(TXBE, 5), 0x3); 536034b2b0SLorenzo Bianconi break; 546034b2b0SLorenzo Bianconi default: 55bfdff5d0SLorenzo Bianconi mt76_clear(dev, MT_BBP(TXBE, 5), 0x3); 566034b2b0SLorenzo Bianconi break; 576034b2b0SLorenzo Bianconi } 586034b2b0SLorenzo Bianconi } 596034b2b0SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_phy_set_txdac); 606034b2b0SLorenzo Bianconi 61b9f192b8SLorenzo Bianconi static u32 62b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4) 63b9f192b8SLorenzo Bianconi { 64b9f192b8SLorenzo Bianconi u32 val = 0; 65b9f192b8SLorenzo Bianconi 66b9f192b8SLorenzo Bianconi val |= (v1 & (BIT(6) - 1)) << 0; 67b9f192b8SLorenzo Bianconi val |= (v2 & (BIT(6) - 1)) << 8; 68b9f192b8SLorenzo Bianconi val |= (v3 & (BIT(6) - 1)) << 16; 69b9f192b8SLorenzo Bianconi val |= (v4 & (BIT(6) - 1)) << 24; 70b9f192b8SLorenzo Bianconi return val; 71b9f192b8SLorenzo Bianconi } 72b9f192b8SLorenzo Bianconi 73b9f192b8SLorenzo Bianconi int mt76x02_get_max_rate_power(struct mt76_rate_power *r) 74b9f192b8SLorenzo Bianconi { 75b9f192b8SLorenzo Bianconi s8 ret = 0; 76b9f192b8SLorenzo Bianconi int i; 77b9f192b8SLorenzo Bianconi 78b9f192b8SLorenzo Bianconi for (i = 0; i < sizeof(r->all); i++) 79b9f192b8SLorenzo Bianconi ret = max(ret, r->all[i]); 80b9f192b8SLorenzo Bianconi 81b9f192b8SLorenzo Bianconi return ret; 82b9f192b8SLorenzo Bianconi } 83b9f192b8SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_get_max_rate_power); 84b9f192b8SLorenzo Bianconi 85b9f192b8SLorenzo Bianconi void mt76x02_limit_rate_power(struct mt76_rate_power *r, int limit) 86b9f192b8SLorenzo Bianconi { 87b9f192b8SLorenzo Bianconi int i; 88b9f192b8SLorenzo Bianconi 89b9f192b8SLorenzo Bianconi for (i = 0; i < sizeof(r->all); i++) 90b9f192b8SLorenzo Bianconi if (r->all[i] > limit) 91b9f192b8SLorenzo Bianconi r->all[i] = limit; 92b9f192b8SLorenzo Bianconi } 93b9f192b8SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_limit_rate_power); 94b9f192b8SLorenzo Bianconi 95b9f192b8SLorenzo Bianconi void mt76x02_add_rate_power_offset(struct mt76_rate_power *r, int offset) 96b9f192b8SLorenzo Bianconi { 97b9f192b8SLorenzo Bianconi int i; 98b9f192b8SLorenzo Bianconi 99b9f192b8SLorenzo Bianconi for (i = 0; i < sizeof(r->all); i++) 100b9f192b8SLorenzo Bianconi r->all[i] += offset; 101b9f192b8SLorenzo Bianconi } 102b9f192b8SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_add_rate_power_offset); 103b9f192b8SLorenzo Bianconi 104bfdff5d0SLorenzo Bianconi void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1) 105b9f192b8SLorenzo Bianconi { 106bfdff5d0SLorenzo Bianconi struct mt76_rate_power *t = &dev->mt76.rate_power; 107b9f192b8SLorenzo Bianconi 108bfdff5d0SLorenzo Bianconi mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0); 109bfdff5d0SLorenzo Bianconi mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1); 110b9f192b8SLorenzo Bianconi 111bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_0, 112b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->cck[0], t->cck[2], t->ofdm[0], 113b9f192b8SLorenzo Bianconi t->ofdm[2])); 114bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_1, 115b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->ofdm[4], t->ofdm[6], t->ht[0], 116b9f192b8SLorenzo Bianconi t->ht[2])); 117bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_2, 118b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->ht[4], t->ht[6], t->ht[8], 119b9f192b8SLorenzo Bianconi t->ht[10])); 120bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_3, 121b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->ht[12], t->ht[14], t->stbc[0], 122b9f192b8SLorenzo Bianconi t->stbc[2])); 123bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_4, 124b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->stbc[4], t->stbc[6], 0, 0)); 125bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_7, 126b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->ofdm[7], t->vht[8], t->ht[7], 127b9f192b8SLorenzo Bianconi t->vht[9])); 128bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_8, 129b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->ht[14], 0, t->vht[8], t->vht[9])); 130bfdff5d0SLorenzo Bianconi mt76_wr(dev, MT_TX_PWR_CFG_9, 131b9f192b8SLorenzo Bianconi mt76x02_tx_power_mask(t->ht[7], 0, t->stbc[8], t->stbc[9])); 132b9f192b8SLorenzo Bianconi } 133b9f192b8SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_phy_set_txpower); 13450b9e8d5SLorenzo Bianconi 135032c08f4SLorenzo Bianconi void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl) 136032c08f4SLorenzo Bianconi { 137032c08f4SLorenzo Bianconi int core_val, agc_val; 138032c08f4SLorenzo Bianconi 139032c08f4SLorenzo Bianconi switch (width) { 140032c08f4SLorenzo Bianconi case NL80211_CHAN_WIDTH_80: 141032c08f4SLorenzo Bianconi core_val = 3; 142032c08f4SLorenzo Bianconi agc_val = 7; 143032c08f4SLorenzo Bianconi break; 144032c08f4SLorenzo Bianconi case NL80211_CHAN_WIDTH_40: 145032c08f4SLorenzo Bianconi core_val = 2; 146032c08f4SLorenzo Bianconi agc_val = 3; 147032c08f4SLorenzo Bianconi break; 148032c08f4SLorenzo Bianconi default: 149032c08f4SLorenzo Bianconi core_val = 0; 150032c08f4SLorenzo Bianconi agc_val = 1; 151032c08f4SLorenzo Bianconi break; 152032c08f4SLorenzo Bianconi } 153032c08f4SLorenzo Bianconi 154032c08f4SLorenzo Bianconi mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val); 155032c08f4SLorenzo Bianconi mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val); 156032c08f4SLorenzo Bianconi mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl); 157032c08f4SLorenzo Bianconi mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl); 158032c08f4SLorenzo Bianconi } 159032c08f4SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_phy_set_bw); 160370c6415SLorenzo Bianconi 161370c6415SLorenzo Bianconi void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band, 162370c6415SLorenzo Bianconi bool primary_upper) 163370c6415SLorenzo Bianconi { 164370c6415SLorenzo Bianconi switch (band) { 165370c6415SLorenzo Bianconi case NL80211_BAND_2GHZ: 166370c6415SLorenzo Bianconi mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G); 167370c6415SLorenzo Bianconi mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G); 168370c6415SLorenzo Bianconi break; 169370c6415SLorenzo Bianconi case NL80211_BAND_5GHZ: 170370c6415SLorenzo Bianconi mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G); 171370c6415SLorenzo Bianconi mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G); 172370c6415SLorenzo Bianconi break; 173370c6415SLorenzo Bianconi } 174370c6415SLorenzo Bianconi 175370c6415SLorenzo Bianconi mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M, 176370c6415SLorenzo Bianconi primary_upper); 177370c6415SLorenzo Bianconi } 178370c6415SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_phy_set_band); 1799f884f0fSLorenzo Bianconi 1809f884f0fSLorenzo Bianconi bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev) 1819f884f0fSLorenzo Bianconi { 1829f884f0fSLorenzo Bianconi u8 limit = dev->cal.low_gain > 0 ? 16 : 4; 1839f884f0fSLorenzo Bianconi bool ret = false; 1849f884f0fSLorenzo Bianconi u32 false_cca; 1859f884f0fSLorenzo Bianconi 1869f884f0fSLorenzo Bianconi false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS, mt76_rr(dev, MT_RX_STAT_1)); 1879f884f0fSLorenzo Bianconi dev->cal.false_cca = false_cca; 1889f884f0fSLorenzo Bianconi if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) { 1899f884f0fSLorenzo Bianconi dev->cal.agc_gain_adjust += 2; 1909f884f0fSLorenzo Bianconi ret = true; 1919f884f0fSLorenzo Bianconi } else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) || 1929f884f0fSLorenzo Bianconi (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) { 1939f884f0fSLorenzo Bianconi dev->cal.agc_gain_adjust -= 2; 1949f884f0fSLorenzo Bianconi ret = true; 1959f884f0fSLorenzo Bianconi } 1969f884f0fSLorenzo Bianconi 197a0ac8061SFelix Fietkau dev->cal.agc_lowest_gain = dev->cal.agc_gain_adjust >= limit; 198a0ac8061SFelix Fietkau 1999f884f0fSLorenzo Bianconi return ret; 2009f884f0fSLorenzo Bianconi } 2019f884f0fSLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_phy_adjust_vga_gain); 202e48797e9SLorenzo Bianconi 203e48797e9SLorenzo Bianconi void mt76x02_init_agc_gain(struct mt76x02_dev *dev) 204e48797e9SLorenzo Bianconi { 205e48797e9SLorenzo Bianconi dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8), 206e48797e9SLorenzo Bianconi MT_BBP_AGC_GAIN); 207e48797e9SLorenzo Bianconi dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9), 208e48797e9SLorenzo Bianconi MT_BBP_AGC_GAIN); 209e48797e9SLorenzo Bianconi memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init, 210e48797e9SLorenzo Bianconi sizeof(dev->cal.agc_gain_cur)); 211e48797e9SLorenzo Bianconi dev->cal.low_gain = -1; 212f1b8ee35SStanislaw Gruszka dev->cal.gain_init_done = true; 213e48797e9SLorenzo Bianconi } 214e48797e9SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x02_init_agc_gain); 215