1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __MT76X02_MAC_H 19 #define __MT76X02_MAC_H 20 21 #include <linux/average.h> 22 23 struct mt76x02_dev; 24 25 struct mt76x02_tx_status { 26 u8 valid:1; 27 u8 success:1; 28 u8 aggr:1; 29 u8 ack_req:1; 30 u8 wcid; 31 u8 pktid; 32 u8 retry; 33 u16 rate; 34 } __packed __aligned(2); 35 36 #define MT_VIF_WCID(_n) (254 - ((_n) & 7)) 37 #define MT_MAX_VIFS 8 38 39 struct mt76x02_vif { 40 u8 idx; 41 42 struct mt76_wcid group_wcid; 43 }; 44 45 struct mt76x02_tx_info { 46 unsigned long jiffies; 47 u8 tries; 48 49 u8 wcid; 50 u8 pktid; 51 u8 retry; 52 }; 53 54 DECLARE_EWMA(signal, 10, 8); 55 56 struct mt76x02_sta { 57 struct mt76_wcid wcid; /* must be first */ 58 59 struct mt76x02_vif *vif; 60 struct mt76x02_tx_status status; 61 int n_frames; 62 63 struct ewma_signal rssi; 64 int inactive_count; 65 }; 66 67 #define MT_RXINFO_BA BIT(0) 68 #define MT_RXINFO_DATA BIT(1) 69 #define MT_RXINFO_NULL BIT(2) 70 #define MT_RXINFO_FRAG BIT(3) 71 #define MT_RXINFO_UNICAST BIT(4) 72 #define MT_RXINFO_MULTICAST BIT(5) 73 #define MT_RXINFO_BROADCAST BIT(6) 74 #define MT_RXINFO_MYBSS BIT(7) 75 #define MT_RXINFO_CRCERR BIT(8) 76 #define MT_RXINFO_ICVERR BIT(9) 77 #define MT_RXINFO_MICERR BIT(10) 78 #define MT_RXINFO_AMSDU BIT(11) 79 #define MT_RXINFO_HTC BIT(12) 80 #define MT_RXINFO_RSSI BIT(13) 81 #define MT_RXINFO_L2PAD BIT(14) 82 #define MT_RXINFO_AMPDU BIT(15) 83 #define MT_RXINFO_DECRYPT BIT(16) 84 #define MT_RXINFO_BSSIDX3 BIT(17) 85 #define MT_RXINFO_WAPI_KEY BIT(18) 86 #define MT_RXINFO_PN_LEN GENMASK(21, 19) 87 #define MT_RXINFO_SW_FTYPE0 BIT(22) 88 #define MT_RXINFO_SW_FTYPE1 BIT(23) 89 #define MT_RXINFO_PROBE_RESP BIT(24) 90 #define MT_RXINFO_BEACON BIT(25) 91 #define MT_RXINFO_DISASSOC BIT(26) 92 #define MT_RXINFO_DEAUTH BIT(27) 93 #define MT_RXINFO_ACTION BIT(28) 94 #define MT_RXINFO_TCP_SUM_ERR BIT(30) 95 #define MT_RXINFO_IP_SUM_ERR BIT(31) 96 97 #define MT_RXWI_CTL_WCID GENMASK(7, 0) 98 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) 99 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) 100 #define MT_RXWI_CTL_UDF GENMASK(15, 13) 101 #define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16) 102 #define MT_RXWI_CTL_EOF BIT(31) 103 104 #define MT_RXWI_TID GENMASK(3, 0) 105 #define MT_RXWI_SN GENMASK(15, 4) 106 107 #define MT_RXWI_RATE_INDEX GENMASK(5, 0) 108 #define MT_RXWI_RATE_LDPC BIT(6) 109 #define MT_RXWI_RATE_BW GENMASK(8, 7) 110 #define MT_RXWI_RATE_SGI BIT(9) 111 #define MT_RXWI_RATE_STBC BIT(10) 112 #define MT_RXWI_RATE_LDPC_EXSYM BIT(11) 113 #define MT_RXWI_RATE_PHY GENMASK(15, 13) 114 115 #define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0) 116 #define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4) 117 118 struct mt76x02_rxwi { 119 __le32 rxinfo; 120 121 __le32 ctl; 122 123 __le16 tid_sn; 124 __le16 rate; 125 126 u8 rssi[4]; 127 128 __le32 bbp_rxinfo[4]; 129 }; 130 131 #define MT_TX_PWR_ADJ GENMASK(3, 0) 132 133 enum mt76x2_phy_bandwidth { 134 MT_PHY_BW_20, 135 MT_PHY_BW_40, 136 MT_PHY_BW_80, 137 }; 138 139 #define MT_TXWI_FLAGS_FRAG BIT(0) 140 #define MT_TXWI_FLAGS_MMPS BIT(1) 141 #define MT_TXWI_FLAGS_CFACK BIT(2) 142 #define MT_TXWI_FLAGS_TS BIT(3) 143 #define MT_TXWI_FLAGS_AMPDU BIT(4) 144 #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) 145 #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) 146 #define MT_TXWI_FLAGS_NDPS BIT(10) 147 #define MT_TXWI_FLAGS_RTSBWSIG BIT(11) 148 #define MT_TXWI_FLAGS_NDP_BW GENMASK(13, 12) 149 #define MT_TXWI_FLAGS_SOUND BIT(14) 150 #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) 151 152 #define MT_TXWI_ACK_CTL_REQ BIT(0) 153 #define MT_TXWI_ACK_CTL_NSEQ BIT(1) 154 #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) 155 156 #define MT_TXWI_PKTID_PROBE BIT(7) 157 158 struct mt76x02_txwi { 159 __le16 flags; 160 __le16 rate; 161 u8 ack_ctl; 162 u8 wcid; 163 __le16 len_ctl; 164 __le32 iv; 165 __le32 eiv; 166 u8 aid; 167 u8 txstream; 168 u8 ctl2; 169 u8 pktid; 170 } __packed __aligned(4); 171 172 static inline bool mt76x02_wait_for_mac(struct mt76_dev *dev) 173 { 174 const u32 MAC_CSR0 = 0x1000; 175 int i; 176 177 for (i = 0; i < 500; i++) { 178 if (test_bit(MT76_REMOVED, &dev->state)) 179 return false; 180 181 switch (dev->bus->rr(dev, MAC_CSR0)) { 182 case 0: 183 case ~0: 184 break; 185 default: 186 return true; 187 } 188 usleep_range(5000, 10000); 189 } 190 return false; 191 } 192 193 static inline struct mt76x02_tx_info * 194 mt76x02_skb_tx_info(struct sk_buff *skb) 195 { 196 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 197 198 return (void *)info->status.status_driver_data; 199 } 200 201 void mt76x02_txq_init(struct mt76x02_dev *dev, struct ieee80211_txq *txq); 202 enum mt76x02_cipher_type 203 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data); 204 205 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 206 u8 key_idx, struct ieee80211_key_conf *key); 207 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 208 struct ieee80211_key_conf *key); 209 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx, 210 u8 *mac); 211 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop); 212 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 213 const struct ieee80211_tx_rate *rate); 214 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 215 struct mt76x02_tx_status *stat); 216 void mt76x02_send_tx_status(struct mt76x02_dev *dev, 217 struct mt76x02_tx_status *stat, u8 *update); 218 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 219 void *rxi); 220 int 221 mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate); 222 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, u8 *addr); 223 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 224 struct sk_buff *skb, struct mt76_wcid *wcid, 225 struct ieee80211_sta *sta, int len); 226 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq); 227 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 228 struct mt76_queue_entry *e, bool flush); 229 #endif 230