1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "mt76x02.h" 19 #include "mt76x02_trace.h" 20 21 static enum mt76x02_cipher_type 22 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 23 { 24 memset(key_data, 0, 32); 25 if (!key) 26 return MT_CIPHER_NONE; 27 28 if (key->keylen > 32) 29 return MT_CIPHER_NONE; 30 31 memcpy(key_data, key->key, key->keylen); 32 33 switch (key->cipher) { 34 case WLAN_CIPHER_SUITE_WEP40: 35 return MT_CIPHER_WEP40; 36 case WLAN_CIPHER_SUITE_WEP104: 37 return MT_CIPHER_WEP104; 38 case WLAN_CIPHER_SUITE_TKIP: 39 return MT_CIPHER_TKIP; 40 case WLAN_CIPHER_SUITE_CCMP: 41 return MT_CIPHER_AES_CCMP; 42 default: 43 return MT_CIPHER_NONE; 44 } 45 } 46 47 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 48 u8 key_idx, struct ieee80211_key_conf *key) 49 { 50 enum mt76x02_cipher_type cipher; 51 u8 key_data[32]; 52 u32 val; 53 54 cipher = mt76x02_mac_get_key_info(key, key_data); 55 if (cipher == MT_CIPHER_NONE && key) 56 return -EOPNOTSUPP; 57 58 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 59 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 60 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 61 mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 62 63 mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 64 sizeof(key_data)); 65 66 return 0; 67 } 68 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 69 70 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 71 struct ieee80211_key_conf *key) 72 { 73 enum mt76x02_cipher_type cipher; 74 u8 key_data[32]; 75 u8 iv_data[8]; 76 77 cipher = mt76x02_mac_get_key_info(key, key_data); 78 if (cipher == MT_CIPHER_NONE && key) 79 return -EOPNOTSUPP; 80 81 mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 82 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 83 84 memset(iv_data, 0, sizeof(iv_data)); 85 if (key) { 86 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 87 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 88 iv_data[3] = key->keyidx << 6; 89 if (cipher >= MT_CIPHER_TKIP) 90 iv_data[3] |= 0x20; 91 } 92 93 mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 94 95 return 0; 96 } 97 98 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, 99 u8 vif_idx, u8 *mac) 100 { 101 struct mt76_wcid_addr addr = {}; 102 u32 attr; 103 104 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 105 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 106 107 mt76_wr(dev, MT_WCID_ATTR(idx), attr); 108 109 if (idx >= 128) 110 return; 111 112 if (mac) 113 memcpy(addr.macaddr, mac, ETH_ALEN); 114 115 mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 116 } 117 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 118 119 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop) 120 { 121 u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); 122 u32 bit = MT_WCID_DROP_MASK(idx); 123 124 /* prevent unnecessary writes */ 125 if ((val & bit) != (bit * drop)) 126 mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 127 } 128 129 static __le16 130 mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev, 131 const struct ieee80211_tx_rate *rate, u8 *nss_val) 132 { 133 u16 rateval; 134 u8 phy, rate_idx; 135 u8 nss = 1; 136 u8 bw = 0; 137 138 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 139 rate_idx = rate->idx; 140 nss = 1 + (rate->idx >> 4); 141 phy = MT_PHY_TYPE_VHT; 142 if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 143 bw = 2; 144 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 145 bw = 1; 146 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 147 rate_idx = rate->idx; 148 nss = 1 + (rate->idx >> 3); 149 phy = MT_PHY_TYPE_HT; 150 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 151 phy = MT_PHY_TYPE_HT_GF; 152 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 153 bw = 1; 154 } else { 155 const struct ieee80211_rate *r; 156 int band = dev->mt76.chandef.chan->band; 157 u16 val; 158 159 r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx]; 160 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 161 val = r->hw_value_short; 162 else 163 val = r->hw_value; 164 165 phy = val >> 8; 166 rate_idx = val & 0xff; 167 bw = 0; 168 } 169 170 rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 171 rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 172 rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 173 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 174 rateval |= MT_RXWI_RATE_SGI; 175 176 *nss_val = nss; 177 return cpu_to_le16(rateval); 178 } 179 180 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 181 const struct ieee80211_tx_rate *rate) 182 { 183 spin_lock_bh(&dev->mt76.lock); 184 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 185 wcid->tx_rate_set = true; 186 spin_unlock_bh(&dev->mt76.lock); 187 } 188 189 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable) 190 { 191 if (enable) 192 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 193 else 194 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 195 } 196 197 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 198 struct mt76x02_tx_status *stat) 199 { 200 u32 stat1, stat2; 201 202 stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 203 stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); 204 205 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 206 if (!stat->valid) 207 return false; 208 209 stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 210 stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 211 stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 212 stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 213 stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 214 215 stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 216 stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 217 218 trace_mac_txstat_fetch(dev, stat); 219 220 return true; 221 } 222 223 static int 224 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 225 enum nl80211_band band) 226 { 227 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 228 229 txrate->idx = 0; 230 txrate->flags = 0; 231 txrate->count = 1; 232 233 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 234 case MT_PHY_TYPE_OFDM: 235 if (band == NL80211_BAND_2GHZ) 236 idx += 4; 237 238 txrate->idx = idx; 239 return 0; 240 case MT_PHY_TYPE_CCK: 241 if (idx >= 8) 242 idx -= 8; 243 244 txrate->idx = idx; 245 return 0; 246 case MT_PHY_TYPE_HT_GF: 247 txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 248 /* fall through */ 249 case MT_PHY_TYPE_HT: 250 txrate->flags |= IEEE80211_TX_RC_MCS; 251 txrate->idx = idx; 252 break; 253 case MT_PHY_TYPE_VHT: 254 txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 255 txrate->idx = idx; 256 break; 257 default: 258 return -EINVAL; 259 } 260 261 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 262 case MT_PHY_BW_20: 263 break; 264 case MT_PHY_BW_40: 265 txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 266 break; 267 case MT_PHY_BW_80: 268 txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 269 break; 270 default: 271 return -EINVAL; 272 } 273 274 if (rate & MT_RXWI_RATE_SGI) 275 txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 276 277 return 0; 278 } 279 280 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 281 struct sk_buff *skb, struct mt76_wcid *wcid, 282 struct ieee80211_sta *sta, int len) 283 { 284 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 285 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 286 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 287 struct ieee80211_key_conf *key = info->control.hw_key; 288 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 289 u16 txwi_flags = 0; 290 u8 nss; 291 s8 txpwr_adj, max_txpwr_adj; 292 u8 ccmp_pn[8], nstreams = dev->mt76.chainmask & 0xf; 293 294 memset(txwi, 0, sizeof(*txwi)); 295 296 if (wcid) 297 txwi->wcid = wcid->idx; 298 else 299 txwi->wcid = 0xff; 300 301 if (wcid && wcid->sw_iv && key) { 302 u64 pn = atomic64_inc_return(&key->tx_pn); 303 ccmp_pn[0] = pn; 304 ccmp_pn[1] = pn >> 8; 305 ccmp_pn[2] = 0; 306 ccmp_pn[3] = 0x20 | (key->keyidx << 6); 307 ccmp_pn[4] = pn >> 16; 308 ccmp_pn[5] = pn >> 24; 309 ccmp_pn[6] = pn >> 32; 310 ccmp_pn[7] = pn >> 40; 311 txwi->iv = *((__le32 *)&ccmp_pn[0]); 312 txwi->eiv = *((__le32 *)&ccmp_pn[1]); 313 } 314 315 spin_lock_bh(&dev->mt76.lock); 316 if (wcid && (rate->idx < 0 || !rate->count)) { 317 txwi->rate = wcid->tx_rate; 318 max_txpwr_adj = wcid->max_txpwr_adj; 319 nss = wcid->tx_rate_nss; 320 } else { 321 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 322 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 323 } 324 spin_unlock_bh(&dev->mt76.lock); 325 326 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->mt76.txpower_conf, 327 max_txpwr_adj); 328 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 329 330 if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4) 331 txwi->txstream = 0x13; 332 else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 && 333 !(txwi->rate & cpu_to_le16(rate_ht_mask))) 334 txwi->txstream = 0x93; 335 336 if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC)) 337 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 338 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 339 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 340 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC) 341 txwi_flags |= MT_TXWI_FLAGS_MMPS; 342 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 343 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 344 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 345 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 346 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 347 u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 348 349 ba_size <<= sta->ht_cap.ampdu_factor; 350 ba_size = min_t(int, 63, ba_size - 1); 351 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 352 ba_size = 0; 353 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 354 355 txwi_flags |= MT_TXWI_FLAGS_AMPDU | 356 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, 357 sta->ht_cap.ampdu_density); 358 } 359 360 if (ieee80211_is_probe_resp(hdr->frame_control) || 361 ieee80211_is_beacon(hdr->frame_control)) 362 txwi_flags |= MT_TXWI_FLAGS_TS; 363 364 txwi->flags |= cpu_to_le16(txwi_flags); 365 txwi->len_ctl = cpu_to_le16(len); 366 } 367 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 368 369 static void 370 mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, 371 struct ieee80211_tx_info *info, 372 struct mt76x02_tx_status *st, int n_frames) 373 { 374 struct ieee80211_tx_rate *rate = info->status.rates; 375 int cur_idx, last_rate; 376 int i; 377 378 if (!n_frames) 379 return; 380 381 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 382 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 383 dev->mt76.chandef.chan->band); 384 if (last_rate < IEEE80211_TX_MAX_RATES - 1) 385 rate[last_rate + 1].idx = -1; 386 387 cur_idx = rate[last_rate].idx + last_rate; 388 for (i = 0; i <= last_rate; i++) { 389 rate[i].flags = rate[last_rate].flags; 390 rate[i].idx = max_t(int, 0, cur_idx - i); 391 rate[i].count = 1; 392 } 393 rate[last_rate].count = st->retry + 1 - last_rate; 394 395 info->status.ampdu_len = n_frames; 396 info->status.ampdu_ack_len = st->success ? n_frames : 0; 397 398 if (st->aggr) 399 info->flags |= IEEE80211_TX_CTL_AMPDU | 400 IEEE80211_TX_STAT_AMPDU; 401 402 if (!st->ack_req) 403 info->flags |= IEEE80211_TX_CTL_NO_ACK; 404 else if (st->success) 405 info->flags |= IEEE80211_TX_STAT_ACK; 406 } 407 408 void mt76x02_send_tx_status(struct mt76x02_dev *dev, 409 struct mt76x02_tx_status *stat, u8 *update) 410 { 411 struct ieee80211_tx_info info = {}; 412 struct ieee80211_tx_status status = { 413 .info = &info 414 }; 415 struct mt76_wcid *wcid = NULL; 416 struct mt76x02_sta *msta = NULL; 417 struct mt76_dev *mdev = &dev->mt76; 418 struct sk_buff_head list; 419 420 if (stat->pktid == MT_PACKET_ID_NO_ACK) 421 return; 422 423 rcu_read_lock(); 424 mt76_tx_status_lock(mdev, &list); 425 426 if (stat->wcid < ARRAY_SIZE(dev->mt76.wcid)) 427 wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]); 428 429 if (wcid && wcid->sta) { 430 void *priv; 431 432 priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 433 status.sta = container_of(priv, struct ieee80211_sta, 434 drv_priv); 435 } 436 437 if (wcid) { 438 if (stat->pktid) 439 status.skb = mt76_tx_status_skb_get(mdev, wcid, 440 stat->pktid, &list); 441 if (status.skb) 442 status.info = IEEE80211_SKB_CB(status.skb); 443 } 444 445 if (msta && stat->aggr && !status.skb) { 446 u32 stat_val, stat_cache; 447 448 stat_val = stat->rate; 449 stat_val |= ((u32) stat->retry) << 16; 450 stat_cache = msta->status.rate; 451 stat_cache |= ((u32) msta->status.retry) << 16; 452 453 if (*update == 0 && stat_val == stat_cache && 454 stat->wcid == msta->status.wcid && msta->n_frames < 32) { 455 msta->n_frames++; 456 goto out; 457 } 458 459 mt76x02_mac_fill_tx_status(dev, status.info, &msta->status, 460 msta->n_frames); 461 462 msta->status = *stat; 463 msta->n_frames = 1; 464 *update = 0; 465 } else { 466 mt76x02_mac_fill_tx_status(dev, status.info, stat, 1); 467 *update = 1; 468 } 469 470 if (status.skb) 471 mt76_tx_status_skb_done(mdev, status.skb, &list); 472 else 473 ieee80211_tx_status_ext(mt76_hw(dev), &status); 474 475 out: 476 mt76_tx_status_unlock(mdev, &list); 477 rcu_read_unlock(); 478 } 479 480 static int 481 mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate) 482 { 483 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 484 485 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 486 case MT_PHY_TYPE_OFDM: 487 if (idx >= 8) 488 idx = 0; 489 490 if (status->band == NL80211_BAND_2GHZ) 491 idx += 4; 492 493 status->rate_idx = idx; 494 return 0; 495 case MT_PHY_TYPE_CCK: 496 if (idx >= 8) { 497 idx -= 8; 498 status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 499 } 500 501 if (idx >= 4) 502 idx = 0; 503 504 status->rate_idx = idx; 505 return 0; 506 case MT_PHY_TYPE_HT_GF: 507 status->enc_flags |= RX_ENC_FLAG_HT_GF; 508 /* fall through */ 509 case MT_PHY_TYPE_HT: 510 status->encoding = RX_ENC_HT; 511 status->rate_idx = idx; 512 break; 513 case MT_PHY_TYPE_VHT: 514 status->encoding = RX_ENC_VHT; 515 status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 516 status->nss = FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1; 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 if (rate & MT_RXWI_RATE_LDPC) 523 status->enc_flags |= RX_ENC_FLAG_LDPC; 524 525 if (rate & MT_RXWI_RATE_SGI) 526 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 527 528 if (rate & MT_RXWI_RATE_STBC) 529 status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 530 531 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 532 case MT_PHY_BW_20: 533 break; 534 case MT_PHY_BW_40: 535 status->bw = RATE_INFO_BW_40; 536 break; 537 case MT_PHY_BW_80: 538 status->bw = RATE_INFO_BW_80; 539 break; 540 default: 541 break; 542 } 543 544 return 0; 545 } 546 547 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, u8 *addr) 548 { 549 ether_addr_copy(dev->mt76.macaddr, addr); 550 551 if (!is_valid_ether_addr(dev->mt76.macaddr)) { 552 eth_random_addr(dev->mt76.macaddr); 553 dev_info(dev->mt76.dev, 554 "Invalid MAC address, using random address %pM\n", 555 dev->mt76.macaddr); 556 } 557 558 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr)); 559 mt76_wr(dev, MT_MAC_ADDR_DW1, 560 get_unaligned_le16(dev->mt76.macaddr + 4) | 561 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 562 } 563 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 564 565 static int 566 mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 567 { 568 struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 569 570 rssi += cal->rssi_offset[chain]; 571 rssi -= cal->lna_gain; 572 573 return rssi; 574 } 575 576 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 577 void *rxi) 578 { 579 struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb; 580 struct mt76x02_rxwi *rxwi = rxi; 581 struct mt76x02_sta *sta; 582 u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 583 u32 ctl = le32_to_cpu(rxwi->ctl); 584 u16 rate = le16_to_cpu(rxwi->rate); 585 u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 586 bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 587 int i, pad_len = 0, nstreams = dev->mt76.chainmask & 0xf; 588 s8 signal; 589 u8 pn_len; 590 u8 wcid; 591 int len; 592 593 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 594 return -EINVAL; 595 596 if (rxinfo & MT_RXINFO_L2PAD) 597 pad_len += 2; 598 599 if (rxinfo & MT_RXINFO_DECRYPT) { 600 status->flag |= RX_FLAG_DECRYPTED; 601 status->flag |= RX_FLAG_MMIC_STRIPPED; 602 status->flag |= RX_FLAG_MIC_STRIPPED; 603 status->flag |= RX_FLAG_IV_STRIPPED; 604 } 605 606 wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 607 sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 608 status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 609 610 len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 611 pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 612 if (pn_len) { 613 int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 614 u8 *data = skb->data + offset; 615 616 status->iv[0] = data[7]; 617 status->iv[1] = data[6]; 618 status->iv[2] = data[5]; 619 status->iv[3] = data[4]; 620 status->iv[4] = data[1]; 621 status->iv[5] = data[0]; 622 623 /* 624 * Driver CCMP validation can't deal with fragments. 625 * Let mac80211 take care of it. 626 */ 627 if (rxinfo & MT_RXINFO_FRAG) { 628 status->flag &= ~RX_FLAG_IV_STRIPPED; 629 } else { 630 pad_len += pn_len << 2; 631 len -= pn_len << 2; 632 } 633 } 634 635 mt76x02_remove_hdr_pad(skb, pad_len); 636 637 if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 638 status->aggr = true; 639 640 if (WARN_ON_ONCE(len > skb->len)) 641 return -EINVAL; 642 643 pskb_trim(skb, len); 644 645 status->chains = BIT(0); 646 signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 647 for (i = 1; i < nstreams; i++) { 648 status->chains |= BIT(i); 649 status->chain_signal[i] = mt76x02_mac_get_rssi(dev, 650 rxwi->rssi[i], 651 i); 652 signal = max_t(s8, signal, status->chain_signal[i]); 653 } 654 status->signal = signal; 655 status->freq = dev->mt76.chandef.chan->center_freq; 656 status->band = dev->mt76.chandef.chan->band; 657 658 status->tid = FIELD_GET(MT_RXWI_TID, tid_sn); 659 status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 660 661 if (sta) { 662 ewma_signal_add(&sta->rssi, status->signal); 663 sta->inactive_count = 0; 664 } 665 666 return mt76x02_mac_process_rate(status, rate); 667 } 668 669 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 670 { 671 struct mt76x02_tx_status stat = {}; 672 unsigned long flags; 673 u8 update = 1; 674 bool ret; 675 676 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 677 return; 678 679 trace_mac_txstat_poll(dev); 680 681 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 682 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 683 ret = mt76x02_mac_load_tx_status(dev, &stat); 684 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 685 686 if (!ret) 687 break; 688 689 if (!irq) { 690 mt76x02_send_tx_status(dev, &stat, &update); 691 continue; 692 } 693 694 kfifo_put(&dev->txstatus_fifo, stat); 695 } 696 } 697 698 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 699 struct mt76_queue_entry *e, bool flush) 700 { 701 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 702 struct mt76x02_txwi *txwi; 703 704 if (!e->txwi) { 705 dev_kfree_skb_any(e->skb); 706 return; 707 } 708 709 mt76x02_mac_poll_tx_status(dev, false); 710 711 txwi = (struct mt76x02_txwi *) &e->txwi->txwi; 712 trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid); 713 714 mt76_tx_complete_skb(mdev, e->skb); 715 } 716 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 717 718 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, u32 val) 719 { 720 u32 data = 0; 721 722 if (val != ~0) 723 data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) | 724 MT_PROT_CFG_RTS_THRESH; 725 726 mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); 727 728 mt76_rmw(dev, MT_CCK_PROT_CFG, 729 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 730 mt76_rmw(dev, MT_OFDM_PROT_CFG, 731 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 732 mt76_rmw(dev, MT_MM20_PROT_CFG, 733 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 734 mt76_rmw(dev, MT_MM40_PROT_CFG, 735 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 736 mt76_rmw(dev, MT_GF20_PROT_CFG, 737 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 738 mt76_rmw(dev, MT_GF40_PROT_CFG, 739 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 740 mt76_rmw(dev, MT_TX_PROT_CFG6, 741 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 742 mt76_rmw(dev, MT_TX_PROT_CFG7, 743 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 744 mt76_rmw(dev, MT_TX_PROT_CFG8, 745 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 746 } 747 748 void mt76x02_update_channel(struct mt76_dev *mdev) 749 { 750 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 751 struct mt76_channel_state *state; 752 u32 active, busy; 753 754 state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan); 755 756 busy = mt76_rr(dev, MT_CH_BUSY); 757 active = busy + mt76_rr(dev, MT_CH_IDLE); 758 759 spin_lock_bh(&dev->mt76.cc_lock); 760 state->cc_busy += busy; 761 state->cc_active += active; 762 spin_unlock_bh(&dev->mt76.cc_lock); 763 } 764 EXPORT_SYMBOL_GPL(mt76x02_update_channel); 765 766 static void mt76x02_check_mac_err(struct mt76x02_dev *dev) 767 { 768 u32 val = mt76_rr(dev, 0x10f4); 769 770 if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) 771 return; 772 773 dev_err(dev->mt76.dev, "mac specific condition occurred\n"); 774 775 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); 776 udelay(10); 777 mt76_clear(dev, MT_MAC_SYS_CTRL, 778 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 779 } 780 781 void mt76x02_mac_work(struct work_struct *work) 782 { 783 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 784 mac_work.work); 785 int i, idx; 786 787 mt76x02_update_channel(&dev->mt76); 788 for (i = 0, idx = 0; i < 16; i++) { 789 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 790 791 dev->aggr_stats[idx++] += val & 0xffff; 792 dev->aggr_stats[idx++] += val >> 16; 793 } 794 795 /* XXX: check beacon stuck for ap mode */ 796 if (!dev->beacon_mask) 797 mt76x02_check_mac_err(dev); 798 799 mt76_tx_status_check(&dev->mt76, NULL, false); 800 801 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work, 802 MT_CALIBRATE_INTERVAL); 803 } 804 805 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr) 806 { 807 idx &= 7; 808 mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr)); 809 mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR, 810 get_unaligned_le16(addr + 4)); 811 } 812 813 static int 814 mt76x02_write_beacon(struct mt76x02_dev *dev, int offset, struct sk_buff *skb) 815 { 816 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 817 struct mt76x02_txwi txwi; 818 819 if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi))) 820 return -ENOSPC; 821 822 mt76x02_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len); 823 824 mt76_wr_copy(dev, offset, &txwi, sizeof(txwi)); 825 offset += sizeof(txwi); 826 827 mt76_wr_copy(dev, offset, skb->data, skb->len); 828 return 0; 829 } 830 831 static int 832 __mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 bcn_idx, 833 struct sk_buff *skb) 834 { 835 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 836 int beacon_addr = mt76x02_beacon_offsets[bcn_idx]; 837 int ret = 0; 838 int i; 839 840 /* Prevent corrupt transmissions during update */ 841 mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx)); 842 843 if (skb) { 844 ret = mt76x02_write_beacon(dev, beacon_addr, skb); 845 if (!ret) 846 dev->beacon_data_mask |= BIT(bcn_idx); 847 } else { 848 dev->beacon_data_mask &= ~BIT(bcn_idx); 849 for (i = 0; i < beacon_len; i += 4) 850 mt76_wr(dev, beacon_addr + i, 0); 851 } 852 853 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask); 854 855 return ret; 856 } 857 858 int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx, 859 struct sk_buff *skb) 860 { 861 bool force_update = false; 862 int bcn_idx = 0; 863 int i; 864 865 for (i = 0; i < ARRAY_SIZE(dev->beacons); i++) { 866 if (vif_idx == i) { 867 force_update = !!dev->beacons[i] ^ !!skb; 868 869 if (dev->beacons[i]) 870 dev_kfree_skb(dev->beacons[i]); 871 872 dev->beacons[i] = skb; 873 __mt76x02_mac_set_beacon(dev, bcn_idx, skb); 874 } else if (force_update && dev->beacons[i]) { 875 __mt76x02_mac_set_beacon(dev, bcn_idx, 876 dev->beacons[i]); 877 } 878 879 bcn_idx += !!dev->beacons[i]; 880 } 881 882 for (i = bcn_idx; i < ARRAY_SIZE(dev->beacons); i++) { 883 if (!(dev->beacon_data_mask & BIT(i))) 884 break; 885 886 __mt76x02_mac_set_beacon(dev, i, NULL); 887 } 888 889 mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 890 bcn_idx - 1); 891 return 0; 892 } 893 894 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, 895 u8 vif_idx, bool val) 896 { 897 u8 old_mask = dev->beacon_mask; 898 bool en; 899 u32 reg; 900 901 if (val) { 902 dev->beacon_mask |= BIT(vif_idx); 903 } else { 904 dev->beacon_mask &= ~BIT(vif_idx); 905 mt76x02_mac_set_beacon(dev, vif_idx, NULL); 906 } 907 908 if (!!old_mask == !!dev->beacon_mask) 909 return; 910 911 en = dev->beacon_mask; 912 913 mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); 914 reg = MT_BEACON_TIME_CFG_BEACON_TX | 915 MT_BEACON_TIME_CFG_TBTT_EN | 916 MT_BEACON_TIME_CFG_TIMER_EN; 917 mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en); 918 919 if (en) 920 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 921 else 922 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 923 } 924