1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "mt76x02.h" 19 #include "mt76x02_trace.h" 20 21 static enum mt76x02_cipher_type 22 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 23 { 24 memset(key_data, 0, 32); 25 if (!key) 26 return MT_CIPHER_NONE; 27 28 if (key->keylen > 32) 29 return MT_CIPHER_NONE; 30 31 memcpy(key_data, key->key, key->keylen); 32 33 switch (key->cipher) { 34 case WLAN_CIPHER_SUITE_WEP40: 35 return MT_CIPHER_WEP40; 36 case WLAN_CIPHER_SUITE_WEP104: 37 return MT_CIPHER_WEP104; 38 case WLAN_CIPHER_SUITE_TKIP: 39 return MT_CIPHER_TKIP; 40 case WLAN_CIPHER_SUITE_CCMP: 41 return MT_CIPHER_AES_CCMP; 42 default: 43 return MT_CIPHER_NONE; 44 } 45 } 46 47 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 48 u8 key_idx, struct ieee80211_key_conf *key) 49 { 50 enum mt76x02_cipher_type cipher; 51 u8 key_data[32]; 52 u32 val; 53 54 cipher = mt76x02_mac_get_key_info(key, key_data); 55 if (cipher == MT_CIPHER_NONE && key) 56 return -EOPNOTSUPP; 57 58 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 59 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 60 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 61 mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 62 63 mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 64 sizeof(key_data)); 65 66 return 0; 67 } 68 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 69 70 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 71 struct ieee80211_key_conf *key) 72 { 73 enum mt76x02_cipher_type cipher; 74 u8 key_data[32]; 75 u8 iv_data[8]; 76 77 cipher = mt76x02_mac_get_key_info(key, key_data); 78 if (cipher == MT_CIPHER_NONE && key) 79 return -EOPNOTSUPP; 80 81 mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 82 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 83 84 memset(iv_data, 0, sizeof(iv_data)); 85 if (key) { 86 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 87 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 88 iv_data[3] = key->keyidx << 6; 89 if (cipher >= MT_CIPHER_TKIP) 90 iv_data[3] |= 0x20; 91 } 92 93 mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 94 95 return 0; 96 } 97 98 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, 99 u8 vif_idx, u8 *mac) 100 { 101 struct mt76_wcid_addr addr = {}; 102 u32 attr; 103 104 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 105 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 106 107 mt76_wr(dev, MT_WCID_ATTR(idx), attr); 108 109 if (idx >= 128) 110 return; 111 112 if (mac) 113 memcpy(addr.macaddr, mac, ETH_ALEN); 114 115 mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 116 } 117 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 118 119 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop) 120 { 121 u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); 122 u32 bit = MT_WCID_DROP_MASK(idx); 123 124 /* prevent unnecessary writes */ 125 if ((val & bit) != (bit * drop)) 126 mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 127 } 128 129 static __le16 130 mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev, 131 const struct ieee80211_tx_rate *rate, u8 *nss_val) 132 { 133 u8 phy, rate_idx, nss, bw = 0; 134 u16 rateval; 135 136 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 137 rate_idx = rate->idx; 138 nss = 1 + (rate->idx >> 4); 139 phy = MT_PHY_TYPE_VHT; 140 if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 141 bw = 2; 142 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 143 bw = 1; 144 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 145 rate_idx = rate->idx; 146 nss = 1 + (rate->idx >> 3); 147 phy = MT_PHY_TYPE_HT; 148 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 149 phy = MT_PHY_TYPE_HT_GF; 150 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 151 bw = 1; 152 } else { 153 const struct ieee80211_rate *r; 154 int band = dev->mt76.chandef.chan->band; 155 u16 val; 156 157 r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx]; 158 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 159 val = r->hw_value_short; 160 else 161 val = r->hw_value; 162 163 phy = val >> 8; 164 rate_idx = val & 0xff; 165 nss = 1; 166 } 167 168 rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 169 rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 170 rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 171 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 172 rateval |= MT_RXWI_RATE_SGI; 173 174 *nss_val = nss; 175 return cpu_to_le16(rateval); 176 } 177 178 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 179 const struct ieee80211_tx_rate *rate) 180 { 181 spin_lock_bh(&dev->mt76.lock); 182 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 183 wcid->tx_rate_set = true; 184 spin_unlock_bh(&dev->mt76.lock); 185 } 186 187 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable) 188 { 189 if (enable) 190 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 191 else 192 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 193 } 194 195 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 196 struct mt76x02_tx_status *stat) 197 { 198 u32 stat1, stat2; 199 200 stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 201 stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); 202 203 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 204 if (!stat->valid) 205 return false; 206 207 stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 208 stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 209 stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 210 stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 211 stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 212 213 stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 214 stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 215 216 trace_mac_txstat_fetch(dev, stat); 217 218 return true; 219 } 220 221 static int 222 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 223 enum nl80211_band band) 224 { 225 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 226 227 txrate->idx = 0; 228 txrate->flags = 0; 229 txrate->count = 1; 230 231 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 232 case MT_PHY_TYPE_OFDM: 233 if (band == NL80211_BAND_2GHZ) 234 idx += 4; 235 236 txrate->idx = idx; 237 return 0; 238 case MT_PHY_TYPE_CCK: 239 if (idx >= 8) 240 idx -= 8; 241 242 txrate->idx = idx; 243 return 0; 244 case MT_PHY_TYPE_HT_GF: 245 txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 246 /* fall through */ 247 case MT_PHY_TYPE_HT: 248 txrate->flags |= IEEE80211_TX_RC_MCS; 249 txrate->idx = idx; 250 break; 251 case MT_PHY_TYPE_VHT: 252 txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 253 txrate->idx = idx; 254 break; 255 default: 256 return -EINVAL; 257 } 258 259 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 260 case MT_PHY_BW_20: 261 break; 262 case MT_PHY_BW_40: 263 txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 264 break; 265 case MT_PHY_BW_80: 266 txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 267 break; 268 default: 269 return -EINVAL; 270 } 271 272 if (rate & MT_RXWI_RATE_SGI) 273 txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 274 275 return 0; 276 } 277 278 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 279 struct sk_buff *skb, struct mt76_wcid *wcid, 280 struct ieee80211_sta *sta, int len) 281 { 282 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 283 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 284 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 285 struct ieee80211_key_conf *key = info->control.hw_key; 286 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 287 u16 txwi_flags = 0; 288 u8 nss; 289 s8 txpwr_adj, max_txpwr_adj; 290 u8 ccmp_pn[8], nstreams = dev->mt76.chainmask & 0xf; 291 292 memset(txwi, 0, sizeof(*txwi)); 293 294 if (!info->control.hw_key && wcid && wcid->hw_key_idx != 0xff && 295 ieee80211_has_protected(hdr->frame_control)) { 296 wcid = NULL; 297 ieee80211_get_tx_rates(info->control.vif, sta, skb, 298 info->control.rates, 1); 299 } 300 301 if (wcid) 302 txwi->wcid = wcid->idx; 303 else 304 txwi->wcid = 0xff; 305 306 if (wcid && wcid->sw_iv && key) { 307 u64 pn = atomic64_inc_return(&key->tx_pn); 308 ccmp_pn[0] = pn; 309 ccmp_pn[1] = pn >> 8; 310 ccmp_pn[2] = 0; 311 ccmp_pn[3] = 0x20 | (key->keyidx << 6); 312 ccmp_pn[4] = pn >> 16; 313 ccmp_pn[5] = pn >> 24; 314 ccmp_pn[6] = pn >> 32; 315 ccmp_pn[7] = pn >> 40; 316 txwi->iv = *((__le32 *)&ccmp_pn[0]); 317 txwi->eiv = *((__le32 *)&ccmp_pn[4]); 318 } 319 320 spin_lock_bh(&dev->mt76.lock); 321 if (wcid && (rate->idx < 0 || !rate->count)) { 322 txwi->rate = wcid->tx_rate; 323 max_txpwr_adj = wcid->max_txpwr_adj; 324 nss = wcid->tx_rate_nss; 325 } else { 326 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 327 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 328 } 329 spin_unlock_bh(&dev->mt76.lock); 330 331 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->mt76.txpower_conf, 332 max_txpwr_adj); 333 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 334 335 if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4) 336 txwi->txstream = 0x13; 337 else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 && 338 !(txwi->rate & cpu_to_le16(rate_ht_mask))) 339 txwi->txstream = 0x93; 340 341 if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC)) 342 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 343 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 344 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 345 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC) 346 txwi_flags |= MT_TXWI_FLAGS_MMPS; 347 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 348 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 349 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 350 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 351 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 352 u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 353 354 ba_size <<= sta->ht_cap.ampdu_factor; 355 ba_size = min_t(int, 63, ba_size - 1); 356 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 357 ba_size = 0; 358 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 359 360 txwi_flags |= MT_TXWI_FLAGS_AMPDU | 361 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, 362 sta->ht_cap.ampdu_density); 363 } 364 365 if (ieee80211_is_probe_resp(hdr->frame_control) || 366 ieee80211_is_beacon(hdr->frame_control)) 367 txwi_flags |= MT_TXWI_FLAGS_TS; 368 369 txwi->flags |= cpu_to_le16(txwi_flags); 370 txwi->len_ctl = cpu_to_le16(len); 371 } 372 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 373 374 static void 375 mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, 376 struct ieee80211_tx_info *info, 377 struct mt76x02_tx_status *st, int n_frames) 378 { 379 struct ieee80211_tx_rate *rate = info->status.rates; 380 int cur_idx, last_rate; 381 int i; 382 383 if (!n_frames) 384 return; 385 386 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 387 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 388 dev->mt76.chandef.chan->band); 389 if (last_rate < IEEE80211_TX_MAX_RATES - 1) 390 rate[last_rate + 1].idx = -1; 391 392 cur_idx = rate[last_rate].idx + last_rate; 393 for (i = 0; i <= last_rate; i++) { 394 rate[i].flags = rate[last_rate].flags; 395 rate[i].idx = max_t(int, 0, cur_idx - i); 396 rate[i].count = 1; 397 } 398 rate[last_rate].count = st->retry + 1 - last_rate; 399 400 info->status.ampdu_len = n_frames; 401 info->status.ampdu_ack_len = st->success ? n_frames : 0; 402 403 if (st->aggr) 404 info->flags |= IEEE80211_TX_CTL_AMPDU | 405 IEEE80211_TX_STAT_AMPDU; 406 407 if (!st->ack_req) 408 info->flags |= IEEE80211_TX_CTL_NO_ACK; 409 else if (st->success) 410 info->flags |= IEEE80211_TX_STAT_ACK; 411 } 412 413 void mt76x02_send_tx_status(struct mt76x02_dev *dev, 414 struct mt76x02_tx_status *stat, u8 *update) 415 { 416 struct ieee80211_tx_info info = {}; 417 struct ieee80211_tx_status status = { 418 .info = &info 419 }; 420 struct mt76_wcid *wcid = NULL; 421 struct mt76x02_sta *msta = NULL; 422 struct mt76_dev *mdev = &dev->mt76; 423 struct sk_buff_head list; 424 425 if (stat->pktid == MT_PACKET_ID_NO_ACK) 426 return; 427 428 rcu_read_lock(); 429 mt76_tx_status_lock(mdev, &list); 430 431 if (stat->wcid < ARRAY_SIZE(dev->mt76.wcid)) 432 wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]); 433 434 if (wcid && wcid->sta) { 435 void *priv; 436 437 priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 438 status.sta = container_of(priv, struct ieee80211_sta, 439 drv_priv); 440 } 441 442 if (wcid) { 443 if (stat->pktid >= MT_PACKET_ID_FIRST) 444 status.skb = mt76_tx_status_skb_get(mdev, wcid, 445 stat->pktid, &list); 446 if (status.skb) 447 status.info = IEEE80211_SKB_CB(status.skb); 448 } 449 450 if (msta && stat->aggr && !status.skb) { 451 u32 stat_val, stat_cache; 452 453 stat_val = stat->rate; 454 stat_val |= ((u32) stat->retry) << 16; 455 stat_cache = msta->status.rate; 456 stat_cache |= ((u32) msta->status.retry) << 16; 457 458 if (*update == 0 && stat_val == stat_cache && 459 stat->wcid == msta->status.wcid && msta->n_frames < 32) { 460 msta->n_frames++; 461 goto out; 462 } 463 464 mt76x02_mac_fill_tx_status(dev, status.info, &msta->status, 465 msta->n_frames); 466 467 msta->status = *stat; 468 msta->n_frames = 1; 469 *update = 0; 470 } else { 471 mt76x02_mac_fill_tx_status(dev, status.info, stat, 1); 472 *update = 1; 473 } 474 475 if (status.skb) 476 mt76_tx_status_skb_done(mdev, status.skb, &list); 477 else 478 ieee80211_tx_status_ext(mt76_hw(dev), &status); 479 480 out: 481 mt76_tx_status_unlock(mdev, &list); 482 rcu_read_unlock(); 483 } 484 485 static int 486 mt76x02_mac_process_rate(struct mt76x02_dev *dev, 487 struct mt76_rx_status *status, 488 u16 rate) 489 { 490 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 491 492 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 493 case MT_PHY_TYPE_OFDM: 494 if (idx >= 8) 495 idx = 0; 496 497 if (status->band == NL80211_BAND_2GHZ) 498 idx += 4; 499 500 status->rate_idx = idx; 501 return 0; 502 case MT_PHY_TYPE_CCK: 503 if (idx >= 8) { 504 idx -= 8; 505 status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 506 } 507 508 if (idx >= 4) 509 idx = 0; 510 511 status->rate_idx = idx; 512 return 0; 513 case MT_PHY_TYPE_HT_GF: 514 status->enc_flags |= RX_ENC_FLAG_HT_GF; 515 /* fall through */ 516 case MT_PHY_TYPE_HT: 517 status->encoding = RX_ENC_HT; 518 status->rate_idx = idx; 519 break; 520 case MT_PHY_TYPE_VHT: { 521 u8 n_rxstream = dev->mt76.chainmask & 0xf; 522 523 status->encoding = RX_ENC_VHT; 524 status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 525 status->nss = min_t(u8, n_rxstream, 526 FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1); 527 break; 528 } 529 default: 530 return -EINVAL; 531 } 532 533 if (rate & MT_RXWI_RATE_LDPC) 534 status->enc_flags |= RX_ENC_FLAG_LDPC; 535 536 if (rate & MT_RXWI_RATE_SGI) 537 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 538 539 if (rate & MT_RXWI_RATE_STBC) 540 status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 541 542 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 543 case MT_PHY_BW_20: 544 break; 545 case MT_PHY_BW_40: 546 status->bw = RATE_INFO_BW_40; 547 break; 548 case MT_PHY_BW_80: 549 status->bw = RATE_INFO_BW_80; 550 break; 551 default: 552 break; 553 } 554 555 return 0; 556 } 557 558 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr) 559 { 560 static const u8 null_addr[ETH_ALEN] = {}; 561 int i; 562 563 ether_addr_copy(dev->mt76.macaddr, addr); 564 565 if (!is_valid_ether_addr(dev->mt76.macaddr)) { 566 eth_random_addr(dev->mt76.macaddr); 567 dev_info(dev->mt76.dev, 568 "Invalid MAC address, using random address %pM\n", 569 dev->mt76.macaddr); 570 } 571 572 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr)); 573 mt76_wr(dev, MT_MAC_ADDR_DW1, 574 get_unaligned_le16(dev->mt76.macaddr + 4) | 575 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 576 577 mt76_wr(dev, MT_MAC_BSSID_DW0, 578 get_unaligned_le32(dev->mt76.macaddr)); 579 mt76_wr(dev, MT_MAC_BSSID_DW1, 580 get_unaligned_le16(dev->mt76.macaddr + 4) | 581 FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 APs + 8 STAs */ 582 MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT); 583 584 for (i = 0; i < 16; i++) 585 mt76x02_mac_set_bssid(dev, i, null_addr); 586 } 587 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 588 589 static int 590 mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 591 { 592 struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 593 594 rssi += cal->rssi_offset[chain]; 595 rssi -= cal->lna_gain; 596 597 return rssi; 598 } 599 600 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 601 void *rxi) 602 { 603 struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb; 604 struct mt76x02_rxwi *rxwi = rxi; 605 struct mt76x02_sta *sta; 606 u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 607 u32 ctl = le32_to_cpu(rxwi->ctl); 608 u16 rate = le16_to_cpu(rxwi->rate); 609 u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 610 bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 611 int pad_len = 0, nstreams = dev->mt76.chainmask & 0xf; 612 s8 signal; 613 u8 pn_len; 614 u8 wcid; 615 int len; 616 617 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 618 return -EINVAL; 619 620 if (rxinfo & MT_RXINFO_L2PAD) 621 pad_len += 2; 622 623 if (rxinfo & MT_RXINFO_DECRYPT) { 624 status->flag |= RX_FLAG_DECRYPTED; 625 status->flag |= RX_FLAG_MMIC_STRIPPED; 626 status->flag |= RX_FLAG_MIC_STRIPPED; 627 status->flag |= RX_FLAG_IV_STRIPPED; 628 } 629 630 wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 631 sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 632 status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 633 634 len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 635 pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 636 if (pn_len) { 637 int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 638 u8 *data = skb->data + offset; 639 640 status->iv[0] = data[7]; 641 status->iv[1] = data[6]; 642 status->iv[2] = data[5]; 643 status->iv[3] = data[4]; 644 status->iv[4] = data[1]; 645 status->iv[5] = data[0]; 646 647 /* 648 * Driver CCMP validation can't deal with fragments. 649 * Let mac80211 take care of it. 650 */ 651 if (rxinfo & MT_RXINFO_FRAG) { 652 status->flag &= ~RX_FLAG_IV_STRIPPED; 653 } else { 654 pad_len += pn_len << 2; 655 len -= pn_len << 2; 656 } 657 } 658 659 mt76x02_remove_hdr_pad(skb, pad_len); 660 661 if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 662 status->aggr = true; 663 664 if (WARN_ON_ONCE(len > skb->len)) 665 return -EINVAL; 666 667 pskb_trim(skb, len); 668 669 status->chains = BIT(0); 670 signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 671 status->chain_signal[0] = signal; 672 if (nstreams > 1) { 673 status->chains |= BIT(1); 674 status->chain_signal[1] = mt76x02_mac_get_rssi(dev, 675 rxwi->rssi[1], 676 1); 677 signal = max_t(s8, signal, status->chain_signal[1]); 678 } 679 status->signal = signal; 680 status->freq = dev->mt76.chandef.chan->center_freq; 681 status->band = dev->mt76.chandef.chan->band; 682 683 status->tid = FIELD_GET(MT_RXWI_TID, tid_sn); 684 status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 685 686 return mt76x02_mac_process_rate(dev, status, rate); 687 } 688 689 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 690 { 691 struct mt76x02_tx_status stat = {}; 692 unsigned long flags; 693 u8 update = 1; 694 bool ret; 695 696 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 697 return; 698 699 trace_mac_txstat_poll(dev); 700 701 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 702 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 703 ret = mt76x02_mac_load_tx_status(dev, &stat); 704 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 705 706 if (!ret) 707 break; 708 709 if (!irq) { 710 mt76x02_send_tx_status(dev, &stat, &update); 711 continue; 712 } 713 714 kfifo_put(&dev->txstatus_fifo, stat); 715 } 716 } 717 718 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 719 struct mt76_queue_entry *e, bool flush) 720 { 721 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 722 struct mt76x02_txwi *txwi; 723 724 if (!e->txwi) { 725 dev_kfree_skb_any(e->skb); 726 return; 727 } 728 729 mt76x02_mac_poll_tx_status(dev, false); 730 731 txwi = (struct mt76x02_txwi *) &e->txwi->txwi; 732 trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid); 733 734 mt76_tx_complete_skb(mdev, e->skb); 735 } 736 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 737 738 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val) 739 { 740 u32 data = 0; 741 742 if (val != ~0) 743 data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) | 744 MT_PROT_CFG_RTS_THRESH; 745 746 mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); 747 748 mt76_rmw(dev, MT_CCK_PROT_CFG, 749 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 750 mt76_rmw(dev, MT_OFDM_PROT_CFG, 751 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 752 } 753 754 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot, 755 int ht_mode) 756 { 757 int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION; 758 bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 759 u32 prot[6]; 760 u32 vht_prot[3]; 761 int i; 762 u16 rts_thr; 763 764 for (i = 0; i < ARRAY_SIZE(prot); i++) { 765 prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4); 766 prot[i] &= ~MT_PROT_CFG_CTRL; 767 if (i >= 2) 768 prot[i] &= ~MT_PROT_CFG_RATE; 769 } 770 771 for (i = 0; i < ARRAY_SIZE(vht_prot); i++) { 772 vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4); 773 vht_prot[i] &= ~(MT_PROT_CFG_CTRL | MT_PROT_CFG_RATE); 774 } 775 776 rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH); 777 778 if (rts_thr != 0xffff) 779 prot[0] |= MT_PROT_CTRL_RTS_CTS; 780 781 if (legacy_prot) { 782 prot[1] |= MT_PROT_CTRL_CTS2SELF; 783 784 prot[2] |= MT_PROT_RATE_CCK_11; 785 prot[3] |= MT_PROT_RATE_CCK_11; 786 prot[4] |= MT_PROT_RATE_CCK_11; 787 prot[5] |= MT_PROT_RATE_CCK_11; 788 789 vht_prot[0] |= MT_PROT_RATE_CCK_11; 790 vht_prot[1] |= MT_PROT_RATE_CCK_11; 791 vht_prot[2] |= MT_PROT_RATE_CCK_11; 792 } else { 793 if (rts_thr != 0xffff) 794 prot[1] |= MT_PROT_CTRL_RTS_CTS; 795 796 prot[2] |= MT_PROT_RATE_OFDM_24; 797 prot[3] |= MT_PROT_RATE_DUP_OFDM_24; 798 prot[4] |= MT_PROT_RATE_OFDM_24; 799 prot[5] |= MT_PROT_RATE_DUP_OFDM_24; 800 801 vht_prot[0] |= MT_PROT_RATE_OFDM_24; 802 vht_prot[1] |= MT_PROT_RATE_DUP_OFDM_24; 803 vht_prot[2] |= MT_PROT_RATE_SGI_OFDM_24; 804 } 805 806 switch (mode) { 807 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 808 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 809 prot[2] |= MT_PROT_CTRL_RTS_CTS; 810 prot[3] |= MT_PROT_CTRL_RTS_CTS; 811 prot[4] |= MT_PROT_CTRL_RTS_CTS; 812 prot[5] |= MT_PROT_CTRL_RTS_CTS; 813 vht_prot[0] |= MT_PROT_CTRL_RTS_CTS; 814 vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 815 vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 816 break; 817 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 818 prot[3] |= MT_PROT_CTRL_RTS_CTS; 819 prot[5] |= MT_PROT_CTRL_RTS_CTS; 820 vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 821 vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 822 break; 823 } 824 825 if (non_gf) { 826 prot[4] |= MT_PROT_CTRL_RTS_CTS; 827 prot[5] |= MT_PROT_CTRL_RTS_CTS; 828 } 829 830 for (i = 0; i < ARRAY_SIZE(prot); i++) 831 mt76_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]); 832 833 for (i = 0; i < ARRAY_SIZE(vht_prot); i++) 834 mt76_wr(dev, MT_TX_PROT_CFG6 + i * 4, vht_prot[i]); 835 } 836 837 void mt76x02_update_channel(struct mt76_dev *mdev) 838 { 839 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 840 struct mt76_channel_state *state; 841 u32 active, busy; 842 843 state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan); 844 845 busy = mt76_rr(dev, MT_CH_BUSY); 846 active = busy + mt76_rr(dev, MT_CH_IDLE); 847 848 spin_lock_bh(&dev->mt76.cc_lock); 849 state->cc_busy += busy; 850 state->cc_active += active; 851 spin_unlock_bh(&dev->mt76.cc_lock); 852 } 853 EXPORT_SYMBOL_GPL(mt76x02_update_channel); 854 855 static void mt76x02_check_mac_err(struct mt76x02_dev *dev) 856 { 857 u32 val = mt76_rr(dev, 0x10f4); 858 859 if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) 860 return; 861 862 dev_err(dev->mt76.dev, "mac specific condition occurred\n"); 863 864 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); 865 udelay(10); 866 mt76_wr(dev, MT_MAC_SYS_CTRL, 867 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 868 } 869 870 static void 871 mt76x02_edcca_tx_enable(struct mt76x02_dev *dev, bool enable) 872 { 873 if (enable) { 874 u32 data; 875 876 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 877 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 878 /* enable pa-lna */ 879 data = mt76_rr(dev, MT_TX_PIN_CFG); 880 data |= MT_TX_PIN_CFG_TXANT | 881 MT_TX_PIN_CFG_RXANT | 882 MT_TX_PIN_RFTR_EN | 883 MT_TX_PIN_TRSW_EN; 884 mt76_wr(dev, MT_TX_PIN_CFG, data); 885 } else { 886 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 887 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 888 /* disable pa-lna */ 889 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT); 890 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT); 891 } 892 dev->ed_tx_blocked = !enable; 893 } 894 895 void mt76x02_edcca_init(struct mt76x02_dev *dev, bool enable) 896 { 897 dev->ed_trigger = 0; 898 dev->ed_silent = 0; 899 900 if (dev->ed_monitor && enable) { 901 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 902 u8 ed_th = chan->band == NL80211_BAND_5GHZ ? 0x0e : 0x20; 903 904 mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 905 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 906 mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0), 907 ed_th << 8 | ed_th); 908 mt76_set(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); 909 } else { 910 mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 911 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 912 if (is_mt76x2(dev)) { 913 mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); 914 mt76_set(dev, MT_TXOP_HLDR_ET, 915 MT_TXOP_HLDR_TX40M_BLK_EN); 916 } else { 917 mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464); 918 mt76_clear(dev, MT_TXOP_HLDR_ET, 919 MT_TXOP_HLDR_TX40M_BLK_EN); 920 } 921 } 922 mt76x02_edcca_tx_enable(dev, true); 923 924 /* clear previous CCA timer value */ 925 mt76_rr(dev, MT_ED_CCA_TIMER); 926 dev->ed_time = ktime_get_boottime(); 927 } 928 EXPORT_SYMBOL_GPL(mt76x02_edcca_init); 929 930 #define MT_EDCCA_TH 92 931 #define MT_EDCCA_BLOCK_TH 2 932 static void mt76x02_edcca_check(struct mt76x02_dev *dev) 933 { 934 ktime_t cur_time; 935 u32 active, val, busy; 936 937 cur_time = ktime_get_boottime(); 938 val = mt76_rr(dev, MT_ED_CCA_TIMER); 939 940 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 941 dev->ed_time = cur_time; 942 943 busy = (val * 100) / active; 944 busy = min_t(u32, busy, 100); 945 946 if (busy > MT_EDCCA_TH) { 947 dev->ed_trigger++; 948 dev->ed_silent = 0; 949 } else { 950 dev->ed_silent++; 951 dev->ed_trigger = 0; 952 } 953 954 if (dev->ed_trigger > MT_EDCCA_BLOCK_TH && 955 !dev->ed_tx_blocked) 956 mt76x02_edcca_tx_enable(dev, false); 957 else if (dev->ed_silent > MT_EDCCA_BLOCK_TH && 958 dev->ed_tx_blocked) 959 mt76x02_edcca_tx_enable(dev, true); 960 } 961 962 void mt76x02_mac_work(struct work_struct *work) 963 { 964 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 965 mac_work.work); 966 int i, idx; 967 968 mutex_lock(&dev->mt76.mutex); 969 970 mt76x02_update_channel(&dev->mt76); 971 for (i = 0, idx = 0; i < 16; i++) { 972 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 973 974 dev->aggr_stats[idx++] += val & 0xffff; 975 dev->aggr_stats[idx++] += val >> 16; 976 } 977 978 if (!dev->beacon_mask) 979 mt76x02_check_mac_err(dev); 980 981 if (dev->ed_monitor) 982 mt76x02_edcca_check(dev); 983 984 mutex_unlock(&dev->mt76.mutex); 985 986 mt76_tx_status_check(&dev->mt76, NULL, false); 987 988 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work, 989 MT_MAC_WORK_INTERVAL); 990 } 991 992 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr) 993 { 994 idx &= 7; 995 mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr)); 996 mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR, 997 get_unaligned_le16(addr + 4)); 998 } 999 1000 static int 1001 mt76x02_write_beacon(struct mt76x02_dev *dev, int offset, struct sk_buff *skb) 1002 { 1003 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 1004 struct mt76x02_txwi txwi; 1005 1006 if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi))) 1007 return -ENOSPC; 1008 1009 mt76x02_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len); 1010 1011 mt76_wr_copy(dev, offset, &txwi, sizeof(txwi)); 1012 offset += sizeof(txwi); 1013 1014 mt76_wr_copy(dev, offset, skb->data, skb->len); 1015 return 0; 1016 } 1017 1018 static int 1019 __mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 bcn_idx, 1020 struct sk_buff *skb) 1021 { 1022 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 1023 int beacon_addr = mt76x02_beacon_offsets[bcn_idx]; 1024 int ret = 0; 1025 int i; 1026 1027 /* Prevent corrupt transmissions during update */ 1028 mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx)); 1029 1030 if (skb) { 1031 ret = mt76x02_write_beacon(dev, beacon_addr, skb); 1032 if (!ret) 1033 dev->beacon_data_mask |= BIT(bcn_idx); 1034 } else { 1035 dev->beacon_data_mask &= ~BIT(bcn_idx); 1036 for (i = 0; i < beacon_len; i += 4) 1037 mt76_wr(dev, beacon_addr + i, 0); 1038 } 1039 1040 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask); 1041 1042 return ret; 1043 } 1044 1045 int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx, 1046 struct sk_buff *skb) 1047 { 1048 bool force_update = false; 1049 int bcn_idx = 0; 1050 int i; 1051 1052 for (i = 0; i < ARRAY_SIZE(dev->beacons); i++) { 1053 if (vif_idx == i) { 1054 force_update = !!dev->beacons[i] ^ !!skb; 1055 1056 if (dev->beacons[i]) 1057 dev_kfree_skb(dev->beacons[i]); 1058 1059 dev->beacons[i] = skb; 1060 __mt76x02_mac_set_beacon(dev, bcn_idx, skb); 1061 } else if (force_update && dev->beacons[i]) { 1062 __mt76x02_mac_set_beacon(dev, bcn_idx, 1063 dev->beacons[i]); 1064 } 1065 1066 bcn_idx += !!dev->beacons[i]; 1067 } 1068 1069 for (i = bcn_idx; i < ARRAY_SIZE(dev->beacons); i++) { 1070 if (!(dev->beacon_data_mask & BIT(i))) 1071 break; 1072 1073 __mt76x02_mac_set_beacon(dev, i, NULL); 1074 } 1075 1076 mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 1077 bcn_idx - 1); 1078 return 0; 1079 } 1080 1081 static void 1082 __mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, u8 vif_idx, 1083 bool val, struct sk_buff *skb) 1084 { 1085 u8 old_mask = dev->beacon_mask; 1086 bool en; 1087 u32 reg; 1088 1089 if (val) { 1090 dev->beacon_mask |= BIT(vif_idx); 1091 if (skb) 1092 mt76x02_mac_set_beacon(dev, vif_idx, skb); 1093 } else { 1094 dev->beacon_mask &= ~BIT(vif_idx); 1095 mt76x02_mac_set_beacon(dev, vif_idx, NULL); 1096 } 1097 1098 if (!!old_mask == !!dev->beacon_mask) 1099 return; 1100 1101 en = dev->beacon_mask; 1102 1103 reg = MT_BEACON_TIME_CFG_BEACON_TX | 1104 MT_BEACON_TIME_CFG_TBTT_EN | 1105 MT_BEACON_TIME_CFG_TIMER_EN; 1106 mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en); 1107 1108 if (mt76_is_usb(dev)) 1109 return; 1110 1111 mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); 1112 if (en) 1113 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1114 else 1115 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1116 } 1117 1118 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, 1119 struct ieee80211_vif *vif, bool val) 1120 { 1121 u8 vif_idx = ((struct mt76x02_vif *)vif->drv_priv)->idx; 1122 struct sk_buff *skb = NULL; 1123 1124 if (mt76_is_mmio(dev)) 1125 tasklet_disable(&dev->pre_tbtt_tasklet); 1126 else if (val) 1127 skb = ieee80211_beacon_get(mt76_hw(dev), vif); 1128 1129 if (!dev->beacon_mask) 1130 dev->tbtt_count = 0; 1131 1132 __mt76x02_mac_set_beacon_enable(dev, vif_idx, val, skb); 1133 1134 if (mt76_is_mmio(dev)) 1135 tasklet_enable(&dev->pre_tbtt_tasklet); 1136 } 1137