1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "mt76x02.h" 19 #include "mt76x02_trace.h" 20 21 static enum mt76x02_cipher_type 22 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 23 { 24 memset(key_data, 0, 32); 25 if (!key) 26 return MT_CIPHER_NONE; 27 28 if (key->keylen > 32) 29 return MT_CIPHER_NONE; 30 31 memcpy(key_data, key->key, key->keylen); 32 33 switch (key->cipher) { 34 case WLAN_CIPHER_SUITE_WEP40: 35 return MT_CIPHER_WEP40; 36 case WLAN_CIPHER_SUITE_WEP104: 37 return MT_CIPHER_WEP104; 38 case WLAN_CIPHER_SUITE_TKIP: 39 return MT_CIPHER_TKIP; 40 case WLAN_CIPHER_SUITE_CCMP: 41 return MT_CIPHER_AES_CCMP; 42 default: 43 return MT_CIPHER_NONE; 44 } 45 } 46 47 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 48 u8 key_idx, struct ieee80211_key_conf *key) 49 { 50 enum mt76x02_cipher_type cipher; 51 u8 key_data[32]; 52 u32 val; 53 54 cipher = mt76x02_mac_get_key_info(key, key_data); 55 if (cipher == MT_CIPHER_NONE && key) 56 return -EOPNOTSUPP; 57 58 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 59 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 60 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 61 mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 62 63 mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 64 sizeof(key_data)); 65 66 return 0; 67 } 68 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 69 70 void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx, 71 struct ieee80211_key_conf *key) 72 { 73 enum mt76x02_cipher_type cipher; 74 u8 key_data[32]; 75 u32 iv, eiv; 76 u64 pn; 77 78 cipher = mt76x02_mac_get_key_info(key, key_data); 79 iv = mt76_rr(dev, MT_WCID_IV(idx)); 80 eiv = mt76_rr(dev, MT_WCID_IV(idx) + 4); 81 82 pn = (u64)eiv << 16; 83 if (cipher == MT_CIPHER_TKIP) { 84 pn |= (iv >> 16) & 0xff; 85 pn |= (iv & 0xff) << 8; 86 } else if (cipher >= MT_CIPHER_AES_CCMP) { 87 pn |= iv & 0xffff; 88 } else { 89 return; 90 } 91 92 atomic64_set(&key->tx_pn, pn); 93 } 94 95 96 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 97 struct ieee80211_key_conf *key) 98 { 99 enum mt76x02_cipher_type cipher; 100 u8 key_data[32]; 101 u8 iv_data[8]; 102 u64 pn; 103 104 cipher = mt76x02_mac_get_key_info(key, key_data); 105 if (cipher == MT_CIPHER_NONE && key) 106 return -EOPNOTSUPP; 107 108 mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 109 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 110 111 memset(iv_data, 0, sizeof(iv_data)); 112 if (key) { 113 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 114 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 115 116 pn = atomic64_read(&key->tx_pn); 117 118 iv_data[3] = key->keyidx << 6; 119 if (cipher >= MT_CIPHER_TKIP) { 120 iv_data[3] |= 0x20; 121 put_unaligned_le32(pn >> 16, &iv_data[4]); 122 } 123 124 if (cipher == MT_CIPHER_TKIP) { 125 iv_data[0] = (pn >> 8) & 0xff; 126 iv_data[1] = (iv_data[0] | 0x20) & 0x7f; 127 iv_data[2] = pn & 0xff; 128 } else if (cipher >= MT_CIPHER_AES_CCMP) { 129 put_unaligned_le16((pn & 0xffff), &iv_data[0]); 130 } 131 } 132 133 mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 134 135 return 0; 136 } 137 138 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, 139 u8 vif_idx, u8 *mac) 140 { 141 struct mt76_wcid_addr addr = {}; 142 u32 attr; 143 144 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 145 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 146 147 mt76_wr(dev, MT_WCID_ATTR(idx), attr); 148 149 if (idx >= 128) 150 return; 151 152 if (mac) 153 memcpy(addr.macaddr, mac, ETH_ALEN); 154 155 mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 156 } 157 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 158 159 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop) 160 { 161 u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); 162 u32 bit = MT_WCID_DROP_MASK(idx); 163 164 /* prevent unnecessary writes */ 165 if ((val & bit) != (bit * drop)) 166 mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 167 } 168 169 static __le16 170 mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev, 171 const struct ieee80211_tx_rate *rate, u8 *nss_val) 172 { 173 u8 phy, rate_idx, nss, bw = 0; 174 u16 rateval; 175 176 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 177 rate_idx = rate->idx; 178 nss = 1 + (rate->idx >> 4); 179 phy = MT_PHY_TYPE_VHT; 180 if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 181 bw = 2; 182 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 183 bw = 1; 184 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 185 rate_idx = rate->idx; 186 nss = 1 + (rate->idx >> 3); 187 phy = MT_PHY_TYPE_HT; 188 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 189 phy = MT_PHY_TYPE_HT_GF; 190 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 191 bw = 1; 192 } else { 193 const struct ieee80211_rate *r; 194 int band = dev->mt76.chandef.chan->band; 195 u16 val; 196 197 r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx]; 198 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 199 val = r->hw_value_short; 200 else 201 val = r->hw_value; 202 203 phy = val >> 8; 204 rate_idx = val & 0xff; 205 nss = 1; 206 } 207 208 rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 209 rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 210 rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 211 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 212 rateval |= MT_RXWI_RATE_SGI; 213 214 *nss_val = nss; 215 return cpu_to_le16(rateval); 216 } 217 218 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 219 const struct ieee80211_tx_rate *rate) 220 { 221 spin_lock_bh(&dev->mt76.lock); 222 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 223 wcid->tx_rate_set = true; 224 spin_unlock_bh(&dev->mt76.lock); 225 } 226 227 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable) 228 { 229 if (enable) 230 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 231 else 232 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); 233 } 234 235 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 236 struct mt76x02_tx_status *stat) 237 { 238 u32 stat1, stat2; 239 240 stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 241 stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); 242 243 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 244 if (!stat->valid) 245 return false; 246 247 stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 248 stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 249 stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 250 stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 251 stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 252 253 stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 254 stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 255 256 trace_mac_txstat_fetch(dev, stat); 257 258 return true; 259 } 260 261 static int 262 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 263 enum nl80211_band band) 264 { 265 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 266 267 txrate->idx = 0; 268 txrate->flags = 0; 269 txrate->count = 1; 270 271 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 272 case MT_PHY_TYPE_OFDM: 273 if (band == NL80211_BAND_2GHZ) 274 idx += 4; 275 276 txrate->idx = idx; 277 return 0; 278 case MT_PHY_TYPE_CCK: 279 if (idx >= 8) 280 idx -= 8; 281 282 txrate->idx = idx; 283 return 0; 284 case MT_PHY_TYPE_HT_GF: 285 txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 286 /* fall through */ 287 case MT_PHY_TYPE_HT: 288 txrate->flags |= IEEE80211_TX_RC_MCS; 289 txrate->idx = idx; 290 break; 291 case MT_PHY_TYPE_VHT: 292 txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 293 txrate->idx = idx; 294 break; 295 default: 296 return -EINVAL; 297 } 298 299 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 300 case MT_PHY_BW_20: 301 break; 302 case MT_PHY_BW_40: 303 txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 304 break; 305 case MT_PHY_BW_80: 306 txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 307 break; 308 default: 309 return -EINVAL; 310 } 311 312 if (rate & MT_RXWI_RATE_SGI) 313 txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 314 315 return 0; 316 } 317 318 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 319 struct sk_buff *skb, struct mt76_wcid *wcid, 320 struct ieee80211_sta *sta, int len) 321 { 322 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 323 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 324 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 325 struct ieee80211_key_conf *key = info->control.hw_key; 326 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 327 u16 txwi_flags = 0; 328 u8 nss; 329 s8 txpwr_adj, max_txpwr_adj; 330 u8 ccmp_pn[8], nstreams = dev->mt76.chainmask & 0xf; 331 332 memset(txwi, 0, sizeof(*txwi)); 333 334 if (!info->control.hw_key && wcid && wcid->hw_key_idx != 0xff && 335 ieee80211_has_protected(hdr->frame_control)) { 336 wcid = NULL; 337 ieee80211_get_tx_rates(info->control.vif, sta, skb, 338 info->control.rates, 1); 339 } 340 341 if (wcid) 342 txwi->wcid = wcid->idx; 343 else 344 txwi->wcid = 0xff; 345 346 if (wcid && wcid->sw_iv && key) { 347 u64 pn = atomic64_inc_return(&key->tx_pn); 348 ccmp_pn[0] = pn; 349 ccmp_pn[1] = pn >> 8; 350 ccmp_pn[2] = 0; 351 ccmp_pn[3] = 0x20 | (key->keyidx << 6); 352 ccmp_pn[4] = pn >> 16; 353 ccmp_pn[5] = pn >> 24; 354 ccmp_pn[6] = pn >> 32; 355 ccmp_pn[7] = pn >> 40; 356 txwi->iv = *((__le32 *)&ccmp_pn[0]); 357 txwi->eiv = *((__le32 *)&ccmp_pn[4]); 358 } 359 360 spin_lock_bh(&dev->mt76.lock); 361 if (wcid && (rate->idx < 0 || !rate->count)) { 362 txwi->rate = wcid->tx_rate; 363 max_txpwr_adj = wcid->max_txpwr_adj; 364 nss = wcid->tx_rate_nss; 365 } else { 366 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 367 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 368 } 369 spin_unlock_bh(&dev->mt76.lock); 370 371 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->mt76.txpower_conf, 372 max_txpwr_adj); 373 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 374 375 if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4) 376 txwi->txstream = 0x13; 377 else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 && 378 !(txwi->rate & cpu_to_le16(rate_ht_mask))) 379 txwi->txstream = 0x93; 380 381 if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC)) 382 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 383 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 384 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 385 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC) 386 txwi_flags |= MT_TXWI_FLAGS_MMPS; 387 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 388 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 389 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 390 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 391 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 392 u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 393 394 ba_size <<= sta->ht_cap.ampdu_factor; 395 ba_size = min_t(int, 63, ba_size - 1); 396 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 397 ba_size = 0; 398 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 399 400 txwi_flags |= MT_TXWI_FLAGS_AMPDU | 401 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, 402 sta->ht_cap.ampdu_density); 403 } 404 405 if (ieee80211_is_probe_resp(hdr->frame_control) || 406 ieee80211_is_beacon(hdr->frame_control)) 407 txwi_flags |= MT_TXWI_FLAGS_TS; 408 409 txwi->flags |= cpu_to_le16(txwi_flags); 410 txwi->len_ctl = cpu_to_le16(len); 411 } 412 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 413 414 static void 415 mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, 416 struct ieee80211_tx_info *info, 417 struct mt76x02_tx_status *st, int n_frames) 418 { 419 struct ieee80211_tx_rate *rate = info->status.rates; 420 int cur_idx, last_rate; 421 int i; 422 423 if (!n_frames) 424 return; 425 426 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 427 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 428 dev->mt76.chandef.chan->band); 429 if (last_rate < IEEE80211_TX_MAX_RATES - 1) 430 rate[last_rate + 1].idx = -1; 431 432 cur_idx = rate[last_rate].idx + last_rate; 433 for (i = 0; i <= last_rate; i++) { 434 rate[i].flags = rate[last_rate].flags; 435 rate[i].idx = max_t(int, 0, cur_idx - i); 436 rate[i].count = 1; 437 } 438 rate[last_rate].count = st->retry + 1 - last_rate; 439 440 info->status.ampdu_len = n_frames; 441 info->status.ampdu_ack_len = st->success ? n_frames : 0; 442 443 if (st->aggr) 444 info->flags |= IEEE80211_TX_CTL_AMPDU | 445 IEEE80211_TX_STAT_AMPDU; 446 447 if (!st->ack_req) 448 info->flags |= IEEE80211_TX_CTL_NO_ACK; 449 else if (st->success) 450 info->flags |= IEEE80211_TX_STAT_ACK; 451 } 452 453 void mt76x02_send_tx_status(struct mt76x02_dev *dev, 454 struct mt76x02_tx_status *stat, u8 *update) 455 { 456 struct ieee80211_tx_info info = {}; 457 struct ieee80211_tx_status status = { 458 .info = &info 459 }; 460 struct mt76_wcid *wcid = NULL; 461 struct mt76x02_sta *msta = NULL; 462 struct mt76_dev *mdev = &dev->mt76; 463 struct sk_buff_head list; 464 465 if (stat->pktid == MT_PACKET_ID_NO_ACK) 466 return; 467 468 rcu_read_lock(); 469 470 if (stat->wcid < ARRAY_SIZE(dev->mt76.wcid)) 471 wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]); 472 473 if (wcid && wcid->sta) { 474 void *priv; 475 476 priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 477 status.sta = container_of(priv, struct ieee80211_sta, 478 drv_priv); 479 } 480 481 mt76_tx_status_lock(mdev, &list); 482 483 if (wcid) { 484 if (stat->pktid >= MT_PACKET_ID_FIRST) 485 status.skb = mt76_tx_status_skb_get(mdev, wcid, 486 stat->pktid, &list); 487 if (status.skb) 488 status.info = IEEE80211_SKB_CB(status.skb); 489 } 490 491 if (msta && stat->aggr && !status.skb) { 492 u32 stat_val, stat_cache; 493 494 stat_val = stat->rate; 495 stat_val |= ((u32) stat->retry) << 16; 496 stat_cache = msta->status.rate; 497 stat_cache |= ((u32) msta->status.retry) << 16; 498 499 if (*update == 0 && stat_val == stat_cache && 500 stat->wcid == msta->status.wcid && msta->n_frames < 32) { 501 msta->n_frames++; 502 mt76_tx_status_unlock(mdev, &list); 503 rcu_read_unlock(); 504 return; 505 } 506 507 mt76x02_mac_fill_tx_status(dev, status.info, &msta->status, 508 msta->n_frames); 509 510 msta->status = *stat; 511 msta->n_frames = 1; 512 *update = 0; 513 } else { 514 mt76x02_mac_fill_tx_status(dev, status.info, stat, 1); 515 *update = 1; 516 } 517 518 if (status.skb) 519 mt76_tx_status_skb_done(mdev, status.skb, &list); 520 mt76_tx_status_unlock(mdev, &list); 521 522 if (!status.skb) 523 ieee80211_tx_status_ext(mt76_hw(dev), &status); 524 rcu_read_unlock(); 525 } 526 527 static int 528 mt76x02_mac_process_rate(struct mt76x02_dev *dev, 529 struct mt76_rx_status *status, 530 u16 rate) 531 { 532 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 533 534 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 535 case MT_PHY_TYPE_OFDM: 536 if (idx >= 8) 537 idx = 0; 538 539 if (status->band == NL80211_BAND_2GHZ) 540 idx += 4; 541 542 status->rate_idx = idx; 543 return 0; 544 case MT_PHY_TYPE_CCK: 545 if (idx >= 8) { 546 idx -= 8; 547 status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 548 } 549 550 if (idx >= 4) 551 idx = 0; 552 553 status->rate_idx = idx; 554 return 0; 555 case MT_PHY_TYPE_HT_GF: 556 status->enc_flags |= RX_ENC_FLAG_HT_GF; 557 /* fall through */ 558 case MT_PHY_TYPE_HT: 559 status->encoding = RX_ENC_HT; 560 status->rate_idx = idx; 561 break; 562 case MT_PHY_TYPE_VHT: { 563 u8 n_rxstream = dev->mt76.chainmask & 0xf; 564 565 status->encoding = RX_ENC_VHT; 566 status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 567 status->nss = min_t(u8, n_rxstream, 568 FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1); 569 break; 570 } 571 default: 572 return -EINVAL; 573 } 574 575 if (rate & MT_RXWI_RATE_LDPC) 576 status->enc_flags |= RX_ENC_FLAG_LDPC; 577 578 if (rate & MT_RXWI_RATE_SGI) 579 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 580 581 if (rate & MT_RXWI_RATE_STBC) 582 status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 583 584 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 585 case MT_PHY_BW_20: 586 break; 587 case MT_PHY_BW_40: 588 status->bw = RATE_INFO_BW_40; 589 break; 590 case MT_PHY_BW_80: 591 status->bw = RATE_INFO_BW_80; 592 break; 593 default: 594 break; 595 } 596 597 return 0; 598 } 599 600 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr) 601 { 602 static const u8 null_addr[ETH_ALEN] = {}; 603 int i; 604 605 ether_addr_copy(dev->mt76.macaddr, addr); 606 607 if (!is_valid_ether_addr(dev->mt76.macaddr)) { 608 eth_random_addr(dev->mt76.macaddr); 609 dev_info(dev->mt76.dev, 610 "Invalid MAC address, using random address %pM\n", 611 dev->mt76.macaddr); 612 } 613 614 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr)); 615 mt76_wr(dev, MT_MAC_ADDR_DW1, 616 get_unaligned_le16(dev->mt76.macaddr + 4) | 617 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 618 619 mt76_wr(dev, MT_MAC_BSSID_DW0, 620 get_unaligned_le32(dev->mt76.macaddr)); 621 mt76_wr(dev, MT_MAC_BSSID_DW1, 622 get_unaligned_le16(dev->mt76.macaddr + 4) | 623 FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 APs + 8 STAs */ 624 MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT); 625 626 for (i = 0; i < 16; i++) 627 mt76x02_mac_set_bssid(dev, i, null_addr); 628 } 629 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 630 631 static int 632 mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 633 { 634 struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 635 636 rssi += cal->rssi_offset[chain]; 637 rssi -= cal->lna_gain; 638 639 return rssi; 640 } 641 642 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 643 void *rxi) 644 { 645 struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb; 646 struct mt76x02_rxwi *rxwi = rxi; 647 struct mt76x02_sta *sta; 648 u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 649 u32 ctl = le32_to_cpu(rxwi->ctl); 650 u16 rate = le16_to_cpu(rxwi->rate); 651 u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 652 bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 653 int pad_len = 0, nstreams = dev->mt76.chainmask & 0xf; 654 s8 signal; 655 u8 pn_len; 656 u8 wcid; 657 int len; 658 659 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 660 return -EINVAL; 661 662 if (rxinfo & MT_RXINFO_L2PAD) 663 pad_len += 2; 664 665 if (rxinfo & MT_RXINFO_DECRYPT) { 666 status->flag |= RX_FLAG_DECRYPTED; 667 status->flag |= RX_FLAG_MMIC_STRIPPED; 668 status->flag |= RX_FLAG_MIC_STRIPPED; 669 status->flag |= RX_FLAG_IV_STRIPPED; 670 } 671 672 wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 673 sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 674 status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 675 676 len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 677 pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 678 if (pn_len) { 679 int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 680 u8 *data = skb->data + offset; 681 682 status->iv[0] = data[7]; 683 status->iv[1] = data[6]; 684 status->iv[2] = data[5]; 685 status->iv[3] = data[4]; 686 status->iv[4] = data[1]; 687 status->iv[5] = data[0]; 688 689 /* 690 * Driver CCMP validation can't deal with fragments. 691 * Let mac80211 take care of it. 692 */ 693 if (rxinfo & MT_RXINFO_FRAG) { 694 status->flag &= ~RX_FLAG_IV_STRIPPED; 695 } else { 696 pad_len += pn_len << 2; 697 len -= pn_len << 2; 698 } 699 } 700 701 mt76x02_remove_hdr_pad(skb, pad_len); 702 703 if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 704 status->aggr = true; 705 706 if (WARN_ON_ONCE(len > skb->len)) 707 return -EINVAL; 708 709 pskb_trim(skb, len); 710 711 status->chains = BIT(0); 712 signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 713 status->chain_signal[0] = signal; 714 if (nstreams > 1) { 715 status->chains |= BIT(1); 716 status->chain_signal[1] = mt76x02_mac_get_rssi(dev, 717 rxwi->rssi[1], 718 1); 719 signal = max_t(s8, signal, status->chain_signal[1]); 720 } 721 status->signal = signal; 722 status->freq = dev->mt76.chandef.chan->center_freq; 723 status->band = dev->mt76.chandef.chan->band; 724 725 status->tid = FIELD_GET(MT_RXWI_TID, tid_sn); 726 status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 727 728 return mt76x02_mac_process_rate(dev, status, rate); 729 } 730 731 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 732 { 733 struct mt76x02_tx_status stat = {}; 734 unsigned long flags; 735 u8 update = 1; 736 bool ret; 737 738 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 739 return; 740 741 trace_mac_txstat_poll(dev); 742 743 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 744 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 745 ret = mt76x02_mac_load_tx_status(dev, &stat); 746 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 747 748 if (!ret) 749 break; 750 751 if (!irq) { 752 mt76x02_send_tx_status(dev, &stat, &update); 753 continue; 754 } 755 756 kfifo_put(&dev->txstatus_fifo, stat); 757 } 758 } 759 760 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 761 struct mt76_queue_entry *e, bool flush) 762 { 763 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 764 struct mt76x02_txwi *txwi; 765 766 if (!e->txwi) { 767 dev_kfree_skb_any(e->skb); 768 return; 769 } 770 771 mt76x02_mac_poll_tx_status(dev, false); 772 773 txwi = (struct mt76x02_txwi *) &e->txwi->txwi; 774 trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid); 775 776 mt76_tx_complete_skb(mdev, e->skb); 777 } 778 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 779 780 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val) 781 { 782 u32 data = 0; 783 784 if (val != ~0) 785 data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) | 786 MT_PROT_CFG_RTS_THRESH; 787 788 mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val); 789 790 mt76_rmw(dev, MT_CCK_PROT_CFG, 791 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 792 mt76_rmw(dev, MT_OFDM_PROT_CFG, 793 MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data); 794 } 795 796 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot, 797 int ht_mode) 798 { 799 int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION; 800 bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 801 u32 prot[6]; 802 u32 vht_prot[3]; 803 int i; 804 u16 rts_thr; 805 806 for (i = 0; i < ARRAY_SIZE(prot); i++) { 807 prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4); 808 prot[i] &= ~MT_PROT_CFG_CTRL; 809 if (i >= 2) 810 prot[i] &= ~MT_PROT_CFG_RATE; 811 } 812 813 for (i = 0; i < ARRAY_SIZE(vht_prot); i++) { 814 vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4); 815 vht_prot[i] &= ~(MT_PROT_CFG_CTRL | MT_PROT_CFG_RATE); 816 } 817 818 rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH); 819 820 if (rts_thr != 0xffff) 821 prot[0] |= MT_PROT_CTRL_RTS_CTS; 822 823 if (legacy_prot) { 824 prot[1] |= MT_PROT_CTRL_CTS2SELF; 825 826 prot[2] |= MT_PROT_RATE_CCK_11; 827 prot[3] |= MT_PROT_RATE_CCK_11; 828 prot[4] |= MT_PROT_RATE_CCK_11; 829 prot[5] |= MT_PROT_RATE_CCK_11; 830 831 vht_prot[0] |= MT_PROT_RATE_CCK_11; 832 vht_prot[1] |= MT_PROT_RATE_CCK_11; 833 vht_prot[2] |= MT_PROT_RATE_CCK_11; 834 } else { 835 if (rts_thr != 0xffff) 836 prot[1] |= MT_PROT_CTRL_RTS_CTS; 837 838 prot[2] |= MT_PROT_RATE_OFDM_24; 839 prot[3] |= MT_PROT_RATE_DUP_OFDM_24; 840 prot[4] |= MT_PROT_RATE_OFDM_24; 841 prot[5] |= MT_PROT_RATE_DUP_OFDM_24; 842 843 vht_prot[0] |= MT_PROT_RATE_OFDM_24; 844 vht_prot[1] |= MT_PROT_RATE_DUP_OFDM_24; 845 vht_prot[2] |= MT_PROT_RATE_SGI_OFDM_24; 846 } 847 848 switch (mode) { 849 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 850 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 851 prot[2] |= MT_PROT_CTRL_RTS_CTS; 852 prot[3] |= MT_PROT_CTRL_RTS_CTS; 853 prot[4] |= MT_PROT_CTRL_RTS_CTS; 854 prot[5] |= MT_PROT_CTRL_RTS_CTS; 855 vht_prot[0] |= MT_PROT_CTRL_RTS_CTS; 856 vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 857 vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 858 break; 859 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 860 prot[3] |= MT_PROT_CTRL_RTS_CTS; 861 prot[5] |= MT_PROT_CTRL_RTS_CTS; 862 vht_prot[1] |= MT_PROT_CTRL_RTS_CTS; 863 vht_prot[2] |= MT_PROT_CTRL_RTS_CTS; 864 break; 865 } 866 867 if (non_gf) { 868 prot[4] |= MT_PROT_CTRL_RTS_CTS; 869 prot[5] |= MT_PROT_CTRL_RTS_CTS; 870 } 871 872 for (i = 0; i < ARRAY_SIZE(prot); i++) 873 mt76_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]); 874 875 for (i = 0; i < ARRAY_SIZE(vht_prot); i++) 876 mt76_wr(dev, MT_TX_PROT_CFG6 + i * 4, vht_prot[i]); 877 } 878 879 void mt76x02_update_channel(struct mt76_dev *mdev) 880 { 881 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 882 struct mt76_channel_state *state; 883 u32 active, busy; 884 885 state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan); 886 887 busy = mt76_rr(dev, MT_CH_BUSY); 888 active = busy + mt76_rr(dev, MT_CH_IDLE); 889 890 spin_lock_bh(&dev->mt76.cc_lock); 891 state->cc_busy += busy; 892 state->cc_active += active; 893 spin_unlock_bh(&dev->mt76.cc_lock); 894 } 895 EXPORT_SYMBOL_GPL(mt76x02_update_channel); 896 897 static void mt76x02_check_mac_err(struct mt76x02_dev *dev) 898 { 899 u32 val = mt76_rr(dev, 0x10f4); 900 901 if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) 902 return; 903 904 dev_err(dev->mt76.dev, "mac specific condition occurred\n"); 905 906 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); 907 udelay(10); 908 mt76_wr(dev, MT_MAC_SYS_CTRL, 909 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 910 } 911 912 static void 913 mt76x02_edcca_tx_enable(struct mt76x02_dev *dev, bool enable) 914 { 915 if (enable) { 916 u32 data; 917 918 mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 919 mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 920 /* enable pa-lna */ 921 data = mt76_rr(dev, MT_TX_PIN_CFG); 922 data |= MT_TX_PIN_CFG_TXANT | 923 MT_TX_PIN_CFG_RXANT | 924 MT_TX_PIN_RFTR_EN | 925 MT_TX_PIN_TRSW_EN; 926 mt76_wr(dev, MT_TX_PIN_CFG, data); 927 } else { 928 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 929 mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN); 930 /* disable pa-lna */ 931 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT); 932 mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT); 933 } 934 dev->ed_tx_blocked = !enable; 935 } 936 937 void mt76x02_edcca_init(struct mt76x02_dev *dev, bool enable) 938 { 939 dev->ed_trigger = 0; 940 dev->ed_silent = 0; 941 942 if (dev->ed_monitor && enable) { 943 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 944 u8 ed_th = chan->band == NL80211_BAND_5GHZ ? 0x0e : 0x20; 945 946 mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 947 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 948 mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0), 949 ed_th << 8 | ed_th); 950 mt76_set(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN); 951 } else { 952 mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN); 953 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 954 if (is_mt76x2(dev)) { 955 mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070); 956 mt76_set(dev, MT_TXOP_HLDR_ET, 957 MT_TXOP_HLDR_TX40M_BLK_EN); 958 } else { 959 mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464); 960 mt76_clear(dev, MT_TXOP_HLDR_ET, 961 MT_TXOP_HLDR_TX40M_BLK_EN); 962 } 963 } 964 mt76x02_edcca_tx_enable(dev, true); 965 dev->ed_monitor_learning = true; 966 967 /* clear previous CCA timer value */ 968 mt76_rr(dev, MT_ED_CCA_TIMER); 969 dev->ed_time = ktime_get_boottime(); 970 } 971 EXPORT_SYMBOL_GPL(mt76x02_edcca_init); 972 973 #define MT_EDCCA_TH 92 974 #define MT_EDCCA_BLOCK_TH 2 975 #define MT_EDCCA_LEARN_TH 50 976 #define MT_EDCCA_LEARN_CCA 180 977 #define MT_EDCCA_LEARN_TIMEOUT (20 * HZ) 978 979 static void mt76x02_edcca_check(struct mt76x02_dev *dev) 980 { 981 ktime_t cur_time; 982 u32 active, val, busy; 983 984 cur_time = ktime_get_boottime(); 985 val = mt76_rr(dev, MT_ED_CCA_TIMER); 986 987 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 988 dev->ed_time = cur_time; 989 990 busy = (val * 100) / active; 991 busy = min_t(u32, busy, 100); 992 993 if (busy > MT_EDCCA_TH) { 994 dev->ed_trigger++; 995 dev->ed_silent = 0; 996 } else { 997 dev->ed_silent++; 998 dev->ed_trigger = 0; 999 } 1000 1001 if (dev->cal.agc_lowest_gain && 1002 dev->cal.false_cca > MT_EDCCA_LEARN_CCA && 1003 dev->ed_trigger > MT_EDCCA_LEARN_TH) { 1004 dev->ed_monitor_learning = false; 1005 dev->ed_trigger_timeout = jiffies + 20 * HZ; 1006 } else if (!dev->ed_monitor_learning && 1007 time_is_after_jiffies(dev->ed_trigger_timeout)) { 1008 dev->ed_monitor_learning = true; 1009 mt76x02_edcca_tx_enable(dev, true); 1010 } 1011 1012 if (dev->ed_monitor_learning) 1013 return; 1014 1015 if (dev->ed_trigger > MT_EDCCA_BLOCK_TH && !dev->ed_tx_blocked) 1016 mt76x02_edcca_tx_enable(dev, false); 1017 else if (dev->ed_silent > MT_EDCCA_BLOCK_TH && dev->ed_tx_blocked) 1018 mt76x02_edcca_tx_enable(dev, true); 1019 } 1020 1021 void mt76x02_mac_work(struct work_struct *work) 1022 { 1023 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 1024 mac_work.work); 1025 int i, idx; 1026 1027 mutex_lock(&dev->mt76.mutex); 1028 1029 mt76x02_update_channel(&dev->mt76); 1030 for (i = 0, idx = 0; i < 16; i++) { 1031 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 1032 1033 dev->aggr_stats[idx++] += val & 0xffff; 1034 dev->aggr_stats[idx++] += val >> 16; 1035 } 1036 1037 if (!dev->beacon_mask) 1038 mt76x02_check_mac_err(dev); 1039 1040 if (dev->ed_monitor) 1041 mt76x02_edcca_check(dev); 1042 1043 mutex_unlock(&dev->mt76.mutex); 1044 1045 mt76_tx_status_check(&dev->mt76, NULL, false); 1046 1047 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work, 1048 MT_MAC_WORK_INTERVAL); 1049 } 1050 1051 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr) 1052 { 1053 idx &= 7; 1054 mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr)); 1055 mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR, 1056 get_unaligned_le16(addr + 4)); 1057 } 1058 1059 static int 1060 mt76x02_write_beacon(struct mt76x02_dev *dev, int offset, struct sk_buff *skb) 1061 { 1062 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 1063 struct mt76x02_txwi txwi; 1064 1065 if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi))) 1066 return -ENOSPC; 1067 1068 mt76x02_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len); 1069 1070 mt76_wr_copy(dev, offset, &txwi, sizeof(txwi)); 1071 offset += sizeof(txwi); 1072 1073 mt76_wr_copy(dev, offset, skb->data, skb->len); 1074 return 0; 1075 } 1076 1077 static int 1078 __mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 bcn_idx, 1079 struct sk_buff *skb) 1080 { 1081 int beacon_len = mt76x02_beacon_offsets[1] - mt76x02_beacon_offsets[0]; 1082 int beacon_addr = mt76x02_beacon_offsets[bcn_idx]; 1083 int ret = 0; 1084 int i; 1085 1086 /* Prevent corrupt transmissions during update */ 1087 mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx)); 1088 1089 if (skb) { 1090 ret = mt76x02_write_beacon(dev, beacon_addr, skb); 1091 if (!ret) 1092 dev->beacon_data_mask |= BIT(bcn_idx); 1093 } else { 1094 dev->beacon_data_mask &= ~BIT(bcn_idx); 1095 for (i = 0; i < beacon_len; i += 4) 1096 mt76_wr(dev, beacon_addr + i, 0); 1097 } 1098 1099 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask); 1100 1101 return ret; 1102 } 1103 1104 int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx, 1105 struct sk_buff *skb) 1106 { 1107 bool force_update = false; 1108 int bcn_idx = 0; 1109 int i; 1110 1111 for (i = 0; i < ARRAY_SIZE(dev->beacons); i++) { 1112 if (vif_idx == i) { 1113 force_update = !!dev->beacons[i] ^ !!skb; 1114 1115 if (dev->beacons[i]) 1116 dev_kfree_skb(dev->beacons[i]); 1117 1118 dev->beacons[i] = skb; 1119 __mt76x02_mac_set_beacon(dev, bcn_idx, skb); 1120 } else if (force_update && dev->beacons[i]) { 1121 __mt76x02_mac_set_beacon(dev, bcn_idx, 1122 dev->beacons[i]); 1123 } 1124 1125 bcn_idx += !!dev->beacons[i]; 1126 } 1127 1128 for (i = bcn_idx; i < ARRAY_SIZE(dev->beacons); i++) { 1129 if (!(dev->beacon_data_mask & BIT(i))) 1130 break; 1131 1132 __mt76x02_mac_set_beacon(dev, i, NULL); 1133 } 1134 1135 mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 1136 bcn_idx - 1); 1137 return 0; 1138 } 1139 1140 static void 1141 __mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, u8 vif_idx, 1142 bool val, struct sk_buff *skb) 1143 { 1144 u8 old_mask = dev->beacon_mask; 1145 bool en; 1146 u32 reg; 1147 1148 if (val) { 1149 dev->beacon_mask |= BIT(vif_idx); 1150 if (skb) 1151 mt76x02_mac_set_beacon(dev, vif_idx, skb); 1152 } else { 1153 dev->beacon_mask &= ~BIT(vif_idx); 1154 mt76x02_mac_set_beacon(dev, vif_idx, NULL); 1155 } 1156 1157 if (!!old_mask == !!dev->beacon_mask) 1158 return; 1159 1160 en = dev->beacon_mask; 1161 1162 reg = MT_BEACON_TIME_CFG_BEACON_TX | 1163 MT_BEACON_TIME_CFG_TBTT_EN | 1164 MT_BEACON_TIME_CFG_TIMER_EN; 1165 mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en); 1166 1167 if (mt76_is_usb(dev)) 1168 return; 1169 1170 mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en); 1171 if (en) 1172 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1173 else 1174 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT); 1175 } 1176 1177 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, 1178 struct ieee80211_vif *vif, bool val) 1179 { 1180 u8 vif_idx = ((struct mt76x02_vif *)vif->drv_priv)->idx; 1181 struct sk_buff *skb = NULL; 1182 1183 if (mt76_is_mmio(dev)) 1184 tasklet_disable(&dev->pre_tbtt_tasklet); 1185 else if (val) 1186 skb = ieee80211_beacon_get(mt76_hw(dev), vif); 1187 1188 if (!dev->beacon_mask) 1189 dev->tbtt_count = 0; 1190 1191 __mt76x02_mac_set_beacon_enable(dev, vif_idx, val, skb); 1192 1193 if (mt76_is_mmio(dev)) 1194 tasklet_enable(&dev->pre_tbtt_tasklet); 1195 } 1196