1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "mt76x02.h" 19 #include "mt76x02_trace.h" 20 21 enum mt76x02_cipher_type 22 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 23 { 24 memset(key_data, 0, 32); 25 if (!key) 26 return MT_CIPHER_NONE; 27 28 if (key->keylen > 32) 29 return MT_CIPHER_NONE; 30 31 memcpy(key_data, key->key, key->keylen); 32 33 switch (key->cipher) { 34 case WLAN_CIPHER_SUITE_WEP40: 35 return MT_CIPHER_WEP40; 36 case WLAN_CIPHER_SUITE_WEP104: 37 return MT_CIPHER_WEP104; 38 case WLAN_CIPHER_SUITE_TKIP: 39 return MT_CIPHER_TKIP; 40 case WLAN_CIPHER_SUITE_CCMP: 41 return MT_CIPHER_AES_CCMP; 42 default: 43 return MT_CIPHER_NONE; 44 } 45 } 46 EXPORT_SYMBOL_GPL(mt76x02_mac_get_key_info); 47 48 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, 49 u8 key_idx, struct ieee80211_key_conf *key) 50 { 51 enum mt76x02_cipher_type cipher; 52 u8 key_data[32]; 53 u32 val; 54 55 cipher = mt76x02_mac_get_key_info(key, key_data); 56 if (cipher == MT_CIPHER_NONE && key) 57 return -EOPNOTSUPP; 58 59 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 60 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 61 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 62 mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 63 64 mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 65 sizeof(key_data)); 66 67 return 0; 68 } 69 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 70 71 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, 72 struct ieee80211_key_conf *key) 73 { 74 enum mt76x02_cipher_type cipher; 75 u8 key_data[32]; 76 u8 iv_data[8]; 77 78 cipher = mt76x02_mac_get_key_info(key, key_data); 79 if (cipher == MT_CIPHER_NONE && key) 80 return -EOPNOTSUPP; 81 82 mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 83 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 84 85 memset(iv_data, 0, sizeof(iv_data)); 86 if (key) { 87 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 88 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 89 iv_data[3] = key->keyidx << 6; 90 if (cipher >= MT_CIPHER_TKIP) 91 iv_data[3] |= 0x20; 92 } 93 94 mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 95 96 return 0; 97 } 98 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_key); 99 100 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, 101 u8 vif_idx, u8 *mac) 102 { 103 struct mt76_wcid_addr addr = {}; 104 u32 attr; 105 106 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 107 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 108 109 mt76_wr(dev, MT_WCID_ATTR(idx), attr); 110 111 mt76_wr(dev, MT_WCID_TX_RATE(idx), 0); 112 mt76_wr(dev, MT_WCID_TX_RATE(idx) + 4, 0); 113 114 if (idx >= 128) 115 return; 116 117 if (mac) 118 memcpy(addr.macaddr, mac, ETH_ALEN); 119 120 mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 121 } 122 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 123 124 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop) 125 { 126 u32 val = mt76_rr(dev, MT_WCID_DROP(idx)); 127 u32 bit = MT_WCID_DROP_MASK(idx); 128 129 /* prevent unnecessary writes */ 130 if ((val & bit) != (bit * drop)) 131 mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 132 } 133 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_drop); 134 135 void mt76x02_txq_init(struct mt76x02_dev *dev, struct ieee80211_txq *txq) 136 { 137 struct mt76_txq *mtxq; 138 139 if (!txq) 140 return; 141 142 mtxq = (struct mt76_txq *) txq->drv_priv; 143 if (txq->sta) { 144 struct mt76x02_sta *sta; 145 146 sta = (struct mt76x02_sta *) txq->sta->drv_priv; 147 mtxq->wcid = &sta->wcid; 148 } else { 149 struct mt76x02_vif *mvif; 150 151 mvif = (struct mt76x02_vif *) txq->vif->drv_priv; 152 mtxq->wcid = &mvif->group_wcid; 153 } 154 155 mt76_txq_init(&dev->mt76, txq); 156 } 157 EXPORT_SYMBOL_GPL(mt76x02_txq_init); 158 159 static __le16 160 mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev, 161 const struct ieee80211_tx_rate *rate, u8 *nss_val) 162 { 163 u16 rateval; 164 u8 phy, rate_idx; 165 u8 nss = 1; 166 u8 bw = 0; 167 168 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 169 rate_idx = rate->idx; 170 nss = 1 + (rate->idx >> 4); 171 phy = MT_PHY_TYPE_VHT; 172 if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 173 bw = 2; 174 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 175 bw = 1; 176 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 177 rate_idx = rate->idx; 178 nss = 1 + (rate->idx >> 3); 179 phy = MT_PHY_TYPE_HT; 180 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 181 phy = MT_PHY_TYPE_HT_GF; 182 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 183 bw = 1; 184 } else { 185 const struct ieee80211_rate *r; 186 int band = dev->mt76.chandef.chan->band; 187 u16 val; 188 189 r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx]; 190 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 191 val = r->hw_value_short; 192 else 193 val = r->hw_value; 194 195 phy = val >> 8; 196 rate_idx = val & 0xff; 197 bw = 0; 198 } 199 200 rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx); 201 rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy); 202 rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw); 203 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 204 rateval |= MT_RXWI_RATE_SGI; 205 206 *nss_val = nss; 207 return cpu_to_le16(rateval); 208 } 209 210 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, 211 const struct ieee80211_tx_rate *rate) 212 { 213 spin_lock_bh(&dev->mt76.lock); 214 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 215 wcid->tx_rate_set = true; 216 spin_unlock_bh(&dev->mt76.lock); 217 } 218 219 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, 220 struct mt76x02_tx_status *stat) 221 { 222 u32 stat1, stat2; 223 224 stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 225 stat1 = mt76_rr(dev, MT_TX_STAT_FIFO); 226 227 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 228 if (!stat->valid) 229 return false; 230 231 stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS); 232 stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR); 233 stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ); 234 stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1); 235 stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1); 236 237 stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2); 238 stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2); 239 240 return true; 241 } 242 EXPORT_SYMBOL_GPL(mt76x02_mac_load_tx_status); 243 244 static int 245 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate, 246 enum nl80211_band band) 247 { 248 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 249 250 txrate->idx = 0; 251 txrate->flags = 0; 252 txrate->count = 1; 253 254 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 255 case MT_PHY_TYPE_OFDM: 256 if (band == NL80211_BAND_2GHZ) 257 idx += 4; 258 259 txrate->idx = idx; 260 return 0; 261 case MT_PHY_TYPE_CCK: 262 if (idx >= 8) 263 idx -= 8; 264 265 txrate->idx = idx; 266 return 0; 267 case MT_PHY_TYPE_HT_GF: 268 txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; 269 /* fall through */ 270 case MT_PHY_TYPE_HT: 271 txrate->flags |= IEEE80211_TX_RC_MCS; 272 txrate->idx = idx; 273 break; 274 case MT_PHY_TYPE_VHT: 275 txrate->flags |= IEEE80211_TX_RC_VHT_MCS; 276 txrate->idx = idx; 277 break; 278 default: 279 return -EINVAL; 280 } 281 282 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 283 case MT_PHY_BW_20: 284 break; 285 case MT_PHY_BW_40: 286 txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 287 break; 288 case MT_PHY_BW_80: 289 txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH; 290 break; 291 default: 292 return -EINVAL; 293 } 294 295 if (rate & MT_RXWI_RATE_SGI) 296 txrate->flags |= IEEE80211_TX_RC_SHORT_GI; 297 298 return 0; 299 } 300 301 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, 302 struct sk_buff *skb, struct mt76_wcid *wcid, 303 struct ieee80211_sta *sta, int len) 304 { 305 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 306 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 307 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 308 struct ieee80211_key_conf *key = info->control.hw_key; 309 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 310 u16 txwi_flags = 0; 311 u8 nss; 312 s8 txpwr_adj, max_txpwr_adj; 313 u8 ccmp_pn[8], nstreams = dev->mt76.chainmask & 0xf; 314 315 memset(txwi, 0, sizeof(*txwi)); 316 317 if (wcid) 318 txwi->wcid = wcid->idx; 319 else 320 txwi->wcid = 0xff; 321 322 txwi->pktid = 1; 323 324 if (wcid && wcid->sw_iv && key) { 325 u64 pn = atomic64_inc_return(&key->tx_pn); 326 ccmp_pn[0] = pn; 327 ccmp_pn[1] = pn >> 8; 328 ccmp_pn[2] = 0; 329 ccmp_pn[3] = 0x20 | (key->keyidx << 6); 330 ccmp_pn[4] = pn >> 16; 331 ccmp_pn[5] = pn >> 24; 332 ccmp_pn[6] = pn >> 32; 333 ccmp_pn[7] = pn >> 40; 334 txwi->iv = *((__le32 *)&ccmp_pn[0]); 335 txwi->eiv = *((__le32 *)&ccmp_pn[1]); 336 } 337 338 spin_lock_bh(&dev->mt76.lock); 339 if (wcid && (rate->idx < 0 || !rate->count)) { 340 txwi->rate = wcid->tx_rate; 341 max_txpwr_adj = wcid->max_txpwr_adj; 342 nss = wcid->tx_rate_nss; 343 } else { 344 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 345 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 346 } 347 spin_unlock_bh(&dev->mt76.lock); 348 349 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->mt76.txpower_conf, 350 max_txpwr_adj); 351 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 352 353 if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4) 354 txwi->txstream = 0x13; 355 else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 && 356 !(txwi->rate & cpu_to_le16(rate_ht_mask))) 357 txwi->txstream = 0x93; 358 359 if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC)) 360 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC); 361 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1) 362 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC); 363 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC) 364 txwi_flags |= MT_TXWI_FLAGS_MMPS; 365 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) 366 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; 367 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) 368 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; 369 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 370 txwi->pktid |= MT_TXWI_PKTID_PROBE; 371 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { 372 u8 ba_size = IEEE80211_MIN_AMPDU_BUF; 373 374 ba_size <<= sta->ht_cap.ampdu_factor; 375 ba_size = min_t(int, 63, ba_size - 1); 376 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) 377 ba_size = 0; 378 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); 379 380 txwi_flags |= MT_TXWI_FLAGS_AMPDU | 381 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, 382 sta->ht_cap.ampdu_density); 383 } 384 385 if (ieee80211_is_probe_resp(hdr->frame_control) || 386 ieee80211_is_beacon(hdr->frame_control)) 387 txwi_flags |= MT_TXWI_FLAGS_TS; 388 389 txwi->flags |= cpu_to_le16(txwi_flags); 390 txwi->len_ctl = cpu_to_le16(len); 391 } 392 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 393 394 static void 395 mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, 396 struct ieee80211_tx_info *info, 397 struct mt76x02_tx_status *st, int n_frames) 398 { 399 struct ieee80211_tx_rate *rate = info->status.rates; 400 int cur_idx, last_rate; 401 int i; 402 403 if (!n_frames) 404 return; 405 406 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 407 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 408 dev->mt76.chandef.chan->band); 409 if (last_rate < IEEE80211_TX_MAX_RATES - 1) 410 rate[last_rate + 1].idx = -1; 411 412 cur_idx = rate[last_rate].idx + last_rate; 413 for (i = 0; i <= last_rate; i++) { 414 rate[i].flags = rate[last_rate].flags; 415 rate[i].idx = max_t(int, 0, cur_idx - i); 416 rate[i].count = 1; 417 } 418 rate[last_rate].count = st->retry + 1 - last_rate; 419 420 info->status.ampdu_len = n_frames; 421 info->status.ampdu_ack_len = st->success ? n_frames : 0; 422 423 if (st->pktid & MT_TXWI_PKTID_PROBE) 424 info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE; 425 426 if (st->aggr) 427 info->flags |= IEEE80211_TX_CTL_AMPDU | 428 IEEE80211_TX_STAT_AMPDU; 429 430 if (!st->ack_req) 431 info->flags |= IEEE80211_TX_CTL_NO_ACK; 432 else if (st->success) 433 info->flags |= IEEE80211_TX_STAT_ACK; 434 } 435 436 void mt76x02_send_tx_status(struct mt76x02_dev *dev, 437 struct mt76x02_tx_status *stat, u8 *update) 438 { 439 struct ieee80211_tx_info info = {}; 440 struct ieee80211_sta *sta = NULL; 441 struct mt76_wcid *wcid = NULL; 442 struct mt76x02_sta *msta = NULL; 443 444 rcu_read_lock(); 445 if (stat->wcid < ARRAY_SIZE(dev->mt76.wcid)) 446 wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]); 447 448 if (wcid) { 449 void *priv; 450 451 priv = msta = container_of(wcid, struct mt76x02_sta, wcid); 452 sta = container_of(priv, struct ieee80211_sta, 453 drv_priv); 454 } 455 456 if (msta && stat->aggr) { 457 u32 stat_val, stat_cache; 458 459 stat_val = stat->rate; 460 stat_val |= ((u32) stat->retry) << 16; 461 stat_cache = msta->status.rate; 462 stat_cache |= ((u32) msta->status.retry) << 16; 463 464 if (*update == 0 && stat_val == stat_cache && 465 stat->wcid == msta->status.wcid && msta->n_frames < 32) { 466 msta->n_frames++; 467 goto out; 468 } 469 470 mt76x02_mac_fill_tx_status(dev, &info, &msta->status, 471 msta->n_frames); 472 473 msta->status = *stat; 474 msta->n_frames = 1; 475 *update = 0; 476 } else { 477 mt76x02_mac_fill_tx_status(dev, &info, stat, 1); 478 *update = 1; 479 } 480 481 ieee80211_tx_status_noskb(dev->mt76.hw, sta, &info); 482 483 out: 484 rcu_read_unlock(); 485 } 486 EXPORT_SYMBOL_GPL(mt76x02_send_tx_status); 487 488 int 489 mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate) 490 { 491 u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate); 492 493 switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) { 494 case MT_PHY_TYPE_OFDM: 495 if (idx >= 8) 496 idx = 0; 497 498 if (status->band == NL80211_BAND_2GHZ) 499 idx += 4; 500 501 status->rate_idx = idx; 502 return 0; 503 case MT_PHY_TYPE_CCK: 504 if (idx >= 8) { 505 idx -= 8; 506 status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 507 } 508 509 if (idx >= 4) 510 idx = 0; 511 512 status->rate_idx = idx; 513 return 0; 514 case MT_PHY_TYPE_HT_GF: 515 status->enc_flags |= RX_ENC_FLAG_HT_GF; 516 /* fall through */ 517 case MT_PHY_TYPE_HT: 518 status->encoding = RX_ENC_HT; 519 status->rate_idx = idx; 520 break; 521 case MT_PHY_TYPE_VHT: 522 status->encoding = RX_ENC_VHT; 523 status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx); 524 status->nss = FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1; 525 break; 526 default: 527 return -EINVAL; 528 } 529 530 if (rate & MT_RXWI_RATE_LDPC) 531 status->enc_flags |= RX_ENC_FLAG_LDPC; 532 533 if (rate & MT_RXWI_RATE_SGI) 534 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 535 536 if (rate & MT_RXWI_RATE_STBC) 537 status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT; 538 539 switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) { 540 case MT_PHY_BW_20: 541 break; 542 case MT_PHY_BW_40: 543 status->bw = RATE_INFO_BW_40; 544 break; 545 case MT_PHY_BW_80: 546 status->bw = RATE_INFO_BW_80; 547 break; 548 default: 549 break; 550 } 551 552 return 0; 553 } 554 EXPORT_SYMBOL_GPL(mt76x02_mac_process_rate); 555 556 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, u8 *addr) 557 { 558 ether_addr_copy(dev->mt76.macaddr, addr); 559 560 if (!is_valid_ether_addr(dev->mt76.macaddr)) { 561 eth_random_addr(dev->mt76.macaddr); 562 dev_info(dev->mt76.dev, 563 "Invalid MAC address, using random address %pM\n", 564 dev->mt76.macaddr); 565 } 566 567 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr)); 568 mt76_wr(dev, MT_MAC_ADDR_DW1, 569 get_unaligned_le16(dev->mt76.macaddr + 4) | 570 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 571 } 572 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 573 574 static int 575 mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain) 576 { 577 struct mt76x02_rx_freq_cal *cal = &dev->cal.rx; 578 579 rssi += cal->rssi_offset[chain]; 580 rssi -= cal->lna_gain; 581 582 return rssi; 583 } 584 585 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 586 void *rxi) 587 { 588 struct mt76_rx_status *status = (struct mt76_rx_status *) skb->cb; 589 struct mt76x02_rxwi *rxwi = rxi; 590 struct mt76x02_sta *sta; 591 u32 rxinfo = le32_to_cpu(rxwi->rxinfo); 592 u32 ctl = le32_to_cpu(rxwi->ctl); 593 u16 rate = le16_to_cpu(rxwi->rate); 594 u16 tid_sn = le16_to_cpu(rxwi->tid_sn); 595 bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST); 596 int i, pad_len = 0, nstreams = dev->mt76.chainmask & 0xf; 597 s8 signal; 598 u8 pn_len; 599 u8 wcid; 600 int len; 601 602 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 603 return -EINVAL; 604 605 if (rxinfo & MT_RXINFO_L2PAD) 606 pad_len += 2; 607 608 if (rxinfo & MT_RXINFO_DECRYPT) { 609 status->flag |= RX_FLAG_DECRYPTED; 610 status->flag |= RX_FLAG_MMIC_STRIPPED; 611 status->flag |= RX_FLAG_MIC_STRIPPED; 612 status->flag |= RX_FLAG_IV_STRIPPED; 613 } 614 615 wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl); 616 sta = mt76x02_rx_get_sta(&dev->mt76, wcid); 617 status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast); 618 619 len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl); 620 pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo); 621 if (pn_len) { 622 int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len; 623 u8 *data = skb->data + offset; 624 625 status->iv[0] = data[7]; 626 status->iv[1] = data[6]; 627 status->iv[2] = data[5]; 628 status->iv[3] = data[4]; 629 status->iv[4] = data[1]; 630 status->iv[5] = data[0]; 631 632 /* 633 * Driver CCMP validation can't deal with fragments. 634 * Let mac80211 take care of it. 635 */ 636 if (rxinfo & MT_RXINFO_FRAG) { 637 status->flag &= ~RX_FLAG_IV_STRIPPED; 638 } else { 639 pad_len += pn_len << 2; 640 len -= pn_len << 2; 641 } 642 } 643 644 mt76x02_remove_hdr_pad(skb, pad_len); 645 646 if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL)) 647 status->aggr = true; 648 649 if (WARN_ON_ONCE(len > skb->len)) 650 return -EINVAL; 651 652 pskb_trim(skb, len); 653 654 status->chains = BIT(0); 655 signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0); 656 for (i = 1; i < nstreams; i++) { 657 status->chains |= BIT(i); 658 status->chain_signal[i] = mt76x02_mac_get_rssi(dev, 659 rxwi->rssi[i], 660 i); 661 signal = max_t(s8, signal, status->chain_signal[i]); 662 } 663 status->signal = signal; 664 status->freq = dev->mt76.chandef.chan->center_freq; 665 status->band = dev->mt76.chandef.chan->band; 666 667 status->tid = FIELD_GET(MT_RXWI_TID, tid_sn); 668 status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn); 669 670 if (sta) { 671 ewma_signal_add(&sta->rssi, status->signal); 672 sta->inactive_count = 0; 673 } 674 675 return mt76x02_mac_process_rate(status, rate); 676 } 677 678 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq) 679 { 680 struct mt76x02_tx_status stat = {}; 681 unsigned long flags; 682 u8 update = 1; 683 bool ret; 684 685 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 686 return; 687 688 trace_mac_txstat_poll(dev); 689 690 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 691 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 692 ret = mt76x02_mac_load_tx_status(dev, &stat); 693 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 694 695 if (!ret) 696 break; 697 698 trace_mac_txstat_fetch(dev, &stat); 699 700 if (!irq) { 701 mt76x02_send_tx_status(dev, &stat, &update); 702 continue; 703 } 704 705 kfifo_put(&dev->txstatus_fifo, stat); 706 } 707 } 708 EXPORT_SYMBOL_GPL(mt76x02_mac_poll_tx_status); 709 710 static void 711 mt76x02_mac_queue_txdone(struct mt76x02_dev *dev, struct sk_buff *skb, 712 void *txwi_ptr) 713 { 714 struct mt76x02_tx_info *txi = mt76x02_skb_tx_info(skb); 715 struct mt76x02_txwi *txwi = txwi_ptr; 716 717 mt76x02_mac_poll_tx_status(dev, false); 718 719 txi->tries = 0; 720 txi->jiffies = jiffies; 721 txi->wcid = txwi->wcid; 722 txi->pktid = txwi->pktid; 723 trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid); 724 mt76x02_tx_complete(&dev->mt76, skb); 725 } 726 727 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q, 728 struct mt76_queue_entry *e, bool flush) 729 { 730 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); 731 732 if (e->txwi) 733 mt76x02_mac_queue_txdone(dev, e->skb, &e->txwi->txwi); 734 else 735 dev_kfree_skb_any(e->skb); 736 } 737 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb); 738