1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __MT76x02_EEPROM_H 19 #define __MT76x02_EEPROM_H 20 21 #include "mt76x02.h" 22 23 enum mt76x02_eeprom_field { 24 MT_EE_CHIP_ID = 0x000, 25 MT_EE_VERSION = 0x002, 26 MT_EE_MAC_ADDR = 0x004, 27 MT_EE_PCI_ID = 0x00A, 28 MT_EE_NIC_CONF_0 = 0x034, 29 MT_EE_NIC_CONF_1 = 0x036, 30 MT_EE_COUNTRY_REGION_5GHZ = 0x038, 31 MT_EE_COUNTRY_REGION_2GHZ = 0x039, 32 MT_EE_FREQ_OFFSET = 0x03a, 33 MT_EE_NIC_CONF_2 = 0x042, 34 35 MT_EE_XTAL_TRIM_1 = 0x03a, 36 MT_EE_XTAL_TRIM_2 = 0x09e, 37 38 MT_EE_LNA_GAIN = 0x044, 39 MT_EE_RSSI_OFFSET_2G_0 = 0x046, 40 MT_EE_RSSI_OFFSET_2G_1 = 0x048, 41 MT_EE_LNA_GAIN_5GHZ_1 = 0x049, 42 MT_EE_RSSI_OFFSET_5G_0 = 0x04a, 43 MT_EE_RSSI_OFFSET_5G_1 = 0x04c, 44 MT_EE_LNA_GAIN_5GHZ_2 = 0x04d, 45 46 MT_EE_TX_POWER_DELTA_BW40 = 0x050, 47 MT_EE_TX_POWER_DELTA_BW80 = 0x052, 48 49 MT_EE_TX_POWER_EXT_PA_5G = 0x054, 50 51 MT_EE_TX_POWER_0_START_2G = 0x056, 52 MT_EE_TX_POWER_1_START_2G = 0x05c, 53 54 /* used as byte arrays */ 55 #define MT_TX_POWER_GROUP_SIZE_5G 5 56 #define MT_TX_POWER_GROUPS_5G 6 57 MT_EE_TX_POWER_0_START_5G = 0x062, 58 59 MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x074, 60 MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x076, 61 62 MT_EE_TX_POWER_1_START_5G = 0x080, 63 64 MT_EE_TX_POWER_CCK = 0x0a0, 65 MT_EE_TX_POWER_OFDM_2G_6M = 0x0a2, 66 MT_EE_TX_POWER_OFDM_2G_24M = 0x0a4, 67 MT_EE_TX_POWER_OFDM_5G_6M = 0x0b2, 68 MT_EE_TX_POWER_OFDM_5G_24M = 0x0b4, 69 MT_EE_TX_POWER_HT_MCS0 = 0x0a6, 70 MT_EE_TX_POWER_HT_MCS4 = 0x0a8, 71 MT_EE_TX_POWER_HT_MCS8 = 0x0aa, 72 MT_EE_TX_POWER_HT_MCS12 = 0x0ac, 73 MT_EE_TX_POWER_VHT_MCS0 = 0x0ba, 74 MT_EE_TX_POWER_VHT_MCS4 = 0x0bc, 75 MT_EE_TX_POWER_VHT_MCS8 = 0x0be, 76 77 MT_EE_2G_TARGET_POWER = 0x0d0, 78 MT_EE_TEMP_OFFSET = 0x0d1, 79 MT_EE_5G_TARGET_POWER = 0x0d2, 80 MT_EE_TSSI_BOUND1 = 0x0d4, 81 MT_EE_TSSI_BOUND2 = 0x0d6, 82 MT_EE_TSSI_BOUND3 = 0x0d8, 83 MT_EE_TSSI_BOUND4 = 0x0da, 84 MT_EE_FREQ_OFFSET_COMPENSATION = 0x0db, 85 MT_EE_TSSI_BOUND5 = 0x0dc, 86 MT_EE_TX_POWER_BYRATE_BASE = 0x0de, 87 88 MT_EE_RF_TEMP_COMP_SLOPE_5G = 0x0f2, 89 MT_EE_RF_TEMP_COMP_SLOPE_2G = 0x0f4, 90 91 MT_EE_RF_2G_TSSI_OFF_TXPOWER = 0x0f6, 92 MT_EE_RF_2G_RX_HIGH_GAIN = 0x0f8, 93 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN = 0x0fa, 94 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN = 0x0fc, 95 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN = 0x0fe, 96 97 MT_EE_BT_RCAL_RESULT = 0x138, 98 MT_EE_BT_VCDL_CALIBRATION = 0x13c, 99 MT_EE_BT_PMUCFG = 0x13e, 100 101 MT_EE_USAGE_MAP_START = 0x1e0, 102 MT_EE_USAGE_MAP_END = 0x1fc, 103 104 __MT_EE_MAX 105 }; 106 107 #define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0) 108 #define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4) 109 #define MT_EE_NIC_CONF_0_PA_TYPE GENMASK(9, 8) 110 #define MT_EE_NIC_CONF_0_PA_INT_2G BIT(8) 111 #define MT_EE_NIC_CONF_0_PA_INT_5G BIT(9) 112 #define MT_EE_NIC_CONF_0_PA_IO_CURRENT BIT(10) 113 #define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12) 114 115 #define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0) 116 #define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1) 117 #define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2) 118 #define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3) 119 #define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13) 120 121 #define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0) 122 #define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4) 123 #define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8) 124 #define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9) 125 #define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11) 126 #define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13) 127 128 #define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \ 129 MT_EE_USAGE_MAP_START + 1) 130 131 enum mt76x02_eeprom_modes { 132 MT_EE_READ, 133 MT_EE_PHYSICAL_READ, 134 }; 135 136 enum mt76x02_board_type { 137 BOARD_TYPE_2GHZ = 1, 138 BOARD_TYPE_5GHZ = 2, 139 }; 140 141 static inline bool mt76x02_field_valid(u8 val) 142 { 143 return val != 0 && val != 0xff; 144 } 145 146 static inline int 147 mt76x02_sign_extend(u32 val, unsigned int size) 148 { 149 bool sign = val & BIT(size - 1); 150 151 val &= BIT(size - 1) - 1; 152 153 return sign ? val : -val; 154 } 155 156 static inline int 157 mt76x02_sign_extend_optional(u32 val, unsigned int size) 158 { 159 bool enable = val & BIT(size); 160 161 return enable ? mt76x02_sign_extend(val, size) : 0; 162 } 163 164 static inline s8 mt76x02_rate_power_val(u8 val) 165 { 166 if (!mt76x02_field_valid(val)) 167 return 0; 168 169 return mt76x02_sign_extend_optional(val, 7); 170 } 171 172 static inline int 173 mt76x02_eeprom_get(struct mt76x02_dev *dev, 174 enum mt76x02_eeprom_field field) 175 { 176 if ((field & 1) || field >= __MT_EE_MAX) 177 return -1; 178 179 return get_unaligned_le16(dev->mt76.eeprom.data + field); 180 } 181 182 bool mt76x02_ext_pa_enabled(struct mt76x02_dev *dev, enum nl80211_band band); 183 int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf, 184 int len, enum mt76x02_eeprom_modes mode); 185 void mt76x02_get_rx_gain(struct mt76x02_dev *dev, enum nl80211_band band, 186 u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g); 187 u8 mt76x02_get_lna_gain(struct mt76x02_dev *dev, 188 s8 *lna_2g, s8 *lna_5g, 189 struct ieee80211_channel *chan); 190 void mt76x02_eeprom_parse_hw_cap(struct mt76x02_dev *dev); 191 192 #endif /* __MT76x02_EEPROM_H */ 193