1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __MT76x02_H 19 #define __MT76x02_H 20 21 #include <linux/kfifo.h> 22 23 #include "mt76.h" 24 #include "mt76x02_regs.h" 25 #include "mt76x02_mac.h" 26 #include "mt76x02_dfs.h" 27 #include "mt76x02_dma.h" 28 29 #define MT_CALIBRATE_INTERVAL HZ 30 #define MT_MAC_WORK_INTERVAL (HZ / 10) 31 32 #define MT_WATCHDOG_TIME (HZ / 10) 33 #define MT_TX_HANG_TH 10 34 35 #define MT_MAX_CHAINS 2 36 struct mt76x02_rx_freq_cal { 37 s8 high_gain[MT_MAX_CHAINS]; 38 s8 rssi_offset[MT_MAX_CHAINS]; 39 s8 lna_gain; 40 u32 mcu_gain; 41 s16 temp_offset; 42 u8 freq_offset; 43 }; 44 45 struct mt76x02_calibration { 46 struct mt76x02_rx_freq_cal rx; 47 48 u8 agc_gain_init[MT_MAX_CHAINS]; 49 u8 agc_gain_cur[MT_MAX_CHAINS]; 50 51 u16 false_cca; 52 s8 avg_rssi_all; 53 s8 agc_gain_adjust; 54 s8 agc_lowest_gain; 55 s8 low_gain; 56 57 s8 temp_vco; 58 s8 temp; 59 60 bool init_cal_done; 61 bool tssi_cal_done; 62 bool tssi_comp_pending; 63 bool dpd_cal_done; 64 bool channel_cal_done; 65 bool gain_init_done; 66 67 int tssi_target; 68 s8 tssi_dc; 69 }; 70 71 struct mt76x02_dev { 72 struct mt76_dev mt76; /* must be first */ 73 74 struct mac_address macaddr_list[8]; 75 76 struct mutex phy_mutex; 77 78 u16 vif_mask; 79 80 u8 txdone_seq; 81 DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status); 82 83 struct sk_buff *rx_head; 84 85 struct tasklet_struct tx_tasklet; 86 struct tasklet_struct pre_tbtt_tasklet; 87 struct delayed_work cal_work; 88 struct delayed_work mac_work; 89 struct delayed_work wdt_work; 90 91 u32 aggr_stats[32]; 92 93 struct sk_buff *beacons[8]; 94 u8 beacon_mask; 95 u8 beacon_data_mask; 96 97 u8 tbtt_count; 98 u16 beacon_int; 99 100 u32 tx_hang_reset; 101 u8 tx_hang_check; 102 u8 mcu_timeout; 103 104 struct mt76x02_calibration cal; 105 106 s8 target_power; 107 s8 target_power_delta[2]; 108 bool enable_tpc; 109 110 bool no_2ghz; 111 112 u8 coverage_class; 113 u8 slottime; 114 115 struct mt76x02_dfs_pattern_detector dfs_pd; 116 117 /* edcca monitor */ 118 unsigned long ed_trigger_timeout; 119 bool ed_tx_blocked; 120 bool ed_monitor; 121 u8 ed_monitor_enabled; 122 u8 ed_monitor_learning; 123 u8 ed_trigger; 124 u8 ed_silent; 125 ktime_t ed_time; 126 }; 127 128 extern struct ieee80211_rate mt76x02_rates[12]; 129 130 void mt76x02_init_device(struct mt76x02_dev *dev); 131 void mt76x02_configure_filter(struct ieee80211_hw *hw, 132 unsigned int changed_flags, 133 unsigned int *total_flags, u64 multicast); 134 int mt76x02_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 135 struct ieee80211_sta *sta); 136 void mt76x02_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 137 struct ieee80211_sta *sta); 138 139 void mt76x02_config_mac_addr_list(struct mt76x02_dev *dev); 140 141 int mt76x02_add_interface(struct ieee80211_hw *hw, 142 struct ieee80211_vif *vif); 143 void mt76x02_remove_interface(struct ieee80211_hw *hw, 144 struct ieee80211_vif *vif); 145 146 int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 147 struct ieee80211_ampdu_params *params); 148 int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 149 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 150 struct ieee80211_key_conf *key); 151 int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 152 u16 queue, const struct ieee80211_tx_queue_params *params); 153 void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw, 154 struct ieee80211_vif *vif, 155 struct ieee80211_sta *sta); 156 s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev, 157 const struct ieee80211_tx_rate *rate); 158 s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr, 159 s8 max_txpwr_adj); 160 void mt76x02_wdt_work(struct work_struct *work); 161 void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr); 162 void mt76x02_set_tx_ackto(struct mt76x02_dev *dev); 163 void mt76x02_set_coverage_class(struct ieee80211_hw *hw, 164 s16 coverage_class); 165 int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val); 166 int mt76x02_insert_hdr_pad(struct sk_buff *skb); 167 void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len); 168 bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update); 169 void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 170 struct sk_buff *skb); 171 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q); 172 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance); 173 void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, 174 struct sk_buff *skb); 175 int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi, 176 struct sk_buff *skb, struct mt76_queue *q, 177 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 178 u32 *tx_info); 179 void mt76x02_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 180 const u8 *mac); 181 void mt76x02_sw_scan_complete(struct ieee80211_hw *hw, 182 struct ieee80211_vif *vif); 183 void mt76x02_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps); 184 void mt76x02_bss_info_changed(struct ieee80211_hw *hw, 185 struct ieee80211_vif *vif, 186 struct ieee80211_bss_conf *info, u32 changed); 187 188 extern const u16 mt76x02_beacon_offsets[16]; 189 void mt76x02_init_beacon_config(struct mt76x02_dev *dev); 190 void mt76x02_set_irq_mask(struct mt76x02_dev *dev, u32 clear, u32 set); 191 void mt76x02_mac_start(struct mt76x02_dev *dev); 192 193 void mt76x02_init_debugfs(struct mt76x02_dev *dev); 194 195 static inline bool is_mt76x0(struct mt76x02_dev *dev) 196 { 197 return mt76_chip(&dev->mt76) == 0x7610 || 198 mt76_chip(&dev->mt76) == 0x7630 || 199 mt76_chip(&dev->mt76) == 0x7650; 200 } 201 202 static inline bool is_mt76x2(struct mt76x02_dev *dev) 203 { 204 return mt76_chip(&dev->mt76) == 0x7612 || 205 mt76_chip(&dev->mt76) == 0x7662 || 206 mt76_chip(&dev->mt76) == 0x7602; 207 } 208 209 static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask) 210 { 211 mt76x02_set_irq_mask(dev, 0, mask); 212 } 213 214 static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask) 215 { 216 mt76x02_set_irq_mask(dev, mask, 0); 217 } 218 219 static inline bool 220 mt76x02_wait_for_txrx_idle(struct mt76_dev *dev) 221 { 222 return __mt76_poll_msec(dev, MT_MAC_STATUS, 223 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 224 0, 100); 225 } 226 227 static inline struct mt76x02_sta * 228 mt76x02_rx_get_sta(struct mt76_dev *dev, u8 idx) 229 { 230 struct mt76_wcid *wcid; 231 232 if (idx >= ARRAY_SIZE(dev->wcid)) 233 return NULL; 234 235 wcid = rcu_dereference(dev->wcid[idx]); 236 if (!wcid) 237 return NULL; 238 239 return container_of(wcid, struct mt76x02_sta, wcid); 240 } 241 242 static inline struct mt76_wcid * 243 mt76x02_rx_get_sta_wcid(struct mt76x02_sta *sta, bool unicast) 244 { 245 if (!sta) 246 return NULL; 247 248 if (unicast) 249 return &sta->wcid; 250 else 251 return &sta->vif->group_wcid; 252 } 253 254 #endif /* __MT76x02_H */ 255