1 /*
2  * (c) Copyright 2002-2010, Ralink Technology, Inc.
3  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 #ifndef _MT76X0_PHY_H_
15 #define _MT76X0_PHY_H_
16 
17 #define RF_G_BAND 	0x0100
18 #define RF_A_BAND 	0x0200
19 #define RF_A_BAND_LB	0x0400
20 #define RF_A_BAND_MB	0x0800
21 #define RF_A_BAND_HB	0x1000
22 #define RF_A_BAND_11J	0x2000
23 
24 #define RF_BW_20        1
25 #define RF_BW_40        2
26 #define RF_BW_10        4
27 #define RF_BW_80        8
28 
29 #define MT_RF(bank, reg) ((bank) << 16 | (reg))
30 #define MT_RF_BANK(offset) (offset >> 16)
31 #define MT_RF_REG(offset) (offset & 0xff)
32 
33 struct mt76x0_bbp_switch_item {
34 	u16 bw_band;
35 	struct mt76_reg_pair reg_pair;
36 };
37 
38 struct mt76x0_rf_switch_item {
39 	u32 rf_bank_reg;
40 	u16 bw_band;
41 	u8 value;
42 };
43 
44 struct mt76x0_freq_item {
45 	u8 channel;
46 	u32 band;
47 	u8 pllR37;
48 	u8 pllR36;
49 	u8 pllR35;
50 	u8 pllR34;
51 	u8 pllR33;
52 	u8 pllR32_b7b5;
53 	u8 pllR32_b4b0; /* PLL_DEN (Denomina - 8) */
54 	u8 pllR31_b7b5;
55 	u8 pllR31_b4b0; /* PLL_K (Nominator *)*/
56 	u8 pllR30_b7;	/* sdm_reset_n */
57 	u8 pllR30_b6b2; /* sdmmash_prbs,sin */
58 	u8 pllR30_b1;	/* sdm_bp */
59 	u16 pll_n;	/* R30<0>, R29<7:0> (hex) */
60 	u8 pllR28_b7b6; /* isi,iso */
61 	u8 pllR28_b5b4;	/* pfd_dly */
62 	u8 pllR28_b3b2;	/* clksel option */
63 	u32 pll_sdm_k;	/* R28<1:0>, R27<7:0>, R26<7:0> (hex) SDM_k */
64 	u8 pllR24_b1b0;	/* xo_div */
65 };
66 
67 struct mt76x0_rate_pwr_item {
68 	s8 mcs_power;
69 	u8 rf_pa_mode;
70 };
71 
72 struct mt76x0_rate_pwr_tab {
73 	struct mt76x0_rate_pwr_item cck[4];
74 	struct mt76x0_rate_pwr_item ofdm[8];
75 	struct mt76x0_rate_pwr_item ht[8];
76 	struct mt76x0_rate_pwr_item vht[10];
77 	struct mt76x0_rate_pwr_item stbc[8];
78 	struct mt76x0_rate_pwr_item mcs32;
79 };
80 
81 #endif /* _MT76X0_PHY_H_ */
82