1 /* 2 * (c) Copyright 2002-2010, Ralink Technology, Inc. 3 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #ifndef _MT76X0_PHY_H_ 15 #define _MT76X0_PHY_H_ 16 17 #define RF_G_BAND 0x0100 18 #define RF_A_BAND 0x0200 19 #define RF_A_BAND_LB 0x0400 20 #define RF_A_BAND_MB 0x0800 21 #define RF_A_BAND_HB 0x1000 22 #define RF_A_BAND_11J 0x2000 23 24 #define RF_BW_20 1 25 #define RF_BW_40 2 26 #define RF_BW_10 4 27 #define RF_BW_80 8 28 29 #define MT_RF(bank, reg) ((bank) << 16 | (reg)) 30 #define MT_RF_BANK(offset) (offset >> 16) 31 #define MT_RF_REG(offset) (offset & 0xff) 32 33 #define MT_RF_VCO_BP_CLOSE_LOOP BIT(3) 34 #define MT_RF_VCO_BP_CLOSE_LOOP_MASK GENMASK(3, 0) 35 #define MT_RF_VCO_CAL_MASK GENMASK(2, 0) 36 #define MT_RF_START_TIME 0x3 37 #define MT_RF_START_TIME_MASK GENMASK(2, 0) 38 #define MT_RF_SETTLE_TIME_MASK GENMASK(6, 4) 39 40 #define MT_RF_PLL_DEN_MASK GENMASK(4, 0) 41 #define MT_RF_PLL_K_MASK GENMASK(4, 0) 42 #define MT_RF_SDM_RESET_MASK BIT(7) 43 #define MT_RF_SDM_MASH_PRBS_MASK GENMASK(6, 2) 44 #define MT_RF_SDM_BP_MASK BIT(1) 45 #define MT_RF_ISI_ISO_MASK GENMASK(7, 6) 46 #define MT_RF_PFD_DLY_MASK GENMASK(5, 4) 47 #define MT_RF_CLK_SEL_MASK GENMASK(3, 2) 48 #define MT_RF_XO_DIV_MASK GENMASK(1, 0) 49 50 struct mt76x0_bbp_switch_item { 51 u16 bw_band; 52 struct mt76_reg_pair reg_pair; 53 }; 54 55 struct mt76x0_rf_switch_item { 56 u32 rf_bank_reg; 57 u16 bw_band; 58 u8 value; 59 }; 60 61 struct mt76x0_freq_item { 62 u8 channel; 63 u32 band; 64 u8 pllR37; 65 u8 pllR36; 66 u8 pllR35; 67 u8 pllR34; 68 u8 pllR33; 69 u8 pllR32_b7b5; 70 u8 pllR32_b4b0; /* PLL_DEN (Denomina - 8) */ 71 u8 pllR31_b7b5; 72 u8 pllR31_b4b0; /* PLL_K (Nominator *)*/ 73 u8 pllR30_b7; /* sdm_reset_n */ 74 u8 pllR30_b6b2; /* sdmmash_prbs,sin */ 75 u8 pllR30_b1; /* sdm_bp */ 76 u16 pll_n; /* R30<0>, R29<7:0> (hex) */ 77 u8 pllR28_b7b6; /* isi,iso */ 78 u8 pllR28_b5b4; /* pfd_dly */ 79 u8 pllR28_b3b2; /* clksel option */ 80 u32 pll_sdm_k; /* R28<1:0>, R27<7:0>, R26<7:0> (hex) SDM_k */ 81 u8 pllR24_b1b0; /* xo_div */ 82 }; 83 84 struct mt76x0_rate_pwr_item { 85 s8 mcs_power; 86 u8 rf_pa_mode; 87 }; 88 89 struct mt76x0_rate_pwr_tab { 90 struct mt76x0_rate_pwr_item cck[4]; 91 struct mt76x0_rate_pwr_item ofdm[8]; 92 struct mt76x0_rate_pwr_item ht[8]; 93 struct mt76x0_rate_pwr_item vht[10]; 94 struct mt76x0_rate_pwr_item stbc[8]; 95 struct mt76x0_rate_pwr_item mcs32; 96 }; 97 98 #endif /* _MT76X0_PHY_H_ */ 99