1 /* 2 * (c) Copyright 2002-2010, Ralink Technology, Inc. 3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 9 * as published by the Free Software Foundation 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/etherdevice.h> 19 20 #include "mt76x0.h" 21 #include "mcu.h" 22 #include "eeprom.h" 23 #include "trace.h" 24 #include "phy.h" 25 #include "initvals.h" 26 #include "initvals_phy.h" 27 #include "../mt76x02_phy.h" 28 29 static int 30 mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value) 31 { 32 int ret = 0; 33 u8 bank, reg; 34 35 if (test_bit(MT76_REMOVED, &dev->mt76.state)) 36 return -ENODEV; 37 38 bank = MT_RF_BANK(offset); 39 reg = MT_RF_REG(offset); 40 41 if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) 42 return -EINVAL; 43 44 mutex_lock(&dev->phy_mutex); 45 46 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { 47 ret = -ETIMEDOUT; 48 goto out; 49 } 50 51 mt76_wr(dev, MT_RF_CSR_CFG, 52 FIELD_PREP(MT_RF_CSR_CFG_DATA, value) | 53 FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | 54 FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | 55 MT_RF_CSR_CFG_WR | 56 MT_RF_CSR_CFG_KICK); 57 trace_mt76x0_rf_write(&dev->mt76, bank, offset, value); 58 out: 59 mutex_unlock(&dev->phy_mutex); 60 61 if (ret < 0) 62 dev_err(dev->mt76.dev, "Error: RF write %d:%d failed:%d!!\n", 63 bank, reg, ret); 64 65 return ret; 66 } 67 68 static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset) 69 { 70 int ret = -ETIMEDOUT; 71 u32 val; 72 u8 bank, reg; 73 74 if (test_bit(MT76_REMOVED, &dev->mt76.state)) 75 return -ENODEV; 76 77 bank = MT_RF_BANK(offset); 78 reg = MT_RF_REG(offset); 79 80 if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) 81 return -EINVAL; 82 83 mutex_lock(&dev->phy_mutex); 84 85 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) 86 goto out; 87 88 mt76_wr(dev, MT_RF_CSR_CFG, 89 FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | 90 FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | 91 MT_RF_CSR_CFG_KICK); 92 93 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) 94 goto out; 95 96 val = mt76_rr(dev, MT_RF_CSR_CFG); 97 if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == reg && 98 FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) { 99 ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val); 100 trace_mt76x0_rf_read(&dev->mt76, bank, offset, ret); 101 } 102 out: 103 mutex_unlock(&dev->phy_mutex); 104 105 if (ret < 0) 106 dev_err(dev->mt76.dev, "Error: RF read %d:%d failed:%d!!\n", 107 bank, reg, ret); 108 109 return ret; 110 } 111 112 static int 113 rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val) 114 { 115 if (mt76_is_usb(dev)) { 116 struct mt76_reg_pair pair = { 117 .reg = offset, 118 .value = val, 119 }; 120 121 WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING, 122 &dev->mt76.state)); 123 return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); 124 } else { 125 return mt76x0_rf_csr_wr(dev, offset, val); 126 } 127 } 128 129 static int 130 rf_rr(struct mt76x02_dev *dev, u32 offset) 131 { 132 int ret; 133 u32 val; 134 135 if (mt76_is_usb(dev)) { 136 struct mt76_reg_pair pair = { 137 .reg = offset, 138 }; 139 140 WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING, 141 &dev->mt76.state)); 142 ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); 143 val = pair.value; 144 } else { 145 ret = val = mt76x0_rf_csr_rr(dev, offset); 146 } 147 148 return (ret < 0) ? ret : val; 149 } 150 151 static int 152 rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val) 153 { 154 int ret; 155 156 ret = rf_rr(dev, offset); 157 if (ret < 0) 158 return ret; 159 val |= ret & ~mask; 160 ret = rf_wr(dev, offset, val); 161 if (ret) 162 return ret; 163 164 return val; 165 } 166 167 static int 168 rf_set(struct mt76x02_dev *dev, u32 offset, u8 val) 169 { 170 return rf_rmw(dev, offset, 0, val); 171 } 172 173 #if 0 174 static int 175 rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask) 176 { 177 return rf_rmw(dev, offset, mask, 0); 178 } 179 #endif 180 181 static void 182 mt76x0_rf_csr_wr_rp(struct mt76x02_dev *dev, const struct mt76_reg_pair *data, 183 int n) 184 { 185 while (n-- > 0) { 186 mt76x0_rf_csr_wr(dev, data->reg, data->value); 187 data++; 188 } 189 } 190 191 #define RF_RANDOM_WRITE(dev, tab) do { \ 192 if (mt76_is_mmio(dev)) \ 193 mt76x0_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \ 194 else \ 195 mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));\ 196 } while (0) 197 198 int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev) 199 { 200 int i = 20; 201 u32 val; 202 203 do { 204 val = mt76_rr(dev, MT_BBP(CORE, 0)); 205 if (val && ~val) 206 break; 207 } while (--i); 208 209 if (!i) { 210 dev_err(dev->mt76.dev, "Error: BBP is not ready\n"); 211 return -EIO; 212 } 213 214 dev_dbg(dev->mt76.dev, "BBP version %08x\n", val); 215 return 0; 216 } 217 218 static void mt76x0_vco_cal(struct mt76x02_dev *dev, u8 channel) 219 { 220 u8 val; 221 222 val = rf_rr(dev, MT_RF(0, 4)); 223 if ((val & 0x70) != 0x30) 224 return; 225 226 /* 227 * Calibration Mode - Open loop, closed loop, and amplitude: 228 * B0.R06.[0]: 1 229 * B0.R06.[3:1] bp_close_code: 100 230 * B0.R05.[7:0] bp_open_code: 0x0 231 * B0.R04.[2:0] cal_bits: 000 232 * B0.R03.[2:0] startup_time: 011 233 * B0.R03.[6:4] settle_time: 234 * 80MHz channel: 110 235 * 40MHz channel: 101 236 * 20MHz channel: 100 237 */ 238 val = rf_rr(dev, MT_RF(0, 6)); 239 val &= ~0xf; 240 val |= 0x09; 241 rf_wr(dev, MT_RF(0, 6), val); 242 243 val = rf_rr(dev, MT_RF(0, 5)); 244 if (val != 0) 245 rf_wr(dev, MT_RF(0, 5), 0x0); 246 247 val = rf_rr(dev, MT_RF(0, 4)); 248 val &= ~0x07; 249 rf_wr(dev, MT_RF(0, 4), val); 250 251 val = rf_rr(dev, MT_RF(0, 3)); 252 val &= ~0x77; 253 if (channel == 1 || channel == 7 || channel == 9 || channel >= 13) { 254 val |= 0x63; 255 } else if (channel == 3 || channel == 4 || channel == 10) { 256 val |= 0x53; 257 } else if (channel == 2 || channel == 5 || channel == 6 || 258 channel == 8 || channel == 11 || channel == 12) { 259 val |= 0x43; 260 } else { 261 WARN(1, "Unknown channel %u\n", channel); 262 return; 263 } 264 rf_wr(dev, MT_RF(0, 3), val); 265 266 /* TODO replace by mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7)); */ 267 val = rf_rr(dev, MT_RF(0, 4)); 268 val = ((val & ~(0x80)) | 0x80); 269 rf_wr(dev, MT_RF(0, 4), val); 270 271 msleep(2); 272 } 273 274 static void 275 mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band) 276 { 277 switch (band) { 278 case NL80211_BAND_2GHZ: 279 RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab); 280 281 rf_wr(dev, MT_RF(5, 0), 0x45); 282 rf_wr(dev, MT_RF(6, 0), 0x44); 283 284 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007); 285 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002); 286 break; 287 case NL80211_BAND_5GHZ: 288 RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab); 289 290 rf_wr(dev, MT_RF(5, 0), 0x44); 291 rf_wr(dev, MT_RF(6, 0), 0x45); 292 293 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005); 294 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102); 295 break; 296 default: 297 break; 298 } 299 } 300 301 static void 302 mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_band) 303 { 304 u16 rf_band = rf_bw_band & 0xff00; 305 u16 rf_bw = rf_bw_band & 0x00ff; 306 enum nl80211_band band; 307 u32 mac_reg; 308 u8 rf_val; 309 int i; 310 bool bSDM = false; 311 const struct mt76x0_freq_item *freq_item; 312 313 for (i = 0; i < ARRAY_SIZE(mt76x0_sdm_channel); i++) { 314 if (channel == mt76x0_sdm_channel[i]) { 315 bSDM = true; 316 break; 317 } 318 } 319 320 for (i = 0; i < ARRAY_SIZE(mt76x0_frequency_plan); i++) { 321 if (channel == mt76x0_frequency_plan[i].channel) { 322 rf_band = mt76x0_frequency_plan[i].band; 323 324 if (bSDM) 325 freq_item = &(mt76x0_sdm_frequency_plan[i]); 326 else 327 freq_item = &(mt76x0_frequency_plan[i]); 328 329 rf_wr(dev, MT_RF(0, 37), freq_item->pllR37); 330 rf_wr(dev, MT_RF(0, 36), freq_item->pllR36); 331 rf_wr(dev, MT_RF(0, 35), freq_item->pllR35); 332 rf_wr(dev, MT_RF(0, 34), freq_item->pllR34); 333 rf_wr(dev, MT_RF(0, 33), freq_item->pllR33); 334 335 rf_val = rf_rr(dev, MT_RF(0, 32)); 336 rf_val &= ~0xE0; 337 rf_val |= freq_item->pllR32_b7b5; 338 rf_wr(dev, MT_RF(0, 32), rf_val); 339 340 /* R32<4:0> pll_den: (Denomina - 8) */ 341 rf_val = rf_rr(dev, MT_RF(0, 32)); 342 rf_val &= ~0x1F; 343 rf_val |= freq_item->pllR32_b4b0; 344 rf_wr(dev, MT_RF(0, 32), rf_val); 345 346 /* R31<7:5> */ 347 rf_val = rf_rr(dev, MT_RF(0, 31)); 348 rf_val &= ~0xE0; 349 rf_val |= freq_item->pllR31_b7b5; 350 rf_wr(dev, MT_RF(0, 31), rf_val); 351 352 /* R31<4:0> pll_k(Nominator) */ 353 rf_val = rf_rr(dev, MT_RF(0, 31)); 354 rf_val &= ~0x1F; 355 rf_val |= freq_item->pllR31_b4b0; 356 rf_wr(dev, MT_RF(0, 31), rf_val); 357 358 /* R30<7> sdm_reset_n */ 359 rf_val = rf_rr(dev, MT_RF(0, 30)); 360 rf_val &= ~0x80; 361 if (bSDM) { 362 rf_wr(dev, MT_RF(0, 30), rf_val); 363 rf_val |= 0x80; 364 rf_wr(dev, MT_RF(0, 30), rf_val); 365 } else { 366 rf_val |= freq_item->pllR30_b7; 367 rf_wr(dev, MT_RF(0, 30), rf_val); 368 } 369 370 /* R30<6:2> sdmmash_prbs,sin */ 371 rf_val = rf_rr(dev, MT_RF(0, 30)); 372 rf_val &= ~0x7C; 373 rf_val |= freq_item->pllR30_b6b2; 374 rf_wr(dev, MT_RF(0, 30), rf_val); 375 376 /* R30<1> sdm_bp */ 377 rf_val = rf_rr(dev, MT_RF(0, 30)); 378 rf_val &= ~0x02; 379 rf_val |= (freq_item->pllR30_b1 << 1); 380 rf_wr(dev, MT_RF(0, 30), rf_val); 381 382 /* R30<0> R29<7:0> (hex) pll_n */ 383 rf_val = freq_item->pll_n & 0x00FF; 384 rf_wr(dev, MT_RF(0, 29), rf_val); 385 386 rf_val = rf_rr(dev, MT_RF(0, 30)); 387 rf_val &= ~0x1; 388 rf_val |= ((freq_item->pll_n >> 8) & 0x0001); 389 rf_wr(dev, MT_RF(0, 30), rf_val); 390 391 /* R28<7:6> isi_iso */ 392 rf_val = rf_rr(dev, MT_RF(0, 28)); 393 rf_val &= ~0xC0; 394 rf_val |= freq_item->pllR28_b7b6; 395 rf_wr(dev, MT_RF(0, 28), rf_val); 396 397 /* R28<5:4> pfd_dly */ 398 rf_val = rf_rr(dev, MT_RF(0, 28)); 399 rf_val &= ~0x30; 400 rf_val |= freq_item->pllR28_b5b4; 401 rf_wr(dev, MT_RF(0, 28), rf_val); 402 403 /* R28<3:2> clksel option */ 404 rf_val = rf_rr(dev, MT_RF(0, 28)); 405 rf_val &= ~0x0C; 406 rf_val |= freq_item->pllR28_b3b2; 407 rf_wr(dev, MT_RF(0, 28), rf_val); 408 409 /* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */ 410 rf_val = freq_item->pll_sdm_k & 0x000000FF; 411 rf_wr(dev, MT_RF(0, 26), rf_val); 412 413 rf_val = ((freq_item->pll_sdm_k >> 8) & 0x000000FF); 414 rf_wr(dev, MT_RF(0, 27), rf_val); 415 416 rf_val = rf_rr(dev, MT_RF(0, 28)); 417 rf_val &= ~0x3; 418 rf_val |= ((freq_item->pll_sdm_k >> 16) & 0x0003); 419 rf_wr(dev, MT_RF(0, 28), rf_val); 420 421 /* R24<1:0> xo_div */ 422 rf_val = rf_rr(dev, MT_RF(0, 24)); 423 rf_val &= ~0x3; 424 rf_val |= freq_item->pllR24_b1b0; 425 rf_wr(dev, MT_RF(0, 24), rf_val); 426 427 break; 428 } 429 } 430 431 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) { 432 if (rf_bw == mt76x0_rf_bw_switch_tab[i].bw_band) { 433 rf_wr(dev, mt76x0_rf_bw_switch_tab[i].rf_bank_reg, 434 mt76x0_rf_bw_switch_tab[i].value); 435 } else if ((rf_bw == (mt76x0_rf_bw_switch_tab[i].bw_band & 0xFF)) && 436 (rf_band & mt76x0_rf_bw_switch_tab[i].bw_band)) { 437 rf_wr(dev, mt76x0_rf_bw_switch_tab[i].rf_bank_reg, 438 mt76x0_rf_bw_switch_tab[i].value); 439 } 440 } 441 442 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) { 443 if (mt76x0_rf_band_switch_tab[i].bw_band & rf_band) { 444 rf_wr(dev, mt76x0_rf_band_switch_tab[i].rf_bank_reg, 445 mt76x0_rf_band_switch_tab[i].value); 446 } 447 } 448 449 mac_reg = mt76_rr(dev, MT_RF_MISC); 450 mac_reg &= ~0xC; /* Clear 0x518[3:2] */ 451 mt76_wr(dev, MT_RF_MISC, mac_reg); 452 453 band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 454 if (mt76x02_ext_pa_enabled(dev, band)) { 455 /* 456 MT_RF_MISC (offset: 0x0518) 457 [2]1'b1: enable external A band PA, 1'b0: disable external A band PA 458 [3]1'b1: enable external G band PA, 1'b0: disable external G band PA 459 */ 460 if (rf_band & RF_A_BAND) { 461 mac_reg = mt76_rr(dev, MT_RF_MISC); 462 mac_reg |= 0x4; 463 mt76_wr(dev, MT_RF_MISC, mac_reg); 464 } else { 465 mac_reg = mt76_rr(dev, MT_RF_MISC); 466 mac_reg |= 0x8; 467 mt76_wr(dev, MT_RF_MISC, mac_reg); 468 } 469 470 /* External PA */ 471 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++) 472 if (mt76x0_rf_ext_pa_tab[i].bw_band & rf_band) 473 rf_wr(dev, mt76x0_rf_ext_pa_tab[i].rf_bank_reg, 474 mt76x0_rf_ext_pa_tab[i].value); 475 } 476 477 if (rf_band & RF_G_BAND) { 478 mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x63707400); 479 /* Set Atten mode = 2 For G band, Disable Tx Inc dcoc. */ 480 mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1); 481 mac_reg &= 0x896400FF; 482 mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg); 483 } else { 484 mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x686A7800); 485 /* Set Atten mode = 0 For Ext A band, Disable Tx Inc dcoc Cal. */ 486 mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1); 487 mac_reg &= 0x890400FF; 488 mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg); 489 } 490 } 491 492 static void 493 mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u16 rf_bw_band) 494 { 495 int i; 496 497 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 498 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 499 const struct mt76_reg_pair *pair = &item->reg_pair; 500 501 if ((rf_bw_band & item->bw_band) != rf_bw_band) 502 continue; 503 504 if (pair->reg == MT_BBP(AGC, 8)) { 505 u32 val = pair->value; 506 u8 gain; 507 508 gain = FIELD_GET(MT_BBP_AGC_GAIN, val); 509 gain -= dev->cal.rx.lna_gain * 2; 510 val &= ~MT_BBP_AGC_GAIN; 511 val |= FIELD_PREP(MT_BBP_AGC_GAIN, gain); 512 mt76_wr(dev, pair->reg, val); 513 } else { 514 mt76_wr(dev, pair->reg, pair->value); 515 } 516 } 517 } 518 519 static void mt76x0_ant_select(struct mt76x02_dev *dev) 520 { 521 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 522 523 /* single antenna mode */ 524 if (chan->band == NL80211_BAND_2GHZ) { 525 mt76_rmw(dev, MT_COEXCFG3, 526 BIT(5) | BIT(4) | BIT(3) | BIT(2), BIT(1)); 527 mt76_rmw(dev, MT_WLAN_FUN_CTRL, BIT(5), BIT(6)); 528 } else { 529 mt76_rmw(dev, MT_COEXCFG3, BIT(5) | BIT(2), 530 BIT(4) | BIT(3)); 531 mt76_clear(dev, MT_WLAN_FUN_CTRL, 532 BIT(6) | BIT(5)); 533 } 534 mt76_clear(dev, MT_CMB_CTRL, BIT(14) | BIT(12)); 535 mt76_clear(dev, MT_COEXCFG0, BIT(2)); 536 } 537 538 static void 539 mt76x0_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width) 540 { 541 enum { BW_20 = 0, BW_40 = 1, BW_80 = 2, BW_10 = 4}; 542 int bw; 543 544 switch (width) { 545 default: 546 case NL80211_CHAN_WIDTH_20_NOHT: 547 case NL80211_CHAN_WIDTH_20: 548 bw = BW_20; 549 break; 550 case NL80211_CHAN_WIDTH_40: 551 bw = BW_40; 552 break; 553 case NL80211_CHAN_WIDTH_80: 554 bw = BW_80; 555 break; 556 case NL80211_CHAN_WIDTH_10: 557 bw = BW_10; 558 break; 559 case NL80211_CHAN_WIDTH_80P80: 560 case NL80211_CHAN_WIDTH_160: 561 case NL80211_CHAN_WIDTH_5: 562 /* TODO error */ 563 return ; 564 } 565 566 mt76x02_mcu_function_select(dev, BW_SETTING, bw, false); 567 } 568 569 void mt76x0_phy_set_txpower(struct mt76x02_dev *dev) 570 { 571 struct mt76_rate_power *t = &dev->mt76.rate_power; 572 u8 info[2]; 573 574 mt76x0_get_power_info(dev, info); 575 mt76x0_get_tx_power_per_rate(dev); 576 577 mt76x02_add_rate_power_offset(t, info[0]); 578 mt76x02_limit_rate_power(t, dev->mt76.txpower_conf); 579 dev->mt76.txpower_cur = mt76x02_get_max_rate_power(t); 580 mt76x02_add_rate_power_offset(t, -info[0]); 581 582 mt76x02_phy_set_txpower(dev, info[0], info[1]); 583 } 584 585 void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on) 586 { 587 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 588 u32 val, tx_alc, reg_val; 589 590 if (power_on) { 591 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0, false); 592 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, chan->hw_value, 593 false); 594 usleep_range(10, 20); 595 /* XXX: tssi */ 596 } 597 598 tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0); 599 mt76_wr(dev, MT_TX_ALC_CFG_0, 0); 600 usleep_range(500, 700); 601 602 reg_val = mt76_rr(dev, MT_BBP(IBI, 9)); 603 mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e); 604 605 if (chan->band == NL80211_BAND_5GHZ) { 606 if (chan->hw_value < 100) 607 val = 0x701; 608 else if (chan->hw_value < 140) 609 val = 0x801; 610 else 611 val = 0x901; 612 } else { 613 val = 0x600; 614 } 615 616 mt76x02_mcu_calibrate(dev, MCU_CAL_FULL, val, false); 617 msleep(350); 618 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, 1, false); 619 usleep_range(15000, 20000); 620 621 mt76_wr(dev, MT_BBP(IBI, 9), reg_val); 622 mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc); 623 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1, false); 624 } 625 EXPORT_SYMBOL_GPL(mt76x0_phy_calibrate); 626 627 int mt76x0_phy_set_channel(struct mt76x02_dev *dev, 628 struct cfg80211_chan_def *chandef) 629 { 630 u32 ext_cca_chan[4] = { 631 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | 632 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | 633 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | 634 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | 635 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), 636 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | 637 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | 638 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | 639 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | 640 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), 641 [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) | 642 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) | 643 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) | 644 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) | 645 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)), 646 [3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) | 647 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) | 648 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) | 649 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) | 650 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)), 651 }; 652 bool scan = test_bit(MT76_SCANNING, &dev->mt76.state); 653 int ch_group_index, freq, freq1; 654 u8 channel; 655 u32 val; 656 u16 rf_bw_band; 657 658 freq = chandef->chan->center_freq; 659 freq1 = chandef->center_freq1; 660 channel = chandef->chan->hw_value; 661 rf_bw_band = (channel <= 14) ? RF_G_BAND : RF_A_BAND; 662 dev->mt76.chandef = *chandef; 663 664 switch (chandef->width) { 665 case NL80211_CHAN_WIDTH_40: 666 if (freq1 > freq) 667 ch_group_index = 0; 668 else 669 ch_group_index = 1; 670 channel += 2 - ch_group_index * 4; 671 rf_bw_band |= RF_BW_40; 672 break; 673 case NL80211_CHAN_WIDTH_80: 674 ch_group_index = (freq - freq1 + 30) / 20; 675 if (WARN_ON(ch_group_index < 0 || ch_group_index > 3)) 676 ch_group_index = 0; 677 channel += 6 - ch_group_index * 4; 678 rf_bw_band |= RF_BW_80; 679 break; 680 default: 681 ch_group_index = 0; 682 rf_bw_band |= RF_BW_20; 683 break; 684 } 685 686 if (mt76_is_usb(dev)) { 687 mt76x0_bbp_set_bw(dev, chandef->width); 688 } else { 689 if (chandef->width == NL80211_CHAN_WIDTH_80 || 690 chandef->width == NL80211_CHAN_WIDTH_40) 691 val = 0x201; 692 else 693 val = 0x601; 694 mt76_wr(dev, MT_TX_SW_CFG0, val); 695 } 696 mt76x02_phy_set_bw(dev, chandef->width, ch_group_index); 697 mt76x02_phy_set_band(dev, chandef->chan->band, 698 ch_group_index & 1); 699 mt76x0_ant_select(dev); 700 701 mt76_rmw(dev, MT_EXT_CCA_CFG, 702 (MT_EXT_CCA_CFG_CCA0 | 703 MT_EXT_CCA_CFG_CCA1 | 704 MT_EXT_CCA_CFG_CCA2 | 705 MT_EXT_CCA_CFG_CCA3 | 706 MT_EXT_CCA_CFG_CCA_MASK), 707 ext_cca_chan[ch_group_index]); 708 709 mt76x0_phy_set_band(dev, chandef->chan->band); 710 mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band); 711 712 /* set Japan Tx filter at channel 14 */ 713 val = mt76_rr(dev, MT_BBP(CORE, 1)); 714 if (channel == 14) 715 val |= 0x20; 716 else 717 val &= ~0x20; 718 mt76_wr(dev, MT_BBP(CORE, 1), val); 719 720 mt76x0_read_rx_gain(dev); 721 mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band); 722 mt76x02_init_agc_gain(dev); 723 724 if (mt76_is_usb(dev)) { 725 mt76x0_vco_cal(dev, channel); 726 } else { 727 /* enable vco */ 728 rf_set(dev, MT_RF(0, 4), BIT(7)); 729 } 730 731 if (scan) 732 return 0; 733 734 if (mt76_is_mmio(dev)) 735 mt76x0_phy_calibrate(dev, false); 736 mt76x0_phy_set_txpower(dev); 737 738 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, 739 MT_CALIBRATE_INTERVAL); 740 741 return 0; 742 } 743 744 void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev) 745 { 746 u32 tx_alc, reg_val; 747 u8 channel = dev->mt76.chandef.chan->hw_value; 748 int is_5ghz = (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ) ? 1 : 0; 749 750 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0, false); 751 752 mt76x0_vco_cal(dev, channel); 753 754 tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0); 755 mt76_wr(dev, MT_TX_ALC_CFG_0, 0); 756 usleep_range(500, 700); 757 758 reg_val = mt76_rr(dev, MT_BBP(IBI, 9)); 759 mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e); 760 761 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 0, false); 762 763 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, is_5ghz, false); 764 mt76x02_mcu_calibrate(dev, MCU_CAL_LOFT, is_5ghz, false); 765 mt76x02_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz, false); 766 mt76x02_mcu_calibrate(dev, MCU_CAL_TX_GROUP_DELAY, is_5ghz, false); 767 mt76x02_mcu_calibrate(dev, MCU_CAL_RXIQ, is_5ghz, false); 768 mt76x02_mcu_calibrate(dev, MCU_CAL_RX_GROUP_DELAY, is_5ghz, false); 769 770 mt76_wr(dev, MT_BBP(IBI, 9), reg_val); 771 mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc); 772 msleep(100); 773 774 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1, false); 775 } 776 777 static void mt76x0_temp_sensor(struct mt76x02_dev *dev) 778 { 779 u8 rf_b7_73, rf_b0_66, rf_b0_67; 780 s8 val; 781 782 rf_b7_73 = rf_rr(dev, MT_RF(7, 73)); 783 rf_b0_66 = rf_rr(dev, MT_RF(0, 66)); 784 rf_b0_67 = rf_rr(dev, MT_RF(0, 67)); 785 786 rf_wr(dev, MT_RF(7, 73), 0x02); 787 rf_wr(dev, MT_RF(0, 66), 0x23); 788 rf_wr(dev, MT_RF(0, 67), 0x01); 789 790 mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055); 791 792 if (!mt76_poll(dev, MT_BBP(CORE, 34), BIT(4), 0, 2000)) { 793 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); 794 goto done; 795 } 796 797 val = mt76_rr(dev, MT_BBP(CORE, 35)); 798 val = (35 * (val - dev->cal.rx.temp_offset)) / 10 + 25; 799 800 if (abs(val - dev->cal.temp_vco) > 20) { 801 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, 802 dev->mt76.chandef.chan->hw_value, 803 false); 804 dev->cal.temp_vco = val; 805 } 806 if (abs(val - dev->cal.temp) > 30) { 807 mt76x0_phy_calibrate(dev, false); 808 dev->cal.temp = val; 809 } 810 811 done: 812 rf_wr(dev, MT_RF(7, 73), rf_b7_73); 813 rf_wr(dev, MT_RF(0, 66), rf_b0_66); 814 rf_wr(dev, MT_RF(0, 67), rf_b0_67); 815 } 816 817 static void mt76x0_phy_set_gain_val(struct mt76x02_dev *dev) 818 { 819 u8 gain = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust; 820 u32 val = 0x122c << 16 | 0xf2; 821 822 mt76_wr(dev, MT_BBP(AGC, 8), 823 val | FIELD_PREP(MT_BBP_AGC_GAIN, gain)); 824 } 825 826 static void 827 mt76x0_phy_update_channel_gain(struct mt76x02_dev *dev) 828 { 829 bool gain_change; 830 u8 gain_delta; 831 int low_gain; 832 833 dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(dev); 834 835 low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) + 836 (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev)); 837 838 gain_change = (dev->cal.low_gain & 2) ^ (low_gain & 2); 839 dev->cal.low_gain = low_gain; 840 841 if (!gain_change) { 842 if (mt76x02_phy_adjust_vga_gain(dev)) 843 mt76x0_phy_set_gain_val(dev); 844 return; 845 } 846 847 dev->cal.agc_gain_adjust = (low_gain == 2) ? 0 : 10; 848 gain_delta = (low_gain == 2) ? 10 : 0; 849 850 dev->cal.agc_gain_cur[0] = dev->cal.agc_gain_init[0] - gain_delta; 851 mt76x0_phy_set_gain_val(dev); 852 853 /* clear false CCA counters */ 854 mt76_rr(dev, MT_RX_STAT_1); 855 } 856 857 static void mt76x0_phy_calibration_work(struct work_struct *work) 858 { 859 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 860 cal_work.work); 861 862 mt76x0_phy_update_channel_gain(dev); 863 if (!mt76x0_tssi_enabled(dev)) 864 mt76x0_temp_sensor(dev); 865 866 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, 867 MT_CALIBRATE_INTERVAL); 868 } 869 870 static void mt76x0_rf_init(struct mt76x02_dev *dev) 871 { 872 int i; 873 u8 val; 874 875 RF_RANDOM_WRITE(dev, mt76x0_rf_central_tab); 876 RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab); 877 RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab); 878 RF_RANDOM_WRITE(dev, mt76x0_rf_vga_channel_0_tab); 879 880 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) { 881 const struct mt76x0_rf_switch_item *item = &mt76x0_rf_bw_switch_tab[i]; 882 883 if (item->bw_band == RF_BW_20) 884 rf_wr(dev, item->rf_bank_reg, item->value); 885 else if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 886 rf_wr(dev, item->rf_bank_reg, item->value); 887 } 888 889 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) { 890 if (mt76x0_rf_band_switch_tab[i].bw_band & RF_G_BAND) { 891 rf_wr(dev, 892 mt76x0_rf_band_switch_tab[i].rf_bank_reg, 893 mt76x0_rf_band_switch_tab[i].value); 894 } 895 } 896 897 /* 898 Frequency calibration 899 E1: B0.R22<6:0>: xo_cxo<6:0> 900 E2: B0.R21<0>: xo_cxo<0>, B0.R22<7:0>: xo_cxo<8:1> 901 */ 902 rf_wr(dev, MT_RF(0, 22), 903 min_t(u8, dev->cal.rx.freq_offset, 0xbf)); 904 val = rf_rr(dev, MT_RF(0, 22)); 905 906 /* 907 Reset the DAC (Set B0.R73<7>=1, then set B0.R73<7>=0, and then set B0.R73<7>) during power up. 908 */ 909 val = rf_rr(dev, MT_RF(0, 73)); 910 val |= 0x80; 911 rf_wr(dev, MT_RF(0, 73), val); 912 val &= ~0x80; 913 rf_wr(dev, MT_RF(0, 73), val); 914 val |= 0x80; 915 rf_wr(dev, MT_RF(0, 73), val); 916 917 /* 918 vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration. 919 */ 920 rf_set(dev, MT_RF(0, 4), 0x80); 921 } 922 923 void mt76x0_phy_init(struct mt76x02_dev *dev) 924 { 925 INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibration_work); 926 927 mt76x0_rf_init(dev); 928 mt76x02_phy_set_rxpath(dev); 929 mt76x02_phy_set_txdac(dev); 930 } 931