1 /* 2 * (c) Copyright 2002-2010, Ralink Technology, Inc. 3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 9 * as published by the Free Software Foundation 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/etherdevice.h> 19 20 #include "mt76x0.h" 21 #include "mcu.h" 22 #include "eeprom.h" 23 #include "phy.h" 24 #include "initvals.h" 25 #include "initvals_phy.h" 26 #include "../mt76x02_phy.h" 27 28 static int 29 mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value) 30 { 31 int ret = 0; 32 u8 bank, reg; 33 34 if (test_bit(MT76_REMOVED, &dev->mt76.state)) 35 return -ENODEV; 36 37 bank = MT_RF_BANK(offset); 38 reg = MT_RF_REG(offset); 39 40 if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) 41 return -EINVAL; 42 43 mutex_lock(&dev->phy_mutex); 44 45 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { 46 ret = -ETIMEDOUT; 47 goto out; 48 } 49 50 mt76_wr(dev, MT_RF_CSR_CFG, 51 FIELD_PREP(MT_RF_CSR_CFG_DATA, value) | 52 FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | 53 FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | 54 MT_RF_CSR_CFG_WR | 55 MT_RF_CSR_CFG_KICK); 56 57 out: 58 mutex_unlock(&dev->phy_mutex); 59 60 if (ret < 0) 61 dev_err(dev->mt76.dev, "Error: RF write %d:%d failed:%d!!\n", 62 bank, reg, ret); 63 64 return ret; 65 } 66 67 static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset) 68 { 69 int ret = -ETIMEDOUT; 70 u32 val; 71 u8 bank, reg; 72 73 if (test_bit(MT76_REMOVED, &dev->mt76.state)) 74 return -ENODEV; 75 76 bank = MT_RF_BANK(offset); 77 reg = MT_RF_REG(offset); 78 79 if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) 80 return -EINVAL; 81 82 mutex_lock(&dev->phy_mutex); 83 84 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) 85 goto out; 86 87 mt76_wr(dev, MT_RF_CSR_CFG, 88 FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | 89 FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | 90 MT_RF_CSR_CFG_KICK); 91 92 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) 93 goto out; 94 95 val = mt76_rr(dev, MT_RF_CSR_CFG); 96 if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == reg && 97 FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) 98 ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val); 99 100 out: 101 mutex_unlock(&dev->phy_mutex); 102 103 if (ret < 0) 104 dev_err(dev->mt76.dev, "Error: RF read %d:%d failed:%d!!\n", 105 bank, reg, ret); 106 107 return ret; 108 } 109 110 static int 111 mt76x0_rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val) 112 { 113 if (mt76_is_usb(dev)) { 114 struct mt76_reg_pair pair = { 115 .reg = offset, 116 .value = val, 117 }; 118 119 WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING, 120 &dev->mt76.state)); 121 return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); 122 } else { 123 return mt76x0_rf_csr_wr(dev, offset, val); 124 } 125 } 126 127 static int mt76x0_rf_rr(struct mt76x02_dev *dev, u32 offset) 128 { 129 int ret; 130 u32 val; 131 132 if (mt76_is_usb(dev)) { 133 struct mt76_reg_pair pair = { 134 .reg = offset, 135 }; 136 137 WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING, 138 &dev->mt76.state)); 139 ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); 140 val = pair.value; 141 } else { 142 ret = val = mt76x0_rf_csr_rr(dev, offset); 143 } 144 145 return (ret < 0) ? ret : val; 146 } 147 148 static int 149 mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val) 150 { 151 int ret; 152 153 ret = mt76x0_rf_rr(dev, offset); 154 if (ret < 0) 155 return ret; 156 157 val |= ret & ~mask; 158 159 ret = mt76x0_rf_wr(dev, offset, val); 160 return ret ? ret : val; 161 } 162 163 static int 164 mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val) 165 { 166 return mt76x0_rf_rmw(dev, offset, 0, val); 167 } 168 169 static int 170 mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask) 171 { 172 return mt76x0_rf_rmw(dev, offset, mask, 0); 173 } 174 175 static void 176 mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev, 177 const struct mt76_reg_pair *data, 178 int n) 179 { 180 while (n-- > 0) { 181 mt76x0_rf_csr_wr(dev, data->reg, data->value); 182 data++; 183 } 184 } 185 186 #define RF_RANDOM_WRITE(dev, tab) do { \ 187 if (mt76_is_mmio(dev)) \ 188 mt76x0_phy_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \ 189 else \ 190 mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));\ 191 } while (0) 192 193 int mt76x0_phy_wait_bbp_ready(struct mt76x02_dev *dev) 194 { 195 int i = 20; 196 u32 val; 197 198 do { 199 val = mt76_rr(dev, MT_BBP(CORE, 0)); 200 if (val && ~val) 201 break; 202 } while (--i); 203 204 if (!i) { 205 dev_err(dev->mt76.dev, "Error: BBP is not ready\n"); 206 return -EIO; 207 } 208 209 dev_dbg(dev->mt76.dev, "BBP version %08x\n", val); 210 return 0; 211 } 212 213 static void 214 mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band) 215 { 216 switch (band) { 217 case NL80211_BAND_2GHZ: 218 RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab); 219 220 mt76x0_rf_wr(dev, MT_RF(5, 0), 0x45); 221 mt76x0_rf_wr(dev, MT_RF(6, 0), 0x44); 222 223 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007); 224 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002); 225 break; 226 case NL80211_BAND_5GHZ: 227 RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab); 228 229 mt76x0_rf_wr(dev, MT_RF(5, 0), 0x44); 230 mt76x0_rf_wr(dev, MT_RF(6, 0), 0x45); 231 232 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005); 233 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102); 234 break; 235 default: 236 break; 237 } 238 } 239 240 static void 241 mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_band) 242 { 243 const struct mt76x0_freq_item *freq_item; 244 u16 rf_band = rf_bw_band & 0xff00; 245 u16 rf_bw = rf_bw_band & 0x00ff; 246 enum nl80211_band band; 247 bool b_sdm = false; 248 u32 mac_reg; 249 int i; 250 251 for (i = 0; i < ARRAY_SIZE(mt76x0_sdm_channel); i++) { 252 if (channel == mt76x0_sdm_channel[i]) { 253 b_sdm = true; 254 break; 255 } 256 } 257 258 for (i = 0; i < ARRAY_SIZE(mt76x0_frequency_plan); i++) { 259 if (channel == mt76x0_frequency_plan[i].channel) { 260 rf_band = mt76x0_frequency_plan[i].band; 261 262 if (b_sdm) 263 freq_item = &(mt76x0_sdm_frequency_plan[i]); 264 else 265 freq_item = &(mt76x0_frequency_plan[i]); 266 267 mt76x0_rf_wr(dev, MT_RF(0, 37), freq_item->pllR37); 268 mt76x0_rf_wr(dev, MT_RF(0, 36), freq_item->pllR36); 269 mt76x0_rf_wr(dev, MT_RF(0, 35), freq_item->pllR35); 270 mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34); 271 mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33); 272 273 mt76x0_rf_rmw(dev, MT_RF(0, 32), 0xe0, 274 freq_item->pllR32_b7b5); 275 276 /* R32<4:0> pll_den: (Denomina - 8) */ 277 mt76x0_rf_rmw(dev, MT_RF(0, 32), MT_RF_PLL_DEN_MASK, 278 freq_item->pllR32_b4b0); 279 280 /* R31<7:5> */ 281 mt76x0_rf_rmw(dev, MT_RF(0, 31), 0xe0, 282 freq_item->pllR31_b7b5); 283 284 /* R31<4:0> pll_k(Nominator) */ 285 mt76x0_rf_rmw(dev, MT_RF(0, 31), MT_RF_PLL_K_MASK, 286 freq_item->pllR31_b4b0); 287 288 /* R30<7> sdm_reset_n */ 289 if (b_sdm) { 290 mt76x0_rf_clear(dev, MT_RF(0, 30), 291 MT_RF_SDM_RESET_MASK); 292 mt76x0_rf_set(dev, MT_RF(0, 30), 293 MT_RF_SDM_RESET_MASK); 294 } else { 295 mt76x0_rf_rmw(dev, MT_RF(0, 30), 296 MT_RF_SDM_RESET_MASK, 297 freq_item->pllR30_b7); 298 } 299 300 /* R30<6:2> sdmmash_prbs,sin */ 301 mt76x0_rf_rmw(dev, MT_RF(0, 30), 302 MT_RF_SDM_MASH_PRBS_MASK, 303 freq_item->pllR30_b6b2); 304 305 /* R30<1> sdm_bp */ 306 mt76x0_rf_rmw(dev, MT_RF(0, 30), MT_RF_SDM_BP_MASK, 307 freq_item->pllR30_b1 << 1); 308 309 /* R30<0> R29<7:0> (hex) pll_n */ 310 mt76x0_rf_wr(dev, MT_RF(0, 29), 311 freq_item->pll_n & 0xff); 312 313 mt76x0_rf_rmw(dev, MT_RF(0, 30), 0x1, 314 (freq_item->pll_n >> 8) & 0x1); 315 316 /* R28<7:6> isi_iso */ 317 mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_ISI_ISO_MASK, 318 freq_item->pllR28_b7b6); 319 320 /* R28<5:4> pfd_dly */ 321 mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_PFD_DLY_MASK, 322 freq_item->pllR28_b5b4); 323 324 /* R28<3:2> clksel option */ 325 mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_CLK_SEL_MASK, 326 freq_item->pllR28_b3b2); 327 328 /* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */ 329 mt76x0_rf_wr(dev, MT_RF(0, 26), 330 freq_item->pll_sdm_k & 0xff); 331 mt76x0_rf_wr(dev, MT_RF(0, 27), 332 (freq_item->pll_sdm_k >> 8) & 0xff); 333 334 mt76x0_rf_rmw(dev, MT_RF(0, 28), 0x3, 335 (freq_item->pll_sdm_k >> 16) & 0x3); 336 337 /* R24<1:0> xo_div */ 338 mt76x0_rf_rmw(dev, MT_RF(0, 24), MT_RF_XO_DIV_MASK, 339 freq_item->pllR24_b1b0); 340 341 break; 342 } 343 } 344 345 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) { 346 if (rf_bw == mt76x0_rf_bw_switch_tab[i].bw_band) { 347 mt76x0_rf_wr(dev, 348 mt76x0_rf_bw_switch_tab[i].rf_bank_reg, 349 mt76x0_rf_bw_switch_tab[i].value); 350 } else if ((rf_bw == (mt76x0_rf_bw_switch_tab[i].bw_band & 0xFF)) && 351 (rf_band & mt76x0_rf_bw_switch_tab[i].bw_band)) { 352 mt76x0_rf_wr(dev, 353 mt76x0_rf_bw_switch_tab[i].rf_bank_reg, 354 mt76x0_rf_bw_switch_tab[i].value); 355 } 356 } 357 358 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) { 359 if (mt76x0_rf_band_switch_tab[i].bw_band & rf_band) { 360 mt76x0_rf_wr(dev, 361 mt76x0_rf_band_switch_tab[i].rf_bank_reg, 362 mt76x0_rf_band_switch_tab[i].value); 363 } 364 } 365 366 mt76_clear(dev, MT_RF_MISC, 0xc); 367 368 band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 369 if (mt76x02_ext_pa_enabled(dev, band)) { 370 /* 371 MT_RF_MISC (offset: 0x0518) 372 [2]1'b1: enable external A band PA, 1'b0: disable external A band PA 373 [3]1'b1: enable external G band PA, 1'b0: disable external G band PA 374 */ 375 if (rf_band & RF_A_BAND) 376 mt76_set(dev, MT_RF_MISC, BIT(2)); 377 else 378 mt76_set(dev, MT_RF_MISC, BIT(3)); 379 380 /* External PA */ 381 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++) 382 if (mt76x0_rf_ext_pa_tab[i].bw_band & rf_band) 383 mt76x0_rf_wr(dev, 384 mt76x0_rf_ext_pa_tab[i].rf_bank_reg, 385 mt76x0_rf_ext_pa_tab[i].value); 386 } 387 388 if (rf_band & RF_G_BAND) { 389 mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x63707400); 390 /* Set Atten mode = 2 For G band, Disable Tx Inc dcoc. */ 391 mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1); 392 mac_reg &= 0x896400FF; 393 mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg); 394 } else { 395 mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x686A7800); 396 /* Set Atten mode = 0 For Ext A band, Disable Tx Inc dcoc Cal. */ 397 mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1); 398 mac_reg &= 0x890400FF; 399 mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg); 400 } 401 } 402 403 static void 404 mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u16 rf_bw_band) 405 { 406 int i; 407 408 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 409 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 410 const struct mt76_reg_pair *pair = &item->reg_pair; 411 412 if ((rf_bw_band & item->bw_band) != rf_bw_band) 413 continue; 414 415 if (pair->reg == MT_BBP(AGC, 8)) { 416 u32 val = pair->value; 417 u8 gain; 418 419 gain = FIELD_GET(MT_BBP_AGC_GAIN, val); 420 gain -= dev->cal.rx.lna_gain * 2; 421 val &= ~MT_BBP_AGC_GAIN; 422 val |= FIELD_PREP(MT_BBP_AGC_GAIN, gain); 423 mt76_wr(dev, pair->reg, val); 424 } else { 425 mt76_wr(dev, pair->reg, pair->value); 426 } 427 } 428 } 429 430 static void mt76x0_phy_ant_select(struct mt76x02_dev *dev) 431 { 432 u16 ee_ant = mt76x02_eeprom_get(dev, MT_EE_ANTENNA); 433 u16 nic_conf2 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); 434 u32 wlan, coex3, cmb; 435 bool ant_div; 436 437 wlan = mt76_rr(dev, MT_WLAN_FUN_CTRL); 438 cmb = mt76_rr(dev, MT_CMB_CTRL); 439 coex3 = mt76_rr(dev, MT_COEXCFG3); 440 441 cmb &= ~(BIT(14) | BIT(12)); 442 wlan &= ~(BIT(6) | BIT(5)); 443 coex3 &= ~GENMASK(5, 2); 444 445 if (ee_ant & MT_EE_ANTENNA_DUAL) { 446 /* dual antenna mode */ 447 ant_div = !(nic_conf2 & MT_EE_NIC_CONF_2_ANT_OPT) && 448 (nic_conf2 & MT_EE_NIC_CONF_2_ANT_DIV); 449 if (ant_div) 450 cmb |= BIT(12); 451 else 452 coex3 |= BIT(4); 453 coex3 |= BIT(3); 454 if (dev->mt76.cap.has_2ghz) 455 wlan |= BIT(6); 456 } else { 457 /* sigle antenna mode */ 458 if (dev->mt76.cap.has_5ghz) { 459 coex3 |= BIT(3) | BIT(4); 460 } else { 461 wlan |= BIT(6); 462 coex3 |= BIT(1); 463 } 464 } 465 466 if (is_mt7630(dev)) 467 cmb |= BIT(14) | BIT(11); 468 469 mt76_wr(dev, MT_WLAN_FUN_CTRL, wlan); 470 mt76_wr(dev, MT_CMB_CTRL, cmb); 471 mt76_clear(dev, MT_COEXCFG0, BIT(2)); 472 mt76_wr(dev, MT_COEXCFG3, coex3); 473 } 474 475 static void 476 mt76x0_phy_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width) 477 { 478 enum { BW_20 = 0, BW_40 = 1, BW_80 = 2, BW_10 = 4}; 479 int bw; 480 481 switch (width) { 482 default: 483 case NL80211_CHAN_WIDTH_20_NOHT: 484 case NL80211_CHAN_WIDTH_20: 485 bw = BW_20; 486 break; 487 case NL80211_CHAN_WIDTH_40: 488 bw = BW_40; 489 break; 490 case NL80211_CHAN_WIDTH_80: 491 bw = BW_80; 492 break; 493 case NL80211_CHAN_WIDTH_10: 494 bw = BW_10; 495 break; 496 case NL80211_CHAN_WIDTH_80P80: 497 case NL80211_CHAN_WIDTH_160: 498 case NL80211_CHAN_WIDTH_5: 499 /* TODO error */ 500 return ; 501 } 502 503 mt76x02_mcu_function_select(dev, BW_SETTING, bw); 504 } 505 506 static void mt76x0_phy_tssi_dc_calibrate(struct mt76x02_dev *dev) 507 { 508 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 509 u32 val; 510 511 if (chan->band == NL80211_BAND_5GHZ) 512 mt76x0_rf_clear(dev, MT_RF(0, 67), 0xf); 513 514 /* bypass ADDA control */ 515 mt76_wr(dev, MT_RF_SETTING_0, 0x60002237); 516 mt76_wr(dev, MT_RF_BYPASS_0, 0xffffffff); 517 518 /* bbp sw reset */ 519 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); 520 usleep_range(500, 1000); 521 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); 522 523 val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050; 524 mt76_wr(dev, MT_BBP(CORE, 34), val); 525 526 /* enable TX with DAC0 input */ 527 mt76_wr(dev, MT_BBP(TXBE, 6), BIT(31)); 528 529 mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200); 530 dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; 531 532 /* stop bypass ADDA */ 533 mt76_wr(dev, MT_RF_BYPASS_0, 0); 534 /* stop TX */ 535 mt76_wr(dev, MT_BBP(TXBE, 6), 0); 536 /* bbp sw reset */ 537 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); 538 usleep_range(500, 1000); 539 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); 540 541 if (chan->band == NL80211_BAND_5GHZ) 542 mt76x0_rf_rmw(dev, MT_RF(0, 67), 0xf, 0x4); 543 } 544 545 static int 546 mt76x0_phy_tssi_adc_calibrate(struct mt76x02_dev *dev, s16 *ltssi, 547 u8 *info) 548 { 549 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 550 u32 val; 551 552 val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050; 553 mt76_wr(dev, MT_BBP(CORE, 34), val); 554 555 if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { 556 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); 557 return -ETIMEDOUT; 558 } 559 560 *ltssi = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; 561 if (chan->band == NL80211_BAND_5GHZ) 562 *ltssi += 128; 563 564 /* set packet info#1 mode */ 565 mt76_wr(dev, MT_BBP(CORE, 34), 0x80041); 566 info[0] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; 567 568 /* set packet info#2 mode */ 569 mt76_wr(dev, MT_BBP(CORE, 34), 0x80042); 570 info[1] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; 571 572 /* set packet info#3 mode */ 573 mt76_wr(dev, MT_BBP(CORE, 34), 0x80043); 574 info[2] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; 575 576 return 0; 577 } 578 579 static u8 mt76x0_phy_get_rf_pa_mode(struct mt76x02_dev *dev, 580 int index, u8 tx_rate) 581 { 582 u32 val, reg; 583 584 reg = (index == 1) ? MT_RF_PA_MODE_CFG1 : MT_RF_PA_MODE_CFG0; 585 val = mt76_rr(dev, reg); 586 return (val & (3 << (tx_rate * 2))) >> (tx_rate * 2); 587 } 588 589 static int 590 mt76x0_phy_get_target_power(struct mt76x02_dev *dev, u8 tx_mode, 591 u8 *info, s8 *target_power, 592 s8 *target_pa_power) 593 { 594 u8 tx_rate, cur_power; 595 596 cur_power = mt76_rr(dev, MT_TX_ALC_CFG_0) & MT_TX_ALC_CFG_0_CH_INIT_0; 597 switch (tx_mode) { 598 case 0: 599 /* cck rates */ 600 tx_rate = (info[0] & 0x60) >> 5; 601 if (tx_rate > 3) 602 return -EINVAL; 603 604 *target_power = cur_power + dev->mt76.rate_power.cck[tx_rate]; 605 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, tx_rate); 606 break; 607 case 1: { 608 u8 index; 609 610 /* ofdm rates */ 611 tx_rate = (info[0] & 0xf0) >> 4; 612 switch (tx_rate) { 613 case 0xb: 614 index = 0; 615 break; 616 case 0xf: 617 index = 1; 618 break; 619 case 0xa: 620 index = 2; 621 break; 622 case 0xe: 623 index = 3; 624 break; 625 case 0x9: 626 index = 4; 627 break; 628 case 0xd: 629 index = 5; 630 break; 631 case 0x8: 632 index = 6; 633 break; 634 case 0xc: 635 index = 7; 636 break; 637 default: 638 return -EINVAL; 639 } 640 641 *target_power = cur_power + dev->mt76.rate_power.ofdm[index]; 642 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, index + 4); 643 break; 644 } 645 case 4: 646 /* vht rates */ 647 tx_rate = info[1] & 0xf; 648 if (tx_rate > 9) 649 return -EINVAL; 650 651 *target_power = cur_power + dev->mt76.rate_power.vht[tx_rate]; 652 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate); 653 break; 654 default: 655 /* ht rates */ 656 tx_rate = info[1] & 0x7f; 657 if (tx_rate > 9) 658 return -EINVAL; 659 660 *target_power = cur_power + dev->mt76.rate_power.ht[tx_rate]; 661 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate); 662 break; 663 } 664 665 return 0; 666 } 667 668 static s16 mt76x0_phy_lin2db(u16 val) 669 { 670 u32 mantissa = val << 4; 671 int ret, data; 672 s16 exp = -4; 673 674 while (mantissa < BIT(15)) { 675 mantissa <<= 1; 676 if (--exp < -20) 677 return -10000; 678 } 679 while (mantissa > 0xffff) { 680 mantissa >>= 1; 681 if (++exp > 20) 682 return -10000; 683 } 684 685 /* s(15,0) */ 686 if (mantissa <= 47104) 687 data = mantissa + (mantissa >> 3) + (mantissa >> 4) - 38400; 688 else 689 data = mantissa - (mantissa >> 3) - (mantissa >> 6) - 23040; 690 data = max_t(int, 0, data); 691 692 ret = ((15 + exp) << 15) + data; 693 ret = (ret << 2) + (ret << 1) + (ret >> 6) + (ret >> 7); 694 return ret >> 10; 695 } 696 697 static int 698 mt76x0_phy_get_delta_power(struct mt76x02_dev *dev, u8 tx_mode, 699 s8 target_power, s8 target_pa_power, 700 s16 ltssi) 701 { 702 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 703 int tssi_target = target_power << 12, tssi_slope; 704 int tssi_offset, tssi_db, ret; 705 u32 data; 706 u16 val; 707 708 if (chan->band == NL80211_BAND_5GHZ) { 709 u8 bound[7]; 710 int i, err; 711 712 err = mt76x02_eeprom_copy(dev, MT_EE_TSSI_BOUND1, bound, 713 sizeof(bound)); 714 if (err < 0) 715 return err; 716 717 for (i = 0; i < ARRAY_SIZE(bound); i++) { 718 if (chan->hw_value <= bound[i] || !bound[i]) 719 break; 720 } 721 val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_5G + i * 2); 722 723 tssi_offset = val >> 8; 724 if ((tssi_offset >= 64 && tssi_offset <= 127) || 725 (tssi_offset & BIT(7))) 726 tssi_offset -= BIT(8); 727 } else { 728 val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_2G); 729 730 tssi_offset = val >> 8; 731 if (tssi_offset & BIT(7)) 732 tssi_offset -= BIT(8); 733 } 734 tssi_slope = val & 0xff; 735 736 switch (target_pa_power) { 737 case 1: 738 if (chan->band == NL80211_BAND_2GHZ) 739 tssi_target += 29491; /* 3.6 * 8192 */ 740 /* fall through */ 741 case 0: 742 break; 743 default: 744 tssi_target += 4424; /* 0.54 * 8192 */ 745 break; 746 } 747 748 if (!tx_mode) { 749 data = mt76_rr(dev, MT_BBP(CORE, 1)); 750 if (is_mt7630(dev) && mt76_is_mmio(dev)) { 751 int offset; 752 753 /* 2.3 * 8192 or 1.5 * 8192 */ 754 offset = (data & BIT(5)) ? 18841 : 12288; 755 tssi_target += offset; 756 } else if (data & BIT(5)) { 757 /* 0.8 * 8192 */ 758 tssi_target += 6554; 759 } 760 } 761 762 data = mt76_rr(dev, MT_BBP(TXBE, 4)); 763 switch (data & 0x3) { 764 case 1: 765 tssi_target -= 49152; /* -6db * 8192 */ 766 break; 767 case 2: 768 tssi_target -= 98304; /* -12db * 8192 */ 769 break; 770 case 3: 771 tssi_target += 49152; /* 6db * 8192 */ 772 break; 773 default: 774 break; 775 } 776 777 tssi_db = mt76x0_phy_lin2db(ltssi - dev->cal.tssi_dc) * tssi_slope; 778 if (chan->band == NL80211_BAND_5GHZ) { 779 tssi_db += ((tssi_offset - 50) << 10); /* offset s4.3 */ 780 tssi_target -= tssi_db; 781 if (ltssi > 254 && tssi_target > 0) { 782 /* upper saturate */ 783 tssi_target = 0; 784 } 785 } else { 786 tssi_db += (tssi_offset << 9); /* offset s3.4 */ 787 tssi_target -= tssi_db; 788 /* upper-lower saturate */ 789 if ((ltssi > 126 && tssi_target > 0) || 790 ((ltssi - dev->cal.tssi_dc) < 1 && tssi_target < 0)) { 791 tssi_target = 0; 792 } 793 } 794 795 if ((dev->cal.tssi_target ^ tssi_target) < 0 && 796 dev->cal.tssi_target > -4096 && dev->cal.tssi_target < 4096 && 797 tssi_target > -4096 && tssi_target < 4096) { 798 if ((tssi_target < 0 && 799 tssi_target + dev->cal.tssi_target > 0) || 800 (tssi_target > 0 && 801 tssi_target + dev->cal.tssi_target <= 0)) 802 tssi_target = 0; 803 else 804 dev->cal.tssi_target = tssi_target; 805 } else { 806 dev->cal.tssi_target = tssi_target; 807 } 808 809 /* make the compensate value to the nearest compensate code */ 810 if (tssi_target > 0) 811 tssi_target += 2048; 812 else 813 tssi_target -= 2048; 814 tssi_target >>= 12; 815 816 ret = mt76_get_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP); 817 if (ret & BIT(5)) 818 ret -= BIT(6); 819 ret += tssi_target; 820 821 ret = min_t(int, 31, ret); 822 return max_t(int, -32, ret); 823 } 824 825 static void mt76x0_phy_tssi_calibrate(struct mt76x02_dev *dev) 826 { 827 s8 target_power, target_pa_power; 828 u8 tssi_info[3], tx_mode; 829 s16 ltssi; 830 s8 val; 831 832 if (mt76x0_phy_tssi_adc_calibrate(dev, <ssi, tssi_info) < 0) 833 return; 834 835 tx_mode = tssi_info[0] & 0x7; 836 if (mt76x0_phy_get_target_power(dev, tx_mode, tssi_info, 837 &target_power, &target_pa_power) < 0) 838 return; 839 840 val = mt76x0_phy_get_delta_power(dev, tx_mode, target_power, 841 target_pa_power, ltssi); 842 mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, val); 843 } 844 845 void mt76x0_phy_set_txpower(struct mt76x02_dev *dev) 846 { 847 struct mt76_rate_power *t = &dev->mt76.rate_power; 848 u8 info[2]; 849 850 mt76x0_get_tx_power_per_rate(dev); 851 mt76x0_get_power_info(dev, info); 852 853 mt76x02_add_rate_power_offset(t, info[0]); 854 mt76x02_limit_rate_power(t, dev->mt76.txpower_conf); 855 dev->mt76.txpower_cur = mt76x02_get_max_rate_power(t); 856 mt76x02_add_rate_power_offset(t, -info[0]); 857 858 mt76x02_phy_set_txpower(dev, info[0], info[1]); 859 } 860 861 void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on) 862 { 863 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 864 int is_5ghz = (chan->band == NL80211_BAND_5GHZ) ? 1 : 0; 865 u32 val, tx_alc, reg_val; 866 867 if (is_mt7630(dev)) 868 return; 869 870 if (power_on) { 871 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0); 872 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, chan->hw_value); 873 usleep_range(10, 20); 874 875 if (mt76x0_tssi_enabled(dev)) { 876 mt76_wr(dev, MT_MAC_SYS_CTRL, 877 MT_MAC_SYS_CTRL_ENABLE_RX); 878 mt76x0_phy_tssi_dc_calibrate(dev); 879 mt76_wr(dev, MT_MAC_SYS_CTRL, 880 MT_MAC_SYS_CTRL_ENABLE_TX | 881 MT_MAC_SYS_CTRL_ENABLE_RX); 882 } 883 } 884 885 tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0); 886 mt76_wr(dev, MT_TX_ALC_CFG_0, 0); 887 usleep_range(500, 700); 888 889 reg_val = mt76_rr(dev, MT_BBP(IBI, 9)); 890 mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e); 891 892 if (is_5ghz) { 893 if (chan->hw_value < 100) 894 val = 0x701; 895 else if (chan->hw_value < 140) 896 val = 0x801; 897 else 898 val = 0x901; 899 } else { 900 val = 0x600; 901 } 902 903 mt76x02_mcu_calibrate(dev, MCU_CAL_FULL, val); 904 msleep(350); 905 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, is_5ghz); 906 usleep_range(15000, 20000); 907 908 mt76_wr(dev, MT_BBP(IBI, 9), reg_val); 909 mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc); 910 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1); 911 } 912 EXPORT_SYMBOL_GPL(mt76x0_phy_calibrate); 913 914 int mt76x0_phy_set_channel(struct mt76x02_dev *dev, 915 struct cfg80211_chan_def *chandef) 916 { 917 u32 ext_cca_chan[4] = { 918 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | 919 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | 920 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | 921 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | 922 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), 923 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | 924 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | 925 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | 926 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | 927 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), 928 [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) | 929 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) | 930 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) | 931 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) | 932 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)), 933 [3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) | 934 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) | 935 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) | 936 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) | 937 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)), 938 }; 939 bool scan = test_bit(MT76_SCANNING, &dev->mt76.state); 940 int ch_group_index, freq, freq1; 941 u8 channel; 942 u32 val; 943 u16 rf_bw_band; 944 945 freq = chandef->chan->center_freq; 946 freq1 = chandef->center_freq1; 947 channel = chandef->chan->hw_value; 948 rf_bw_band = (channel <= 14) ? RF_G_BAND : RF_A_BAND; 949 dev->mt76.chandef = *chandef; 950 951 switch (chandef->width) { 952 case NL80211_CHAN_WIDTH_40: 953 if (freq1 > freq) 954 ch_group_index = 0; 955 else 956 ch_group_index = 1; 957 channel += 2 - ch_group_index * 4; 958 rf_bw_band |= RF_BW_40; 959 break; 960 case NL80211_CHAN_WIDTH_80: 961 ch_group_index = (freq - freq1 + 30) / 20; 962 if (WARN_ON(ch_group_index < 0 || ch_group_index > 3)) 963 ch_group_index = 0; 964 channel += 6 - ch_group_index * 4; 965 rf_bw_band |= RF_BW_80; 966 break; 967 default: 968 ch_group_index = 0; 969 rf_bw_band |= RF_BW_20; 970 break; 971 } 972 973 if (mt76_is_usb(dev)) { 974 mt76x0_phy_bbp_set_bw(dev, chandef->width); 975 } else { 976 if (chandef->width == NL80211_CHAN_WIDTH_80 || 977 chandef->width == NL80211_CHAN_WIDTH_40) 978 val = 0x201; 979 else 980 val = 0x601; 981 mt76_wr(dev, MT_TX_SW_CFG0, val); 982 } 983 mt76x02_phy_set_bw(dev, chandef->width, ch_group_index); 984 mt76x02_phy_set_band(dev, chandef->chan->band, 985 ch_group_index & 1); 986 987 mt76_rmw(dev, MT_EXT_CCA_CFG, 988 (MT_EXT_CCA_CFG_CCA0 | 989 MT_EXT_CCA_CFG_CCA1 | 990 MT_EXT_CCA_CFG_CCA2 | 991 MT_EXT_CCA_CFG_CCA3 | 992 MT_EXT_CCA_CFG_CCA_MASK), 993 ext_cca_chan[ch_group_index]); 994 995 mt76x0_phy_set_band(dev, chandef->chan->band); 996 mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band); 997 998 /* set Japan Tx filter at channel 14 */ 999 if (channel == 14) 1000 mt76_set(dev, MT_BBP(CORE, 1), 0x20); 1001 else 1002 mt76_clear(dev, MT_BBP(CORE, 1), 0x20); 1003 1004 mt76x0_read_rx_gain(dev); 1005 mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band); 1006 1007 /* enable vco */ 1008 mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7)); 1009 if (scan) 1010 return 0; 1011 1012 mt76x02_init_agc_gain(dev); 1013 mt76x0_phy_calibrate(dev, false); 1014 mt76x0_phy_set_txpower(dev); 1015 1016 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, 1017 MT_CALIBRATE_INTERVAL); 1018 1019 return 0; 1020 } 1021 1022 static void mt76x0_phy_temp_sensor(struct mt76x02_dev *dev) 1023 { 1024 u8 rf_b7_73, rf_b0_66, rf_b0_67; 1025 s8 val; 1026 1027 rf_b7_73 = mt76x0_rf_rr(dev, MT_RF(7, 73)); 1028 rf_b0_66 = mt76x0_rf_rr(dev, MT_RF(0, 66)); 1029 rf_b0_67 = mt76x0_rf_rr(dev, MT_RF(0, 67)); 1030 1031 mt76x0_rf_wr(dev, MT_RF(7, 73), 0x02); 1032 mt76x0_rf_wr(dev, MT_RF(0, 66), 0x23); 1033 mt76x0_rf_wr(dev, MT_RF(0, 67), 0x01); 1034 1035 mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055); 1036 if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { 1037 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); 1038 goto done; 1039 } 1040 1041 val = mt76_rr(dev, MT_BBP(CORE, 35)); 1042 val = (35 * (val - dev->cal.rx.temp_offset)) / 10 + 25; 1043 1044 if (abs(val - dev->cal.temp_vco) > 20) { 1045 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, 1046 dev->mt76.chandef.chan->hw_value); 1047 dev->cal.temp_vco = val; 1048 } 1049 if (abs(val - dev->cal.temp) > 30) { 1050 mt76x0_phy_calibrate(dev, false); 1051 dev->cal.temp = val; 1052 } 1053 1054 done: 1055 mt76x0_rf_wr(dev, MT_RF(7, 73), rf_b7_73); 1056 mt76x0_rf_wr(dev, MT_RF(0, 66), rf_b0_66); 1057 mt76x0_rf_wr(dev, MT_RF(0, 67), rf_b0_67); 1058 } 1059 1060 static void mt76x0_phy_set_gain_val(struct mt76x02_dev *dev) 1061 { 1062 u8 gain = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust; 1063 1064 mt76_rmw_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN, gain); 1065 1066 if ((dev->mt76.chandef.chan->flags & IEEE80211_CHAN_RADAR) && 1067 !is_mt7630(dev)) 1068 mt76x02_phy_dfs_adjust_agc(dev); 1069 } 1070 1071 static void 1072 mt76x0_phy_update_channel_gain(struct mt76x02_dev *dev) 1073 { 1074 bool gain_change; 1075 u8 gain_delta; 1076 int low_gain; 1077 1078 dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(dev); 1079 1080 low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) + 1081 (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev)); 1082 1083 gain_change = dev->cal.low_gain < 0 || 1084 (dev->cal.low_gain & 2) ^ (low_gain & 2); 1085 dev->cal.low_gain = low_gain; 1086 1087 if (!gain_change) { 1088 if (mt76x02_phy_adjust_vga_gain(dev)) 1089 mt76x0_phy_set_gain_val(dev); 1090 return; 1091 } 1092 1093 dev->cal.agc_gain_adjust = (low_gain == 2) ? 0 : 10; 1094 gain_delta = (low_gain == 2) ? 10 : 0; 1095 1096 dev->cal.agc_gain_cur[0] = dev->cal.agc_gain_init[0] - gain_delta; 1097 mt76x0_phy_set_gain_val(dev); 1098 1099 /* clear false CCA counters */ 1100 mt76_rr(dev, MT_RX_STAT_1); 1101 } 1102 1103 static void mt76x0_phy_calibration_work(struct work_struct *work) 1104 { 1105 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 1106 cal_work.work); 1107 1108 mt76x0_phy_update_channel_gain(dev); 1109 if (mt76x0_tssi_enabled(dev)) 1110 mt76x0_phy_tssi_calibrate(dev); 1111 else 1112 mt76x0_phy_temp_sensor(dev); 1113 1114 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, 1115 4 * MT_CALIBRATE_INTERVAL); 1116 } 1117 1118 static void mt76x0_rf_patch_reg_array(struct mt76x02_dev *dev, 1119 const struct mt76_reg_pair *rp, int len) 1120 { 1121 int i; 1122 1123 for (i = 0; i < len; i++) { 1124 u32 reg = rp[i].reg; 1125 u8 val = rp[i].value; 1126 1127 switch (reg) { 1128 case MT_RF(0, 3): 1129 if (mt76_is_mmio(dev)) { 1130 if (is_mt7630(dev)) 1131 val = 0x70; 1132 else 1133 val = 0x63; 1134 } else { 1135 val = 0x73; 1136 } 1137 break; 1138 case MT_RF(0, 21): 1139 if (is_mt7610e(dev)) 1140 val = 0x10; 1141 else 1142 val = 0x12; 1143 break; 1144 case MT_RF(5, 2): 1145 if (is_mt7630(dev)) 1146 val = 0x1d; 1147 else if (is_mt7610e(dev)) 1148 val = 0x00; 1149 else 1150 val = 0x0c; 1151 break; 1152 default: 1153 break; 1154 } 1155 mt76x0_rf_wr(dev, reg, val); 1156 } 1157 } 1158 1159 static void mt76x0_phy_rf_init(struct mt76x02_dev *dev) 1160 { 1161 int i; 1162 u8 val; 1163 1164 mt76x0_rf_patch_reg_array(dev, mt76x0_rf_central_tab, 1165 ARRAY_SIZE(mt76x0_rf_central_tab)); 1166 mt76x0_rf_patch_reg_array(dev, mt76x0_rf_2g_channel_0_tab, 1167 ARRAY_SIZE(mt76x0_rf_2g_channel_0_tab)); 1168 RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab); 1169 RF_RANDOM_WRITE(dev, mt76x0_rf_vga_channel_0_tab); 1170 1171 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) { 1172 const struct mt76x0_rf_switch_item *item = &mt76x0_rf_bw_switch_tab[i]; 1173 1174 if (item->bw_band == RF_BW_20) 1175 mt76x0_rf_wr(dev, item->rf_bank_reg, item->value); 1176 else if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 1177 mt76x0_rf_wr(dev, item->rf_bank_reg, item->value); 1178 } 1179 1180 for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) { 1181 if (mt76x0_rf_band_switch_tab[i].bw_band & RF_G_BAND) { 1182 mt76x0_rf_wr(dev, 1183 mt76x0_rf_band_switch_tab[i].rf_bank_reg, 1184 mt76x0_rf_band_switch_tab[i].value); 1185 } 1186 } 1187 1188 /* 1189 Frequency calibration 1190 E1: B0.R22<6:0>: xo_cxo<6:0> 1191 E2: B0.R21<0>: xo_cxo<0>, B0.R22<7:0>: xo_cxo<8:1> 1192 */ 1193 mt76x0_rf_wr(dev, MT_RF(0, 22), 1194 min_t(u8, dev->cal.rx.freq_offset, 0xbf)); 1195 val = mt76x0_rf_rr(dev, MT_RF(0, 22)); 1196 1197 /* Reset procedure DAC during power-up: 1198 * - set B0.R73<7> 1199 * - clear B0.R73<7> 1200 * - set B0.R73<7> 1201 */ 1202 mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7)); 1203 mt76x0_rf_clear(dev, MT_RF(0, 73), BIT(7)); 1204 mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7)); 1205 1206 /* vcocal_en: initiate VCO calibration (reset after completion)) */ 1207 mt76x0_rf_set(dev, MT_RF(0, 4), 0x80); 1208 } 1209 1210 void mt76x0_phy_init(struct mt76x02_dev *dev) 1211 { 1212 INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibration_work); 1213 1214 mt76x0_phy_ant_select(dev); 1215 mt76x0_phy_rf_init(dev); 1216 mt76x02_phy_set_rxpath(dev); 1217 mt76x02_phy_set_txdac(dev); 1218 } 1219