1 /* 2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef MT76X0U_H 17 #define MT76X0U_H 18 19 #include <linux/bitfield.h> 20 #include <linux/kernel.h> 21 #include <linux/device.h> 22 #include <linux/mutex.h> 23 #include <linux/usb.h> 24 #include <linux/completion.h> 25 #include <net/mac80211.h> 26 #include <linux/debugfs.h> 27 28 #include "../mt76.h" 29 #include "../mt76x02_regs.h" 30 #include "../mt76x02_mac.h" 31 32 #define MT_CALIBRATE_INTERVAL (4 * HZ) 33 34 #define MT_FREQ_CAL_INIT_DELAY (30 * HZ) 35 #define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ) 36 #define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2) 37 38 #define MT_BBP_REG_VERSION 0x00 39 40 #define MT_USB_AGGR_SIZE_LIMIT 21 /* * 1024B */ 41 #define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */ 42 #define MT_RX_ORDER 3 43 #define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER) 44 45 struct mt76x0_dma_buf { 46 struct urb *urb; 47 void *buf; 48 dma_addr_t dma; 49 size_t len; 50 }; 51 52 struct mac_stats { 53 u64 rx_stat[6]; 54 u64 tx_stat[6]; 55 u64 aggr_stat[2]; 56 u64 aggr_n[32]; 57 u64 zero_len_del[2]; 58 }; 59 60 #define N_RX_ENTRIES 16 61 struct mt76x0_rx_queue { 62 struct mt76x0_dev *dev; 63 64 struct mt76x0_dma_buf_rx { 65 struct urb *urb; 66 struct page *p; 67 } e[N_RX_ENTRIES]; 68 69 unsigned int start; 70 unsigned int end; 71 unsigned int entries; 72 unsigned int pending; 73 }; 74 75 #define N_TX_ENTRIES 64 76 77 struct mt76x0_tx_queue { 78 struct mt76x0_dev *dev; 79 80 struct mt76x0_dma_buf_tx { 81 struct urb *urb; 82 struct sk_buff *skb; 83 } e[N_TX_ENTRIES]; 84 85 unsigned int start; 86 unsigned int end; 87 unsigned int entries; 88 unsigned int used; 89 unsigned int fifo_seq; 90 }; 91 92 struct mt76x0_eeprom_params; 93 94 #define MT_EE_TEMPERATURE_SLOPE 39 95 #define MT_FREQ_OFFSET_INVALID -128 96 97 /* addr req mask */ 98 #define MT_VEND_TYPE_EEPROM BIT(31) 99 #define MT_VEND_TYPE_CFG BIT(30) 100 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 101 102 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 103 104 enum mt_bw { 105 MT_BW_20, 106 MT_BW_40, 107 }; 108 109 /** 110 * struct mt76x0_dev - adapter structure 111 * @lock: protects @wcid->tx_rate. 112 * @mac_lock: locks out mac80211's tx status and rx paths. 113 * @tx_lock: protects @tx_q and changes of MT76_STATE_*_STATS 114 * flags in @state. 115 * @rx_lock: protects @rx_q. 116 * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. 117 * @mutex: ensures exclusive access from mac80211 callbacks. 118 * @reg_atomic_mutex: ensures atomicity of indirect register accesses 119 * (accesses to RF and BBP). 120 * @hw_atomic_mutex: ensures exclusive access to HW during critical 121 * operations (power management, channel switch). 122 */ 123 struct mt76x0_dev { 124 struct mt76_dev mt76; /* must be first */ 125 126 struct mutex usb_ctrl_mtx; 127 u8 data[32]; 128 129 struct tasklet_struct rx_tasklet; 130 struct tasklet_struct tx_tasklet; 131 132 u8 out_ep[__MT_EP_OUT_MAX]; 133 u16 out_max_packet; 134 u8 in_ep[__MT_EP_IN_MAX]; 135 u16 in_max_packet; 136 137 struct delayed_work cal_work; 138 struct delayed_work mac_work; 139 140 struct workqueue_struct *stat_wq; 141 struct delayed_work stat_work; 142 143 spinlock_t mac_lock; 144 145 const u16 *beacon_offsets; 146 147 u8 macaddr[ETH_ALEN]; 148 struct mt76x0_eeprom_params *ee; 149 150 struct mutex reg_atomic_mutex; 151 struct mutex hw_atomic_mutex; 152 153 u32 debugfs_reg; 154 155 /* TX */ 156 spinlock_t tx_lock; 157 struct mt76x0_tx_queue *tx_q; 158 struct sk_buff_head tx_skb_done; 159 160 atomic_t avg_ampdu_len; 161 162 /* RX */ 163 spinlock_t rx_lock; 164 struct mt76x0_rx_queue rx_q; 165 166 /* Connection monitoring things */ 167 spinlock_t con_mon_lock; 168 u8 ap_bssid[ETH_ALEN]; 169 170 s8 bcn_freq_off; 171 u8 bcn_phy_mode; 172 173 int avg_rssi; /* starts at 0 and converges */ 174 175 u8 agc_save; 176 u16 chainmask; 177 178 struct mac_stats stats; 179 }; 180 181 struct mt76x0_wcid { 182 u8 idx; 183 u8 hw_key_idx; 184 185 u16 tx_rate; 186 bool tx_rate_set; 187 u8 tx_rate_nss; 188 }; 189 190 extern const struct ieee80211_ops mt76x0_ops; 191 192 static inline bool is_mt7610e(struct mt76x0_dev *dev) 193 { 194 /* TODO */ 195 return false; 196 } 197 198 void mt76x0_init_debugfs(struct mt76x0_dev *dev); 199 200 /* Compatibility with mt76 */ 201 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 202 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 203 204 int mt76x0_write_reg_pairs(struct mt76x0_dev *dev, u32 base, 205 const struct mt76_reg_pair *data, int len); 206 int mt76x0_read_reg_pairs(struct mt76x0_dev *dev, u32 base, 207 struct mt76_reg_pair *data, int len); 208 int mt76x0_burst_write_regs(struct mt76x0_dev *dev, u32 offset, 209 const u32 *data, int n); 210 void mt76x0_addr_wr(struct mt76x0_dev *dev, const u32 offset, const u8 *addr); 211 212 /* Init */ 213 struct mt76x0_dev *mt76x0_alloc_device(struct device *dev); 214 int mt76x0_init_hardware(struct mt76x0_dev *dev); 215 int mt76x0_register_device(struct mt76x0_dev *dev); 216 void mt76x0_cleanup(struct mt76x0_dev *dev); 217 void mt76x0_chip_onoff(struct mt76x0_dev *dev, bool enable, bool reset); 218 219 int mt76x0_mac_start(struct mt76x0_dev *dev); 220 void mt76x0_mac_stop(struct mt76x0_dev *dev); 221 222 /* PHY */ 223 void mt76x0_phy_init(struct mt76x0_dev *dev); 224 int mt76x0_wait_bbp_ready(struct mt76x0_dev *dev); 225 void mt76x0_agc_save(struct mt76x0_dev *dev); 226 void mt76x0_agc_restore(struct mt76x0_dev *dev); 227 int mt76x0_phy_set_channel(struct mt76x0_dev *dev, 228 struct cfg80211_chan_def *chandef); 229 void mt76x0_phy_recalibrate_after_assoc(struct mt76x0_dev *dev); 230 int mt76x0_phy_get_rssi(struct mt76x0_dev *dev, struct mt76x02_rxwi *rxwi); 231 void mt76x0_phy_con_cal_onoff(struct mt76x0_dev *dev, 232 struct ieee80211_bss_conf *info); 233 234 /* MAC */ 235 void mt76x0_mac_work(struct work_struct *work); 236 void mt76x0_mac_set_protection(struct mt76x0_dev *dev, bool legacy_prot, 237 int ht_mode); 238 void mt76x0_mac_set_short_preamble(struct mt76x0_dev *dev, bool short_preamb); 239 void mt76x0_mac_config_tsf(struct mt76x0_dev *dev, bool enable, int interval); 240 void mt76x0_mac_set_ampdu_factor(struct mt76x0_dev *dev); 241 242 /* TX */ 243 void mt76x0_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, 244 struct sk_buff *skb); 245 void mt76x0_tx_status(struct mt76x0_dev *dev, struct sk_buff *skb); 246 void mt76x0_tx_stat(struct work_struct *work); 247 248 /* util */ 249 void mt76x0_remove_hdr_pad(struct sk_buff *skb); 250 int mt76x0_insert_hdr_pad(struct sk_buff *skb); 251 252 int mt76x0_dma_init(struct mt76x0_dev *dev); 253 void mt76x0_dma_cleanup(struct mt76x0_dev *dev); 254 255 int mt76x0_dma_enqueue_tx(struct mt76x0_dev *dev, struct sk_buff *skb, 256 struct mt76_wcid *wcid, int hw_q); 257 258 #endif 259