1 /* 2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef MT76X0U_H 17 #define MT76X0U_H 18 19 #include <linux/bitfield.h> 20 #include <linux/kernel.h> 21 #include <linux/device.h> 22 #include <linux/mutex.h> 23 #include <linux/usb.h> 24 #include <linux/completion.h> 25 #include <net/mac80211.h> 26 #include <linux/debugfs.h> 27 28 #include "../mt76.h" 29 #include "../mt76x02_regs.h" 30 #include "../mt76x02_mac.h" 31 32 #define MT_CALIBRATE_INTERVAL (4 * HZ) 33 34 #define MT_FREQ_CAL_INIT_DELAY (30 * HZ) 35 #define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ) 36 #define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2) 37 38 #define MT_BBP_REG_VERSION 0x00 39 40 #define MT_USB_AGGR_SIZE_LIMIT 21 /* * 1024B */ 41 #define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */ 42 #define MT_RX_ORDER 3 43 #define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER) 44 45 struct mt76x0_dma_buf { 46 struct urb *urb; 47 void *buf; 48 dma_addr_t dma; 49 size_t len; 50 }; 51 52 struct mac_stats { 53 u64 rx_stat[6]; 54 u64 tx_stat[6]; 55 u64 aggr_stat[2]; 56 u64 aggr_n[32]; 57 u64 zero_len_del[2]; 58 }; 59 60 #define N_RX_ENTRIES 16 61 struct mt76x0_rx_queue { 62 struct mt76x0_dev *dev; 63 64 struct mt76x0_dma_buf_rx { 65 struct urb *urb; 66 struct page *p; 67 } e[N_RX_ENTRIES]; 68 69 unsigned int start; 70 unsigned int end; 71 unsigned int entries; 72 unsigned int pending; 73 }; 74 75 #define N_TX_ENTRIES 64 76 77 struct mt76x0_tx_queue { 78 struct mt76x0_dev *dev; 79 80 struct mt76x0_dma_buf_tx { 81 struct urb *urb; 82 struct sk_buff *skb; 83 } e[N_TX_ENTRIES]; 84 85 unsigned int start; 86 unsigned int end; 87 unsigned int entries; 88 unsigned int used; 89 unsigned int fifo_seq; 90 }; 91 92 /* WCID allocation: 93 * 0: mcast wcid 94 * 1: bssid wcid 95 * 1...: STAs 96 * ...7e: group wcids 97 * 7f: reserved 98 */ 99 #define GROUP_WCID(idx) (254 - idx) 100 101 struct mt76x0_eeprom_params; 102 103 #define MT_EE_TEMPERATURE_SLOPE 39 104 #define MT_FREQ_OFFSET_INVALID -128 105 106 /* addr req mask */ 107 #define MT_VEND_TYPE_EEPROM BIT(31) 108 #define MT_VEND_TYPE_CFG BIT(30) 109 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 110 111 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 112 113 enum mt_bw { 114 MT_BW_20, 115 MT_BW_40, 116 }; 117 118 /** 119 * struct mt76x0_dev - adapter structure 120 * @lock: protects @wcid->tx_rate. 121 * @mac_lock: locks out mac80211's tx status and rx paths. 122 * @tx_lock: protects @tx_q and changes of MT76_STATE_*_STATS 123 * flags in @state. 124 * @rx_lock: protects @rx_q. 125 * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. 126 * @mutex: ensures exclusive access from mac80211 callbacks. 127 * @reg_atomic_mutex: ensures atomicity of indirect register accesses 128 * (accesses to RF and BBP). 129 * @hw_atomic_mutex: ensures exclusive access to HW during critical 130 * operations (power management, channel switch). 131 */ 132 struct mt76x0_dev { 133 struct mt76_dev mt76; /* must be first */ 134 135 struct mutex usb_ctrl_mtx; 136 u8 data[32]; 137 138 struct tasklet_struct rx_tasklet; 139 struct tasklet_struct tx_tasklet; 140 141 u8 out_ep[__MT_EP_OUT_MAX]; 142 u16 out_max_packet; 143 u8 in_ep[__MT_EP_IN_MAX]; 144 u16 in_max_packet; 145 146 unsigned long vif_mask; 147 148 struct delayed_work cal_work; 149 struct delayed_work mac_work; 150 151 struct workqueue_struct *stat_wq; 152 struct delayed_work stat_work; 153 154 spinlock_t mac_lock; 155 156 const u16 *beacon_offsets; 157 158 u8 macaddr[ETH_ALEN]; 159 struct mt76x0_eeprom_params *ee; 160 161 struct mutex reg_atomic_mutex; 162 struct mutex hw_atomic_mutex; 163 164 u32 debugfs_reg; 165 166 /* TX */ 167 spinlock_t tx_lock; 168 struct mt76x0_tx_queue *tx_q; 169 struct sk_buff_head tx_skb_done; 170 171 atomic_t avg_ampdu_len; 172 173 /* RX */ 174 spinlock_t rx_lock; 175 struct mt76x0_rx_queue rx_q; 176 177 /* Connection monitoring things */ 178 spinlock_t con_mon_lock; 179 u8 ap_bssid[ETH_ALEN]; 180 181 s8 bcn_freq_off; 182 u8 bcn_phy_mode; 183 184 int avg_rssi; /* starts at 0 and converges */ 185 186 u8 agc_save; 187 u16 chainmask; 188 189 struct mac_stats stats; 190 }; 191 192 struct mt76x0_wcid { 193 u8 idx; 194 u8 hw_key_idx; 195 196 u16 tx_rate; 197 bool tx_rate_set; 198 u8 tx_rate_nss; 199 }; 200 201 struct mt76x0_rxwi; 202 203 extern const struct ieee80211_ops mt76x0_ops; 204 205 static inline bool is_mt7610e(struct mt76x0_dev *dev) 206 { 207 /* TODO */ 208 return false; 209 } 210 211 void mt76x0_init_debugfs(struct mt76x0_dev *dev); 212 213 /* Compatibility with mt76 */ 214 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 215 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 216 217 int mt76x0_write_reg_pairs(struct mt76x0_dev *dev, u32 base, 218 const struct mt76_reg_pair *data, int len); 219 int mt76x0_read_reg_pairs(struct mt76x0_dev *dev, u32 base, 220 struct mt76_reg_pair *data, int len); 221 int mt76x0_burst_write_regs(struct mt76x0_dev *dev, u32 offset, 222 const u32 *data, int n); 223 void mt76x0_addr_wr(struct mt76x0_dev *dev, const u32 offset, const u8 *addr); 224 225 /* Init */ 226 struct mt76x0_dev *mt76x0_alloc_device(struct device *dev); 227 int mt76x0_init_hardware(struct mt76x0_dev *dev); 228 int mt76x0_register_device(struct mt76x0_dev *dev); 229 void mt76x0_cleanup(struct mt76x0_dev *dev); 230 void mt76x0_chip_onoff(struct mt76x0_dev *dev, bool enable, bool reset); 231 232 int mt76x0_mac_start(struct mt76x0_dev *dev); 233 void mt76x0_mac_stop(struct mt76x0_dev *dev); 234 235 /* PHY */ 236 void mt76x0_phy_init(struct mt76x0_dev *dev); 237 int mt76x0_wait_bbp_ready(struct mt76x0_dev *dev); 238 void mt76x0_agc_save(struct mt76x0_dev *dev); 239 void mt76x0_agc_restore(struct mt76x0_dev *dev); 240 int mt76x0_phy_set_channel(struct mt76x0_dev *dev, 241 struct cfg80211_chan_def *chandef); 242 void mt76x0_phy_recalibrate_after_assoc(struct mt76x0_dev *dev); 243 int mt76x0_phy_get_rssi(struct mt76x0_dev *dev, struct mt76x0_rxwi *rxwi); 244 void mt76x0_phy_con_cal_onoff(struct mt76x0_dev *dev, 245 struct ieee80211_bss_conf *info); 246 247 /* MAC */ 248 void mt76x0_mac_work(struct work_struct *work); 249 void mt76x0_mac_set_protection(struct mt76x0_dev *dev, bool legacy_prot, 250 int ht_mode); 251 void mt76x0_mac_set_short_preamble(struct mt76x0_dev *dev, bool short_preamb); 252 void mt76x0_mac_config_tsf(struct mt76x0_dev *dev, bool enable, int interval); 253 void mt76x0_mac_set_ampdu_factor(struct mt76x0_dev *dev); 254 255 /* TX */ 256 void mt76x0_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, 257 struct sk_buff *skb); 258 int mt76x0_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 259 u16 queue, const struct ieee80211_tx_queue_params *params); 260 void mt76x0_tx_status(struct mt76x0_dev *dev, struct sk_buff *skb); 261 void mt76x0_tx_stat(struct work_struct *work); 262 263 /* util */ 264 void mt76x0_remove_hdr_pad(struct sk_buff *skb); 265 int mt76x0_insert_hdr_pad(struct sk_buff *skb); 266 267 int mt76x0_dma_init(struct mt76x0_dev *dev); 268 void mt76x0_dma_cleanup(struct mt76x0_dev *dev); 269 270 int mt76x0_dma_enqueue_tx(struct mt76x0_dev *dev, struct sk_buff *skb, 271 struct mt76_wcid *wcid, int hw_q); 272 273 #endif 274