1 /* 2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef MT76X0U_H 17 #define MT76X0U_H 18 19 #include <linux/bitfield.h> 20 #include <linux/kernel.h> 21 #include <linux/device.h> 22 #include <linux/mutex.h> 23 #include <linux/usb.h> 24 #include <linux/completion.h> 25 #include <net/mac80211.h> 26 #include <linux/debugfs.h> 27 28 #include "../mt76.h" 29 #include "../mt76x02_regs.h" 30 #include "../mt76x02_mac.h" 31 32 #define MT_CALIBRATE_INTERVAL (4 * HZ) 33 34 #define MT_FREQ_CAL_INIT_DELAY (30 * HZ) 35 #define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ) 36 #define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2) 37 38 #define MT_BBP_REG_VERSION 0x00 39 40 #define MT_USB_AGGR_SIZE_LIMIT 21 /* * 1024B */ 41 #define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */ 42 #define MT_RX_ORDER 3 43 #define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER) 44 45 struct mt76x0_dma_buf { 46 struct urb *urb; 47 void *buf; 48 dma_addr_t dma; 49 size_t len; 50 }; 51 52 struct mt76x0_mcu { 53 struct mutex mutex; 54 55 u8 msg_seq; 56 57 struct mt76x0_dma_buf resp; 58 struct completion resp_cmpl; 59 60 struct mt76_reg_pair *reg_pairs; 61 unsigned int reg_pairs_len; 62 u32 reg_base; 63 bool burst_read; 64 }; 65 66 struct mac_stats { 67 u64 rx_stat[6]; 68 u64 tx_stat[6]; 69 u64 aggr_stat[2]; 70 u64 aggr_n[32]; 71 u64 zero_len_del[2]; 72 }; 73 74 #define N_RX_ENTRIES 16 75 struct mt76x0_rx_queue { 76 struct mt76x0_dev *dev; 77 78 struct mt76x0_dma_buf_rx { 79 struct urb *urb; 80 struct page *p; 81 } e[N_RX_ENTRIES]; 82 83 unsigned int start; 84 unsigned int end; 85 unsigned int entries; 86 unsigned int pending; 87 }; 88 89 #define N_TX_ENTRIES 64 90 91 struct mt76x0_tx_queue { 92 struct mt76x0_dev *dev; 93 94 struct mt76x0_dma_buf_tx { 95 struct urb *urb; 96 struct sk_buff *skb; 97 } e[N_TX_ENTRIES]; 98 99 unsigned int start; 100 unsigned int end; 101 unsigned int entries; 102 unsigned int used; 103 unsigned int fifo_seq; 104 }; 105 106 /* WCID allocation: 107 * 0: mcast wcid 108 * 1: bssid wcid 109 * 1...: STAs 110 * ...7e: group wcids 111 * 7f: reserved 112 */ 113 #define N_WCIDS 128 114 #define GROUP_WCID(idx) (254 - idx) 115 116 struct mt76x0_eeprom_params; 117 118 #define MT_EE_TEMPERATURE_SLOPE 39 119 #define MT_FREQ_OFFSET_INVALID -128 120 121 /* addr req mask */ 122 #define MT_VEND_TYPE_EEPROM BIT(31) 123 #define MT_VEND_TYPE_CFG BIT(30) 124 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 125 126 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 127 128 enum mt_bw { 129 MT_BW_20, 130 MT_BW_40, 131 }; 132 133 /** 134 * struct mt76x0_dev - adapter structure 135 * @lock: protects @wcid->tx_rate. 136 * @mac_lock: locks out mac80211's tx status and rx paths. 137 * @tx_lock: protects @tx_q and changes of MT76_STATE_*_STATS 138 * flags in @state. 139 * @rx_lock: protects @rx_q. 140 * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. 141 * @mutex: ensures exclusive access from mac80211 callbacks. 142 * @reg_atomic_mutex: ensures atomicity of indirect register accesses 143 * (accesses to RF and BBP). 144 * @hw_atomic_mutex: ensures exclusive access to HW during critical 145 * operations (power management, channel switch). 146 */ 147 struct mt76x0_dev { 148 struct mt76_dev mt76; /* must be first */ 149 150 struct mutex usb_ctrl_mtx; 151 u8 data[32]; 152 153 struct tasklet_struct rx_tasklet; 154 struct tasklet_struct tx_tasklet; 155 156 u8 out_ep[__MT_EP_OUT_MAX]; 157 u16 out_max_packet; 158 u8 in_ep[__MT_EP_IN_MAX]; 159 u16 in_max_packet; 160 161 unsigned long wcid_mask[DIV_ROUND_UP(N_WCIDS, BITS_PER_LONG)]; 162 unsigned long vif_mask; 163 164 struct mt76x0_mcu mcu; 165 166 struct delayed_work cal_work; 167 struct delayed_work mac_work; 168 169 struct workqueue_struct *stat_wq; 170 struct delayed_work stat_work; 171 172 struct mt76_wcid *mon_wcid; 173 struct mt76_wcid __rcu *wcid[N_WCIDS]; 174 175 spinlock_t mac_lock; 176 177 const u16 *beacon_offsets; 178 179 u8 macaddr[ETH_ALEN]; 180 struct mt76x0_eeprom_params *ee; 181 182 struct mutex reg_atomic_mutex; 183 struct mutex hw_atomic_mutex; 184 185 u32 debugfs_reg; 186 187 /* TX */ 188 spinlock_t tx_lock; 189 struct mt76x0_tx_queue *tx_q; 190 struct sk_buff_head tx_skb_done; 191 192 atomic_t avg_ampdu_len; 193 194 /* RX */ 195 spinlock_t rx_lock; 196 struct mt76x0_rx_queue rx_q; 197 198 /* Connection monitoring things */ 199 spinlock_t con_mon_lock; 200 u8 ap_bssid[ETH_ALEN]; 201 202 s8 bcn_freq_off; 203 u8 bcn_phy_mode; 204 205 int avg_rssi; /* starts at 0 and converges */ 206 207 u8 agc_save; 208 u16 chainmask; 209 210 struct mac_stats stats; 211 }; 212 213 struct mt76x0_wcid { 214 u8 idx; 215 u8 hw_key_idx; 216 217 u16 tx_rate; 218 bool tx_rate_set; 219 u8 tx_rate_nss; 220 }; 221 222 struct mt76_vif { 223 u8 idx; 224 225 struct mt76_wcid group_wcid; 226 }; 227 228 struct mt76_tx_status { 229 u8 valid:1; 230 u8 success:1; 231 u8 aggr:1; 232 u8 ack_req:1; 233 u8 is_probe:1; 234 u8 wcid; 235 u8 pktid; 236 u8 retry; 237 u16 rate; 238 } __packed __aligned(2); 239 240 struct mt76_sta { 241 struct mt76_wcid wcid; 242 struct mt76_tx_status status; 243 int n_frames; 244 u16 agg_ssn[IEEE80211_NUM_TIDS]; 245 }; 246 247 struct mt76_reg_pair { 248 u32 reg; 249 u32 value; 250 }; 251 252 struct mt76x0_rxwi; 253 254 extern const struct ieee80211_ops mt76x0_ops; 255 256 static inline bool is_mt7610e(struct mt76x0_dev *dev) 257 { 258 /* TODO */ 259 return false; 260 } 261 262 void mt76x0_init_debugfs(struct mt76x0_dev *dev); 263 264 /* Compatibility with mt76 */ 265 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 266 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 267 268 int mt76x0_write_reg_pairs(struct mt76x0_dev *dev, u32 base, 269 const struct mt76_reg_pair *data, int len); 270 int mt76x0_read_reg_pairs(struct mt76x0_dev *dev, u32 base, 271 struct mt76_reg_pair *data, int len); 272 int mt76x0_burst_write_regs(struct mt76x0_dev *dev, u32 offset, 273 const u32 *data, int n); 274 void mt76x0_addr_wr(struct mt76x0_dev *dev, const u32 offset, const u8 *addr); 275 276 /* Init */ 277 struct mt76x0_dev *mt76x0_alloc_device(struct device *dev); 278 int mt76x0_init_hardware(struct mt76x0_dev *dev); 279 int mt76x0_register_device(struct mt76x0_dev *dev); 280 void mt76x0_cleanup(struct mt76x0_dev *dev); 281 void mt76x0_chip_onoff(struct mt76x0_dev *dev, bool enable, bool reset); 282 283 int mt76x0_mac_start(struct mt76x0_dev *dev); 284 void mt76x0_mac_stop(struct mt76x0_dev *dev); 285 286 /* PHY */ 287 void mt76x0_phy_init(struct mt76x0_dev *dev); 288 int mt76x0_wait_bbp_ready(struct mt76x0_dev *dev); 289 void mt76x0_agc_save(struct mt76x0_dev *dev); 290 void mt76x0_agc_restore(struct mt76x0_dev *dev); 291 int mt76x0_phy_set_channel(struct mt76x0_dev *dev, 292 struct cfg80211_chan_def *chandef); 293 void mt76x0_phy_recalibrate_after_assoc(struct mt76x0_dev *dev); 294 int mt76x0_phy_get_rssi(struct mt76x0_dev *dev, struct mt76x0_rxwi *rxwi); 295 void mt76x0_phy_con_cal_onoff(struct mt76x0_dev *dev, 296 struct ieee80211_bss_conf *info); 297 298 /* MAC */ 299 void mt76x0_mac_work(struct work_struct *work); 300 void mt76x0_mac_set_protection(struct mt76x0_dev *dev, bool legacy_prot, 301 int ht_mode); 302 void mt76x0_mac_set_short_preamble(struct mt76x0_dev *dev, bool short_preamb); 303 void mt76x0_mac_config_tsf(struct mt76x0_dev *dev, bool enable, int interval); 304 void mt76x0_mac_set_ampdu_factor(struct mt76x0_dev *dev); 305 306 /* TX */ 307 void mt76x0_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, 308 struct sk_buff *skb); 309 int mt76x0_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 310 u16 queue, const struct ieee80211_tx_queue_params *params); 311 void mt76x0_tx_status(struct mt76x0_dev *dev, struct sk_buff *skb); 312 void mt76x0_tx_stat(struct work_struct *work); 313 314 /* util */ 315 void mt76x0_remove_hdr_pad(struct sk_buff *skb); 316 int mt76x0_insert_hdr_pad(struct sk_buff *skb); 317 318 int mt76x0_dma_init(struct mt76x0_dev *dev); 319 void mt76x0_dma_cleanup(struct mt76x0_dev *dev); 320 321 int mt76x0_dma_enqueue_tx(struct mt76x0_dev *dev, struct sk_buff *skb, 322 struct mt76_wcid *wcid, int hw_q); 323 324 #endif 325