1 /* 2 * (c) Copyright 2002-2010, Ralink Technology, Inc. 3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 9 * as published by the Free Software Foundation 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include "mt76x0.h" 18 #include "eeprom.h" 19 #include "trace.h" 20 #include "mcu.h" 21 #include "initvals.h" 22 23 static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband) 24 { 25 struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap; 26 u16 mcs_map = 0; 27 int i; 28 29 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC; 30 for (i = 0; i < 8; i++) { 31 if (!i) 32 mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2)); 33 else 34 mcs_map |= 35 (IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2)); 36 } 37 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 38 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 39 } 40 41 static void 42 mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable) 43 { 44 u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD; 45 46 /* Note: we don't turn off WLAN_CLK because that makes the device 47 * not respond properly on the probe path. 48 * In case anyone (PSM?) wants to use this function we can 49 * bring the clock stuff back and fixup the probe path. 50 */ 51 52 if (enable) 53 val |= (MT_WLAN_FUN_CTRL_WLAN_EN | 54 MT_WLAN_FUN_CTRL_WLAN_CLK_EN); 55 else 56 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); 57 58 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 59 udelay(20); 60 61 /* Note: vendor driver tries to disable/enable wlan here and retry 62 * but the code which does it is so buggy it must have never 63 * triggered, so don't bother. 64 */ 65 if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000)) 66 dev_err(dev->mt76.dev, "PLL and XTAL check failed\n"); 67 } 68 69 void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset) 70 { 71 u32 val; 72 73 val = mt76_rr(dev, MT_WLAN_FUN_CTRL); 74 75 if (reset) { 76 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; 77 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; 78 79 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { 80 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | 81 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 82 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 83 udelay(20); 84 85 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | 86 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 87 } 88 } 89 90 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 91 udelay(20); 92 93 mt76x0_set_wlan_state(dev, val, enable); 94 } 95 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff); 96 97 static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev) 98 { 99 mt76_wr(dev, MT_MAC_SYS_CTRL, 100 MT_MAC_SYS_CTRL_RESET_CSR | 101 MT_MAC_SYS_CTRL_RESET_BBP); 102 msleep(200); 103 mt76_clear(dev, MT_MAC_SYS_CTRL, 104 MT_MAC_SYS_CTRL_RESET_CSR | 105 MT_MAC_SYS_CTRL_RESET_BBP); 106 } 107 108 #define RANDOM_WRITE(dev, tab) \ 109 mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \ 110 tab, ARRAY_SIZE(tab)) 111 112 static int mt76x0_init_bbp(struct mt76x02_dev *dev) 113 { 114 int ret, i; 115 116 ret = mt76x0_wait_bbp_ready(dev); 117 if (ret) 118 return ret; 119 120 RANDOM_WRITE(dev, mt76x0_bbp_init_tab); 121 122 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 123 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 124 const struct mt76_reg_pair *pair = &item->reg_pair; 125 126 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 127 mt76_wr(dev, pair->reg, pair->value); 128 } 129 130 RANDOM_WRITE(dev, mt76x0_dcoc_tab); 131 132 return 0; 133 } 134 135 static void mt76x0_init_mac_registers(struct mt76x02_dev *dev) 136 { 137 u32 reg; 138 139 RANDOM_WRITE(dev, common_mac_reg_table); 140 141 mt76x02_set_beacon_offsets(dev); 142 143 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ 144 RANDOM_WRITE(dev, mt76x0_mac_reg_table); 145 146 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */ 147 reg = mt76_rr(dev, MT_MAC_SYS_CTRL); 148 reg &= ~0x3; 149 mt76_wr(dev, MT_MAC_SYS_CTRL, reg); 150 151 /* Set 0x141C[15:12]=0xF */ 152 reg = mt76_rr(dev, MT_EXT_CCA_CFG); 153 reg |= 0x0000F000; 154 mt76_wr(dev, MT_EXT_CCA_CFG, reg); 155 156 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 157 158 /* 159 TxRing 9 is for Mgmt frame. 160 TxRing 8 is for In-band command frame. 161 WMM_RG0_TXQMA: This register setting is for FCE to define the rule of TxRing 9. 162 WMM_RG1_TXQMA: This register setting is for FCE to define the rule of TxRing 8. 163 */ 164 reg = mt76_rr(dev, MT_WMM_CTRL); 165 reg &= ~0x000003FF; 166 reg |= 0x00000201; 167 mt76_wr(dev, MT_WMM_CTRL, reg); 168 } 169 170 static int mt76x0_init_wcid_mem(struct mt76x02_dev *dev) 171 { 172 u32 *vals; 173 int i; 174 175 vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL); 176 if (!vals) 177 return -ENOMEM; 178 179 for (i = 0; i < MT76_N_WCIDS; i++) { 180 vals[i * 2] = 0xffffffff; 181 vals[i * 2 + 1] = 0x00ffffff; 182 } 183 184 mt76_wr_copy(dev, MT_WCID_ADDR_BASE, vals, MT76_N_WCIDS * 2); 185 kfree(vals); 186 return 0; 187 } 188 189 static void mt76x0_init_key_mem(struct mt76x02_dev *dev) 190 { 191 u32 vals[4] = {}; 192 193 mt76_wr_copy(dev, MT_SKEY_MODE_BASE_0, vals, ARRAY_SIZE(vals)); 194 } 195 196 static int mt76x0_init_wcid_attr_mem(struct mt76x02_dev *dev) 197 { 198 u32 *vals; 199 int i; 200 201 vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL); 202 if (!vals) 203 return -ENOMEM; 204 205 for (i = 0; i < MT76_N_WCIDS * 2; i++) 206 vals[i] = 1; 207 208 mt76_wr_copy(dev, MT_WCID_ATTR_BASE, vals, MT76_N_WCIDS * 2); 209 kfree(vals); 210 return 0; 211 } 212 213 static void mt76x0_reset_counters(struct mt76x02_dev *dev) 214 { 215 mt76_rr(dev, MT_RX_STAT_0); 216 mt76_rr(dev, MT_RX_STAT_1); 217 mt76_rr(dev, MT_RX_STAT_2); 218 mt76_rr(dev, MT_TX_STA_0); 219 mt76_rr(dev, MT_TX_STA_1); 220 mt76_rr(dev, MT_TX_STA_2); 221 } 222 223 int mt76x0_mac_start(struct mt76x02_dev *dev) 224 { 225 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 226 227 if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000)) 228 return -ETIMEDOUT; 229 230 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); 231 mt76_wr(dev, MT_MAC_SYS_CTRL, 232 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 233 234 return !mt76x02_wait_for_wpdma(&dev->mt76, 50) ? -ETIMEDOUT : 0; 235 } 236 EXPORT_SYMBOL_GPL(mt76x0_mac_start); 237 238 void mt76x0_mac_stop(struct mt76x02_dev *dev) 239 { 240 int i = 200, ok = 0; 241 242 /* Page count on TxQ */ 243 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || 244 (mt76_rr(dev, 0x0a30) & 0x000000ff) || 245 (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) 246 msleep(10); 247 248 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) 249 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n"); 250 251 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | 252 MT_MAC_SYS_CTRL_ENABLE_TX); 253 254 /* Page count on RxQ */ 255 for (i = 0; i < 200; i++) { 256 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) && 257 !mt76_rr(dev, 0x0a30) && 258 !mt76_rr(dev, 0x0a34)) { 259 if (ok++ > 5) 260 break; 261 continue; 262 } 263 msleep(1); 264 } 265 266 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) 267 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n"); 268 } 269 EXPORT_SYMBOL_GPL(mt76x0_mac_stop); 270 271 int mt76x0_init_hardware(struct mt76x02_dev *dev) 272 { 273 int ret; 274 275 if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000)) 276 return -EIO; 277 278 /* Wait for ASIC ready after FW load. */ 279 if (!mt76x02_wait_for_mac(&dev->mt76)) 280 return -ETIMEDOUT; 281 282 mt76x0_reset_csr_bbp(dev); 283 ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1, false); 284 if (ret) 285 return ret; 286 287 mt76x0_init_mac_registers(dev); 288 289 if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) 290 return -EIO; 291 292 ret = mt76x0_init_bbp(dev); 293 if (ret) 294 return ret; 295 296 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 297 298 ret = mt76x0_init_wcid_mem(dev); 299 if (ret) 300 return ret; 301 302 mt76x0_init_key_mem(dev); 303 304 ret = mt76x0_init_wcid_attr_mem(dev); 305 if (ret) 306 return ret; 307 308 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | 309 MT_BEACON_TIME_CFG_SYNC_MODE | 310 MT_BEACON_TIME_CFG_TBTT_EN | 311 MT_BEACON_TIME_CFG_BEACON_TX)); 312 313 mt76x0_reset_counters(dev); 314 315 ret = mt76x0_eeprom_init(dev); 316 if (ret) 317 return ret; 318 319 mt76x0_phy_init(dev); 320 321 return 0; 322 } 323 EXPORT_SYMBOL_GPL(mt76x0_init_hardware); 324 325 struct mt76x02_dev * 326 mt76x0_alloc_device(struct device *pdev, 327 const struct mt76_driver_ops *drv_ops, 328 const struct ieee80211_ops *ops) 329 { 330 struct mt76x02_dev *dev; 331 struct mt76_dev *mdev; 332 333 mdev = mt76_alloc_device(sizeof(*dev), ops); 334 if (!mdev) 335 return NULL; 336 337 mdev->dev = pdev; 338 mdev->drv = drv_ops; 339 340 dev = container_of(mdev, struct mt76x02_dev, mt76); 341 mutex_init(&dev->phy_mutex); 342 atomic_set(&dev->avg_ampdu_len, 1); 343 344 return dev; 345 } 346 EXPORT_SYMBOL_GPL(mt76x0_alloc_device); 347 348 int mt76x0_register_device(struct mt76x02_dev *dev) 349 { 350 struct mt76_dev *mdev = &dev->mt76; 351 struct ieee80211_hw *hw = mdev->hw; 352 struct wiphy *wiphy = hw->wiphy; 353 int ret; 354 355 /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to 356 * entry no. 1 like it does in the vendor driver. 357 */ 358 mdev->wcid_mask[0] |= 1; 359 360 /* init fake wcid for monitor interfaces */ 361 mdev->global_wcid.idx = 0xff; 362 mdev->global_wcid.hw_key_idx = -1; 363 364 /* init antenna configuration */ 365 mdev->antenna_mask = 1; 366 367 hw->queues = 4; 368 hw->max_rates = 1; 369 hw->max_report_rates = 7; 370 hw->max_rate_tries = 1; 371 hw->extra_tx_headroom = 2; 372 if (mt76_is_usb(dev)) 373 hw->extra_tx_headroom += sizeof(struct mt76x02_txwi) + 374 MT_DMA_HDR_LEN; 375 376 hw->sta_data_size = sizeof(struct mt76x02_sta); 377 hw->vif_data_size = sizeof(struct mt76x02_vif); 378 379 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 380 381 INIT_DELAYED_WORK(&dev->mac_work, mt76x0_mac_work); 382 383 ret = mt76_register_device(mdev, true, mt76x02_rates, 384 ARRAY_SIZE(mt76x02_rates)); 385 if (ret) 386 return ret; 387 388 /* overwrite unsupported features */ 389 if (mdev->cap.has_5ghz) 390 mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband); 391 392 mt76x0_init_debugfs(dev); 393 394 return 0; 395 } 396 EXPORT_SYMBOL_GPL(mt76x0_register_device); 397