1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) Copyright 2002-2010, Ralink Technology, Inc. 4 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 5 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 6 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 7 */ 8 9 #include "mt76x0.h" 10 #include "eeprom.h" 11 #include "mcu.h" 12 #include "initvals.h" 13 #include "../mt76x02_phy.h" 14 15 static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband) 16 { 17 struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap; 18 u16 mcs_map = 0; 19 int i; 20 21 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC; 22 for (i = 0; i < 8; i++) { 23 if (!i) 24 mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2)); 25 else 26 mcs_map |= 27 (IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2)); 28 } 29 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 30 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 31 } 32 33 static void 34 mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable) 35 { 36 u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD; 37 38 /* Note: we don't turn off WLAN_CLK because that makes the device 39 * not respond properly on the probe path. 40 * In case anyone (PSM?) wants to use this function we can 41 * bring the clock stuff back and fixup the probe path. 42 */ 43 44 if (enable) 45 val |= (MT_WLAN_FUN_CTRL_WLAN_EN | 46 MT_WLAN_FUN_CTRL_WLAN_CLK_EN); 47 else 48 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); 49 50 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 51 udelay(20); 52 53 /* Note: vendor driver tries to disable/enable wlan here and retry 54 * but the code which does it is so buggy it must have never 55 * triggered, so don't bother. 56 */ 57 if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000)) 58 dev_err(dev->mt76.dev, "PLL and XTAL check failed\n"); 59 } 60 61 void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset) 62 { 63 u32 val; 64 65 val = mt76_rr(dev, MT_WLAN_FUN_CTRL); 66 67 if (reset) { 68 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; 69 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; 70 71 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { 72 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | 73 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 74 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 75 udelay(20); 76 77 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | 78 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 79 } 80 } 81 82 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 83 udelay(20); 84 85 mt76x0_set_wlan_state(dev, val, enable); 86 } 87 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff); 88 89 static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev) 90 { 91 mt76_wr(dev, MT_MAC_SYS_CTRL, 92 MT_MAC_SYS_CTRL_RESET_CSR | 93 MT_MAC_SYS_CTRL_RESET_BBP); 94 msleep(200); 95 mt76_clear(dev, MT_MAC_SYS_CTRL, 96 MT_MAC_SYS_CTRL_RESET_CSR | 97 MT_MAC_SYS_CTRL_RESET_BBP); 98 } 99 100 #define RANDOM_WRITE(dev, tab) \ 101 mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \ 102 tab, ARRAY_SIZE(tab)) 103 104 static int mt76x0_init_bbp(struct mt76x02_dev *dev) 105 { 106 int ret, i; 107 108 ret = mt76x0_phy_wait_bbp_ready(dev); 109 if (ret) 110 return ret; 111 112 RANDOM_WRITE(dev, mt76x0_bbp_init_tab); 113 114 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 115 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 116 const struct mt76_reg_pair *pair = &item->reg_pair; 117 118 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 119 mt76_wr(dev, pair->reg, pair->value); 120 } 121 122 RANDOM_WRITE(dev, mt76x0_dcoc_tab); 123 124 return 0; 125 } 126 127 static void mt76x0_init_mac_registers(struct mt76x02_dev *dev) 128 { 129 RANDOM_WRITE(dev, common_mac_reg_table); 130 131 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ 132 RANDOM_WRITE(dev, mt76x0_mac_reg_table); 133 134 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */ 135 mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3); 136 137 /* Set 0x141C[15:12]=0xF */ 138 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); 139 140 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 141 142 /* 143 * tx_ring 9 is for mgmt frame 144 * tx_ring 8 is for in-band command frame. 145 * WMM_RG0_TXQMA: this register setting is for FCE to 146 * define the rule of tx_ring 9 147 * WMM_RG1_TXQMA: this register setting is for FCE to 148 * define the rule of tx_ring 8 149 */ 150 mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201); 151 } 152 153 static void mt76x0_reset_counters(struct mt76x02_dev *dev) 154 { 155 mt76_rr(dev, MT_RX_STAT_0); 156 mt76_rr(dev, MT_RX_STAT_1); 157 mt76_rr(dev, MT_RX_STAT_2); 158 mt76_rr(dev, MT_TX_STA_0); 159 mt76_rr(dev, MT_TX_STA_1); 160 mt76_rr(dev, MT_TX_STA_2); 161 } 162 163 int mt76x0_mac_start(struct mt76x02_dev *dev) 164 { 165 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 166 167 if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000)) 168 return -ETIMEDOUT; 169 170 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); 171 mt76_wr(dev, MT_MAC_SYS_CTRL, 172 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 173 174 return !mt76x02_wait_for_wpdma(&dev->mt76, 50) ? -ETIMEDOUT : 0; 175 } 176 EXPORT_SYMBOL_GPL(mt76x0_mac_start); 177 178 void mt76x0_mac_stop(struct mt76x02_dev *dev) 179 { 180 int i = 200, ok = 0; 181 182 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 183 184 /* Page count on TxQ */ 185 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || 186 (mt76_rr(dev, 0x0a30) & 0x000000ff) || 187 (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) 188 msleep(10); 189 190 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) 191 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n"); 192 193 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | 194 MT_MAC_SYS_CTRL_ENABLE_TX); 195 196 /* Page count on RxQ */ 197 for (i = 0; i < 200; i++) { 198 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) && 199 !mt76_rr(dev, 0x0a30) && 200 !mt76_rr(dev, 0x0a34)) { 201 if (ok++ > 5) 202 break; 203 continue; 204 } 205 msleep(1); 206 } 207 208 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) 209 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n"); 210 } 211 EXPORT_SYMBOL_GPL(mt76x0_mac_stop); 212 213 int mt76x0_init_hardware(struct mt76x02_dev *dev) 214 { 215 int ret, i, k; 216 217 if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000)) 218 return -EIO; 219 220 /* Wait for ASIC ready after FW load. */ 221 if (!mt76x02_wait_for_mac(&dev->mt76)) 222 return -ETIMEDOUT; 223 224 mt76x0_reset_csr_bbp(dev); 225 ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1); 226 if (ret) 227 return ret; 228 229 mt76x0_init_mac_registers(dev); 230 231 if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) 232 return -EIO; 233 234 ret = mt76x0_init_bbp(dev); 235 if (ret) 236 return ret; 237 238 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 239 240 for (i = 0; i < 16; i++) 241 for (k = 0; k < 4; k++) 242 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 243 244 for (i = 0; i < 256; i++) 245 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 246 247 mt76x0_reset_counters(dev); 248 249 ret = mt76x0_eeprom_init(dev); 250 if (ret) 251 return ret; 252 253 mt76x0_phy_init(dev); 254 255 return 0; 256 } 257 EXPORT_SYMBOL_GPL(mt76x0_init_hardware); 258 259 static void 260 mt76x0_init_txpower(struct mt76x02_dev *dev, 261 struct ieee80211_supported_band *sband) 262 { 263 struct ieee80211_channel *chan; 264 struct mt76_rate_power t; 265 s8 tp; 266 int i; 267 268 for (i = 0; i < sband->n_channels; i++) { 269 chan = &sband->channels[i]; 270 271 mt76x0_get_tx_power_per_rate(dev, chan, &t); 272 mt76x0_get_power_info(dev, chan, &tp); 273 274 chan->orig_mpwr = (mt76x02_get_max_rate_power(&t) + tp) / 2; 275 chan->max_power = min_t(int, chan->max_reg_power, 276 chan->orig_mpwr); 277 } 278 } 279 280 int mt76x0_register_device(struct mt76x02_dev *dev) 281 { 282 int ret; 283 284 mt76x02_init_device(dev); 285 mt76x02_config_mac_addr_list(dev); 286 287 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 288 ARRAY_SIZE(mt76x02_rates)); 289 if (ret) 290 return ret; 291 292 if (dev->mt76.cap.has_5ghz) { 293 /* overwrite unsupported features */ 294 mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband); 295 mt76x0_init_txpower(dev, &dev->mt76.sband_5g.sband); 296 } 297 298 if (dev->mt76.cap.has_2ghz) 299 mt76x0_init_txpower(dev, &dev->mt76.sband_2g.sband); 300 301 mt76x02_init_debugfs(dev); 302 303 return 0; 304 } 305 EXPORT_SYMBOL_GPL(mt76x0_register_device); 306