1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * (c) Copyright 2002-2010, Ralink Technology, Inc.
4  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
5  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
6  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
7  */
8 
9 #include "mt76x0.h"
10 #include "eeprom.h"
11 #include "mcu.h"
12 #include "initvals.h"
13 #include "../mt76x02_phy.h"
14 
15 static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband)
16 {
17 	struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap;
18 	u16 mcs_map = 0;
19 	int i;
20 
21 	vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC;
22 	for (i = 0; i < 8; i++) {
23 		if (!i)
24 			mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2));
25 		else
26 			mcs_map |=
27 				(IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2));
28 	}
29 	vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
30 	vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
31 }
32 
33 static void
34 mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable)
35 {
36 	u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD;
37 
38 	/* Note: we don't turn off WLAN_CLK because that makes the device
39 	 *	 not respond properly on the probe path.
40 	 *	 In case anyone (PSM?) wants to use this function we can
41 	 *	 bring the clock stuff back and fixup the probe path.
42 	 */
43 
44 	if (enable)
45 		val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
46 			MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
47 	else
48 		val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
49 
50 	mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
51 	udelay(20);
52 
53 	/* Note: vendor driver tries to disable/enable wlan here and retry
54 	 *       but the code which does it is so buggy it must have never
55 	 *       triggered, so don't bother.
56 	 */
57 	if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000))
58 		dev_err(dev->mt76.dev, "PLL and XTAL check failed\n");
59 }
60 
61 void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset)
62 {
63 	u32 val;
64 
65 	val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
66 
67 	if (reset) {
68 		val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
69 		val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
70 
71 		if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
72 			val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
73 				MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
74 			mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
75 			udelay(20);
76 
77 			val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
78 				 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
79 		}
80 	}
81 
82 	mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
83 	udelay(20);
84 
85 	mt76x0_set_wlan_state(dev, val, enable);
86 }
87 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff);
88 
89 static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev)
90 {
91 	mt76_wr(dev, MT_MAC_SYS_CTRL,
92 		MT_MAC_SYS_CTRL_RESET_CSR |
93 		MT_MAC_SYS_CTRL_RESET_BBP);
94 	msleep(200);
95 	mt76_clear(dev, MT_MAC_SYS_CTRL,
96 		   MT_MAC_SYS_CTRL_RESET_CSR |
97 		   MT_MAC_SYS_CTRL_RESET_BBP);
98 }
99 
100 #define RANDOM_WRITE(dev, tab)			\
101 	mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN,	\
102 		   tab, ARRAY_SIZE(tab))
103 
104 static int mt76x0_init_bbp(struct mt76x02_dev *dev)
105 {
106 	int ret, i;
107 
108 	ret = mt76x0_phy_wait_bbp_ready(dev);
109 	if (ret)
110 		return ret;
111 
112 	RANDOM_WRITE(dev, mt76x0_bbp_init_tab);
113 
114 	for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) {
115 		const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i];
116 		const struct mt76_reg_pair *pair = &item->reg_pair;
117 
118 		if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20))
119 			mt76_wr(dev, pair->reg, pair->value);
120 	}
121 
122 	RANDOM_WRITE(dev, mt76x0_dcoc_tab);
123 
124 	return 0;
125 }
126 
127 static void mt76x0_init_mac_registers(struct mt76x02_dev *dev)
128 {
129 	RANDOM_WRITE(dev, common_mac_reg_table);
130 
131 	/* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
132 	RANDOM_WRITE(dev, mt76x0_mac_reg_table);
133 
134 	/* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */
135 	mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3);
136 
137 	/* Set 0x141C[15:12]=0xF */
138 	mt76_set(dev, MT_EXT_CCA_CFG, 0xf000);
139 
140 	mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
141 
142 	/*
143 	 * tx_ring 9 is for mgmt frame
144 	 * tx_ring 8 is for in-band command frame.
145 	 * WMM_RG0_TXQMA: this register setting is for FCE to
146 	 *		  define the rule of tx_ring 9
147 	 * WMM_RG1_TXQMA: this register setting is for FCE to
148 	 *		  define the rule of tx_ring 8
149 	 */
150 	mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201);
151 }
152 
153 void mt76x0_mac_stop(struct mt76x02_dev *dev)
154 {
155 	int i = 200, ok = 0;
156 
157 	mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
158 
159 	/* Page count on TxQ */
160 	while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
161 		       (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
162 		       (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
163 		msleep(10);
164 
165 	if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
166 		dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n");
167 
168 	mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
169 					 MT_MAC_SYS_CTRL_ENABLE_TX);
170 
171 	/* Page count on RxQ */
172 	for (i = 0; i < 200; i++) {
173 		if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
174 		    !mt76_rr(dev, 0x0a30) &&
175 		    !mt76_rr(dev, 0x0a34)) {
176 			if (ok++ > 5)
177 				break;
178 			continue;
179 		}
180 		msleep(1);
181 	}
182 
183 	if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
184 		dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n");
185 }
186 EXPORT_SYMBOL_GPL(mt76x0_mac_stop);
187 
188 int mt76x0_init_hardware(struct mt76x02_dev *dev)
189 {
190 	int ret, i, k;
191 
192 	if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000))
193 		return -EIO;
194 
195 	/* Wait for ASIC ready after FW load. */
196 	if (!mt76x02_wait_for_mac(&dev->mt76))
197 		return -ETIMEDOUT;
198 
199 	mt76x0_reset_csr_bbp(dev);
200 	ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1);
201 	if (ret)
202 		return ret;
203 
204 	mt76x0_init_mac_registers(dev);
205 
206 	if (!mt76x02_wait_for_txrx_idle(&dev->mt76))
207 		return -EIO;
208 
209 	ret = mt76x0_init_bbp(dev);
210 	if (ret)
211 		return ret;
212 
213 	dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
214 
215 	for (i = 0; i < 16; i++)
216 		for (k = 0; k < 4; k++)
217 			mt76x02_mac_shared_key_setup(dev, i, k, NULL);
218 
219 	for (i = 0; i < 256; i++)
220 		mt76x02_mac_wcid_setup(dev, i, 0, NULL);
221 
222 	ret = mt76x0_eeprom_init(dev);
223 	if (ret)
224 		return ret;
225 
226 	mt76x0_phy_init(dev);
227 
228 	return 0;
229 }
230 EXPORT_SYMBOL_GPL(mt76x0_init_hardware);
231 
232 static void
233 mt76x0_init_txpower(struct mt76x02_dev *dev,
234 		    struct ieee80211_supported_band *sband)
235 {
236 	struct ieee80211_channel *chan;
237 	struct mt76_rate_power t;
238 	s8 tp;
239 	int i;
240 
241 	for (i = 0; i < sband->n_channels; i++) {
242 		chan = &sband->channels[i];
243 
244 		mt76x0_get_tx_power_per_rate(dev, chan, &t);
245 		mt76x0_get_power_info(dev, chan, &tp);
246 
247 		chan->orig_mpwr = (mt76x02_get_max_rate_power(&t) + tp) / 2;
248 		chan->max_power = min_t(int, chan->max_reg_power,
249 					chan->orig_mpwr);
250 	}
251 }
252 
253 int mt76x0_register_device(struct mt76x02_dev *dev)
254 {
255 	int ret;
256 
257 	mt76x02_init_device(dev);
258 	mt76x02_config_mac_addr_list(dev);
259 
260 	ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
261 				   ARRAY_SIZE(mt76x02_rates));
262 	if (ret)
263 		return ret;
264 
265 	if (dev->mt76.cap.has_5ghz) {
266 		/* overwrite unsupported features */
267 		mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband);
268 		mt76x0_init_txpower(dev, &dev->mt76.sband_5g.sband);
269 	}
270 
271 	if (dev->mt76.cap.has_2ghz)
272 		mt76x0_init_txpower(dev, &dev->mt76.sband_2g.sband);
273 
274 	mt76x02_init_debugfs(dev);
275 
276 	return 0;
277 }
278 EXPORT_SYMBOL_GPL(mt76x0_register_device);
279