1 /* 2 * (c) Copyright 2002-2010, Ralink Technology, Inc. 3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 9 * as published by the Free Software Foundation 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include "mt76x0.h" 18 #include "eeprom.h" 19 #include "mcu.h" 20 #include "initvals.h" 21 #include "../mt76x02_phy.h" 22 23 static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband) 24 { 25 struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap; 26 u16 mcs_map = 0; 27 int i; 28 29 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC; 30 for (i = 0; i < 8; i++) { 31 if (!i) 32 mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2)); 33 else 34 mcs_map |= 35 (IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2)); 36 } 37 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 38 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 39 } 40 41 static void 42 mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable) 43 { 44 u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD; 45 46 /* Note: we don't turn off WLAN_CLK because that makes the device 47 * not respond properly on the probe path. 48 * In case anyone (PSM?) wants to use this function we can 49 * bring the clock stuff back and fixup the probe path. 50 */ 51 52 if (enable) 53 val |= (MT_WLAN_FUN_CTRL_WLAN_EN | 54 MT_WLAN_FUN_CTRL_WLAN_CLK_EN); 55 else 56 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); 57 58 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 59 udelay(20); 60 61 /* Note: vendor driver tries to disable/enable wlan here and retry 62 * but the code which does it is so buggy it must have never 63 * triggered, so don't bother. 64 */ 65 if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000)) 66 dev_err(dev->mt76.dev, "PLL and XTAL check failed\n"); 67 } 68 69 void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset) 70 { 71 u32 val; 72 73 val = mt76_rr(dev, MT_WLAN_FUN_CTRL); 74 75 if (reset) { 76 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; 77 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; 78 79 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { 80 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | 81 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 82 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 83 udelay(20); 84 85 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | 86 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 87 } 88 } 89 90 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 91 udelay(20); 92 93 mt76x0_set_wlan_state(dev, val, enable); 94 } 95 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff); 96 97 static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev) 98 { 99 mt76_wr(dev, MT_MAC_SYS_CTRL, 100 MT_MAC_SYS_CTRL_RESET_CSR | 101 MT_MAC_SYS_CTRL_RESET_BBP); 102 msleep(200); 103 mt76_clear(dev, MT_MAC_SYS_CTRL, 104 MT_MAC_SYS_CTRL_RESET_CSR | 105 MT_MAC_SYS_CTRL_RESET_BBP); 106 } 107 108 #define RANDOM_WRITE(dev, tab) \ 109 mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \ 110 tab, ARRAY_SIZE(tab)) 111 112 static int mt76x0_init_bbp(struct mt76x02_dev *dev) 113 { 114 int ret, i; 115 116 ret = mt76x0_phy_wait_bbp_ready(dev); 117 if (ret) 118 return ret; 119 120 RANDOM_WRITE(dev, mt76x0_bbp_init_tab); 121 122 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 123 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 124 const struct mt76_reg_pair *pair = &item->reg_pair; 125 126 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 127 mt76_wr(dev, pair->reg, pair->value); 128 } 129 130 RANDOM_WRITE(dev, mt76x0_dcoc_tab); 131 132 return 0; 133 } 134 135 static void mt76x0_init_mac_registers(struct mt76x02_dev *dev) 136 { 137 RANDOM_WRITE(dev, common_mac_reg_table); 138 139 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ 140 RANDOM_WRITE(dev, mt76x0_mac_reg_table); 141 142 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */ 143 mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3); 144 145 /* Set 0x141C[15:12]=0xF */ 146 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); 147 148 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 149 150 /* 151 * tx_ring 9 is for mgmt frame 152 * tx_ring 8 is for in-band command frame. 153 * WMM_RG0_TXQMA: this register setting is for FCE to 154 * define the rule of tx_ring 9 155 * WMM_RG1_TXQMA: this register setting is for FCE to 156 * define the rule of tx_ring 8 157 */ 158 mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201); 159 } 160 161 static void mt76x0_reset_counters(struct mt76x02_dev *dev) 162 { 163 mt76_rr(dev, MT_RX_STAT_0); 164 mt76_rr(dev, MT_RX_STAT_1); 165 mt76_rr(dev, MT_RX_STAT_2); 166 mt76_rr(dev, MT_TX_STA_0); 167 mt76_rr(dev, MT_TX_STA_1); 168 mt76_rr(dev, MT_TX_STA_2); 169 } 170 171 int mt76x0_mac_start(struct mt76x02_dev *dev) 172 { 173 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 174 175 if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000)) 176 return -ETIMEDOUT; 177 178 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); 179 mt76_wr(dev, MT_MAC_SYS_CTRL, 180 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 181 182 return !mt76x02_wait_for_wpdma(&dev->mt76, 50) ? -ETIMEDOUT : 0; 183 } 184 EXPORT_SYMBOL_GPL(mt76x0_mac_start); 185 186 void mt76x0_mac_stop(struct mt76x02_dev *dev) 187 { 188 int i = 200, ok = 0; 189 190 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 191 192 /* Page count on TxQ */ 193 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || 194 (mt76_rr(dev, 0x0a30) & 0x000000ff) || 195 (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) 196 msleep(10); 197 198 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) 199 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n"); 200 201 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | 202 MT_MAC_SYS_CTRL_ENABLE_TX); 203 204 /* Page count on RxQ */ 205 for (i = 0; i < 200; i++) { 206 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) && 207 !mt76_rr(dev, 0x0a30) && 208 !mt76_rr(dev, 0x0a34)) { 209 if (ok++ > 5) 210 break; 211 continue; 212 } 213 msleep(1); 214 } 215 216 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) 217 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n"); 218 } 219 EXPORT_SYMBOL_GPL(mt76x0_mac_stop); 220 221 int mt76x0_init_hardware(struct mt76x02_dev *dev) 222 { 223 int ret, i, k; 224 225 if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000)) 226 return -EIO; 227 228 /* Wait for ASIC ready after FW load. */ 229 if (!mt76x02_wait_for_mac(&dev->mt76)) 230 return -ETIMEDOUT; 231 232 mt76x0_reset_csr_bbp(dev); 233 ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1); 234 if (ret) 235 return ret; 236 237 mt76x0_init_mac_registers(dev); 238 239 if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) 240 return -EIO; 241 242 ret = mt76x0_init_bbp(dev); 243 if (ret) 244 return ret; 245 246 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 247 248 for (i = 0; i < 16; i++) 249 for (k = 0; k < 4; k++) 250 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 251 252 for (i = 0; i < 256; i++) 253 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 254 255 mt76x0_reset_counters(dev); 256 257 ret = mt76x0_eeprom_init(dev); 258 if (ret) 259 return ret; 260 261 mt76x0_phy_init(dev); 262 mt76x02_init_beacon_config(dev); 263 264 return 0; 265 } 266 EXPORT_SYMBOL_GPL(mt76x0_init_hardware); 267 268 static void 269 mt76x0_init_txpower(struct mt76x02_dev *dev, 270 struct ieee80211_supported_band *sband) 271 { 272 struct ieee80211_channel *chan; 273 struct mt76_rate_power t; 274 s8 tp; 275 int i; 276 277 for (i = 0; i < sband->n_channels; i++) { 278 chan = &sband->channels[i]; 279 280 mt76x0_get_tx_power_per_rate(dev, chan, &t); 281 mt76x0_get_power_info(dev, chan, &tp); 282 283 chan->max_power = (mt76x02_get_max_rate_power(&t) + tp) / 2; 284 } 285 } 286 287 int mt76x0_register_device(struct mt76x02_dev *dev) 288 { 289 int ret; 290 291 mt76x02_init_device(dev); 292 mt76x02_config_mac_addr_list(dev); 293 294 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 295 ARRAY_SIZE(mt76x02_rates)); 296 if (ret) 297 return ret; 298 299 if (dev->mt76.cap.has_5ghz) { 300 /* overwrite unsupported features */ 301 mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband); 302 mt76x0_init_txpower(dev, &dev->mt76.sband_5g.sband); 303 } 304 305 if (dev->mt76.cap.has_2ghz) 306 mt76x0_init_txpower(dev, &dev->mt76.sband_2g.sband); 307 308 mt76x02_init_debugfs(dev); 309 310 return 0; 311 } 312 EXPORT_SYMBOL_GPL(mt76x0_register_device); 313