1134b2d0dSStanislaw Gruszka /* 2134b2d0dSStanislaw Gruszka * (c) Copyright 2002-2010, Ralink Technology, Inc. 3134b2d0dSStanislaw Gruszka * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 4134b2d0dSStanislaw Gruszka * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5134b2d0dSStanislaw Gruszka * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 6134b2d0dSStanislaw Gruszka * 7134b2d0dSStanislaw Gruszka * This program is free software; you can redistribute it and/or modify 8134b2d0dSStanislaw Gruszka * it under the terms of the GNU General Public License version 2 9134b2d0dSStanislaw Gruszka * as published by the Free Software Foundation 10134b2d0dSStanislaw Gruszka * 11134b2d0dSStanislaw Gruszka * This program is distributed in the hope that it will be useful, 12134b2d0dSStanislaw Gruszka * but WITHOUT ANY WARRANTY; without even the implied warranty of 13134b2d0dSStanislaw Gruszka * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14134b2d0dSStanislaw Gruszka * GNU General Public License for more details. 15134b2d0dSStanislaw Gruszka */ 16134b2d0dSStanislaw Gruszka 17134b2d0dSStanislaw Gruszka #include "mt76x0.h" 18134b2d0dSStanislaw Gruszka #include "eeprom.h" 19134b2d0dSStanislaw Gruszka #include "trace.h" 20134b2d0dSStanislaw Gruszka #include "mcu.h" 21f2653a4eSLorenzo Bianconi #include "../mt76x02_util.h" 223b11db26SLorenzo Bianconi #include "../mt76x02_dma.h" 23134b2d0dSStanislaw Gruszka 24134b2d0dSStanislaw Gruszka #include "initvals.h" 25134b2d0dSStanislaw Gruszka 261bee323aSLorenzo Bianconi static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband) 271bee323aSLorenzo Bianconi { 281bee323aSLorenzo Bianconi struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap; 291bee323aSLorenzo Bianconi u16 mcs_map = 0; 301bee323aSLorenzo Bianconi int i; 311bee323aSLorenzo Bianconi 321bee323aSLorenzo Bianconi vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC; 331bee323aSLorenzo Bianconi for (i = 0; i < 8; i++) { 341bee323aSLorenzo Bianconi if (!i) 351bee323aSLorenzo Bianconi mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2)); 361bee323aSLorenzo Bianconi else 371bee323aSLorenzo Bianconi mcs_map |= 381bee323aSLorenzo Bianconi (IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2)); 391bee323aSLorenzo Bianconi } 401bee323aSLorenzo Bianconi vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 411bee323aSLorenzo Bianconi vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 421bee323aSLorenzo Bianconi } 431bee323aSLorenzo Bianconi 44134b2d0dSStanislaw Gruszka static void 45b2d871c0SLorenzo Bianconi mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable) 46134b2d0dSStanislaw Gruszka { 475b394355SLorenzo Bianconi u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD; 48134b2d0dSStanislaw Gruszka 49134b2d0dSStanislaw Gruszka /* Note: we don't turn off WLAN_CLK because that makes the device 50134b2d0dSStanislaw Gruszka * not respond properly on the probe path. 51134b2d0dSStanislaw Gruszka * In case anyone (PSM?) wants to use this function we can 52134b2d0dSStanislaw Gruszka * bring the clock stuff back and fixup the probe path. 53134b2d0dSStanislaw Gruszka */ 54134b2d0dSStanislaw Gruszka 55134b2d0dSStanislaw Gruszka if (enable) 56134b2d0dSStanislaw Gruszka val |= (MT_WLAN_FUN_CTRL_WLAN_EN | 57134b2d0dSStanislaw Gruszka MT_WLAN_FUN_CTRL_WLAN_CLK_EN); 58134b2d0dSStanislaw Gruszka else 59134b2d0dSStanislaw Gruszka val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); 60134b2d0dSStanislaw Gruszka 61134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 62134b2d0dSStanislaw Gruszka udelay(20); 63134b2d0dSStanislaw Gruszka 64134b2d0dSStanislaw Gruszka /* Note: vendor driver tries to disable/enable wlan here and retry 65134b2d0dSStanislaw Gruszka * but the code which does it is so buggy it must have never 66134b2d0dSStanislaw Gruszka * triggered, so don't bother. 67134b2d0dSStanislaw Gruszka */ 685b394355SLorenzo Bianconi if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000)) 695b394355SLorenzo Bianconi dev_err(dev->mt76.dev, "PLL and XTAL check failed\n"); 70134b2d0dSStanislaw Gruszka } 71134b2d0dSStanislaw Gruszka 72b2d871c0SLorenzo Bianconi void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset) 73134b2d0dSStanislaw Gruszka { 74134b2d0dSStanislaw Gruszka u32 val; 75134b2d0dSStanislaw Gruszka 76134b2d0dSStanislaw Gruszka val = mt76_rr(dev, MT_WLAN_FUN_CTRL); 77134b2d0dSStanislaw Gruszka 78134b2d0dSStanislaw Gruszka if (reset) { 79134b2d0dSStanislaw Gruszka val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; 80134b2d0dSStanislaw Gruszka val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; 81134b2d0dSStanislaw Gruszka 82134b2d0dSStanislaw Gruszka if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { 83134b2d0dSStanislaw Gruszka val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | 84134b2d0dSStanislaw Gruszka MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 85134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 86134b2d0dSStanislaw Gruszka udelay(20); 87134b2d0dSStanislaw Gruszka 88134b2d0dSStanislaw Gruszka val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | 89134b2d0dSStanislaw Gruszka MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 90134b2d0dSStanislaw Gruszka } 91134b2d0dSStanislaw Gruszka } 92134b2d0dSStanislaw Gruszka 93134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 94134b2d0dSStanislaw Gruszka udelay(20); 95134b2d0dSStanislaw Gruszka 96134b2d0dSStanislaw Gruszka mt76x0_set_wlan_state(dev, val, enable); 97134b2d0dSStanislaw Gruszka } 98c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_chip_onoff); 99134b2d0dSStanislaw Gruszka 100b2d871c0SLorenzo Bianconi static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev) 101134b2d0dSStanislaw Gruszka { 102512bd4b1SLorenzo Bianconi mt76_wr(dev, MT_MAC_SYS_CTRL, 103512bd4b1SLorenzo Bianconi MT_MAC_SYS_CTRL_RESET_CSR | 104134b2d0dSStanislaw Gruszka MT_MAC_SYS_CTRL_RESET_BBP); 105134b2d0dSStanislaw Gruszka msleep(200); 1062b2cb40bSLorenzo Bianconi mt76_clear(dev, MT_MAC_SYS_CTRL, 1072b2cb40bSLorenzo Bianconi MT_MAC_SYS_CTRL_RESET_CSR | 1082b2cb40bSLorenzo Bianconi MT_MAC_SYS_CTRL_RESET_BBP); 109134b2d0dSStanislaw Gruszka } 110134b2d0dSStanislaw Gruszka 111134b2d0dSStanislaw Gruszka #define RANDOM_WRITE(dev, tab) \ 11217507157SLorenzo Bianconi mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \ 113f1638c7cSStanislaw Gruszka tab, ARRAY_SIZE(tab)) 114134b2d0dSStanislaw Gruszka 115b2d871c0SLorenzo Bianconi static int mt76x0_init_bbp(struct mt76x02_dev *dev) 116134b2d0dSStanislaw Gruszka { 117134b2d0dSStanislaw Gruszka int ret, i; 118134b2d0dSStanislaw Gruszka 119134b2d0dSStanislaw Gruszka ret = mt76x0_wait_bbp_ready(dev); 120134b2d0dSStanislaw Gruszka if (ret) 121134b2d0dSStanislaw Gruszka return ret; 122134b2d0dSStanislaw Gruszka 123134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, mt76x0_bbp_init_tab); 124134b2d0dSStanislaw Gruszka 125134b2d0dSStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 126134b2d0dSStanislaw Gruszka const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 127134b2d0dSStanislaw Gruszka const struct mt76_reg_pair *pair = &item->reg_pair; 128134b2d0dSStanislaw Gruszka 129134b2d0dSStanislaw Gruszka if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 130134b2d0dSStanislaw Gruszka mt76_wr(dev, pair->reg, pair->value); 131134b2d0dSStanislaw Gruszka } 132134b2d0dSStanislaw Gruszka 133134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, mt76x0_dcoc_tab); 134134b2d0dSStanislaw Gruszka 135134b2d0dSStanislaw Gruszka return 0; 136134b2d0dSStanislaw Gruszka } 137134b2d0dSStanislaw Gruszka 138b2d871c0SLorenzo Bianconi static void mt76x0_init_mac_registers(struct mt76x02_dev *dev) 139134b2d0dSStanislaw Gruszka { 140134b2d0dSStanislaw Gruszka u32 reg; 141134b2d0dSStanislaw Gruszka 142134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, common_mac_reg_table); 143134b2d0dSStanislaw Gruszka 144a6daf796SLorenzo Bianconi mt76x02_set_beacon_offsets(&dev->mt76); 145134b2d0dSStanislaw Gruszka 146134b2d0dSStanislaw Gruszka /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ 147134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, mt76x0_mac_reg_table); 148134b2d0dSStanislaw Gruszka 149134b2d0dSStanislaw Gruszka /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */ 150134b2d0dSStanislaw Gruszka reg = mt76_rr(dev, MT_MAC_SYS_CTRL); 151134b2d0dSStanislaw Gruszka reg &= ~0x3; 152134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_MAC_SYS_CTRL, reg); 153134b2d0dSStanislaw Gruszka 154134b2d0dSStanislaw Gruszka /* Set 0x141C[15:12]=0xF */ 155134b2d0dSStanislaw Gruszka reg = mt76_rr(dev, MT_EXT_CCA_CFG); 156134b2d0dSStanislaw Gruszka reg |= 0x0000F000; 157134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_EXT_CCA_CFG, reg); 158134b2d0dSStanislaw Gruszka 159134b2d0dSStanislaw Gruszka mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 160134b2d0dSStanislaw Gruszka 161134b2d0dSStanislaw Gruszka /* 162134b2d0dSStanislaw Gruszka TxRing 9 is for Mgmt frame. 163134b2d0dSStanislaw Gruszka TxRing 8 is for In-band command frame. 164134b2d0dSStanislaw Gruszka WMM_RG0_TXQMA: This register setting is for FCE to define the rule of TxRing 9. 165134b2d0dSStanislaw Gruszka WMM_RG1_TXQMA: This register setting is for FCE to define the rule of TxRing 8. 166134b2d0dSStanislaw Gruszka */ 167134b2d0dSStanislaw Gruszka reg = mt76_rr(dev, MT_WMM_CTRL); 168134b2d0dSStanislaw Gruszka reg &= ~0x000003FF; 169134b2d0dSStanislaw Gruszka reg |= 0x00000201; 170134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_WMM_CTRL, reg); 171134b2d0dSStanislaw Gruszka } 172134b2d0dSStanislaw Gruszka 173b2d871c0SLorenzo Bianconi static int mt76x0_init_wcid_mem(struct mt76x02_dev *dev) 174134b2d0dSStanislaw Gruszka { 175134b2d0dSStanislaw Gruszka u32 *vals; 176331419b2SStanislaw Gruszka int i; 177134b2d0dSStanislaw Gruszka 17836404c06SStanislaw Gruszka vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL); 179134b2d0dSStanislaw Gruszka if (!vals) 180134b2d0dSStanislaw Gruszka return -ENOMEM; 181134b2d0dSStanislaw Gruszka 18236404c06SStanislaw Gruszka for (i = 0; i < MT76_N_WCIDS; i++) { 183134b2d0dSStanislaw Gruszka vals[i * 2] = 0xffffffff; 184134b2d0dSStanislaw Gruszka vals[i * 2 + 1] = 0x00ffffff; 185134b2d0dSStanislaw Gruszka } 186134b2d0dSStanislaw Gruszka 187331419b2SStanislaw Gruszka mt76_wr_copy(dev, MT_WCID_ADDR_BASE, vals, MT76_N_WCIDS * 2); 188134b2d0dSStanislaw Gruszka kfree(vals); 189331419b2SStanislaw Gruszka return 0; 190134b2d0dSStanislaw Gruszka } 191134b2d0dSStanislaw Gruszka 192b2d871c0SLorenzo Bianconi static void mt76x0_init_key_mem(struct mt76x02_dev *dev) 193134b2d0dSStanislaw Gruszka { 194134b2d0dSStanislaw Gruszka u32 vals[4] = {}; 195134b2d0dSStanislaw Gruszka 196331419b2SStanislaw Gruszka mt76_wr_copy(dev, MT_SKEY_MODE_BASE_0, vals, ARRAY_SIZE(vals)); 197134b2d0dSStanislaw Gruszka } 198134b2d0dSStanislaw Gruszka 199b2d871c0SLorenzo Bianconi static int mt76x0_init_wcid_attr_mem(struct mt76x02_dev *dev) 200134b2d0dSStanislaw Gruszka { 201134b2d0dSStanislaw Gruszka u32 *vals; 202331419b2SStanislaw Gruszka int i; 203134b2d0dSStanislaw Gruszka 20436404c06SStanislaw Gruszka vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL); 205134b2d0dSStanislaw Gruszka if (!vals) 206134b2d0dSStanislaw Gruszka return -ENOMEM; 207134b2d0dSStanislaw Gruszka 20836404c06SStanislaw Gruszka for (i = 0; i < MT76_N_WCIDS * 2; i++) 209134b2d0dSStanislaw Gruszka vals[i] = 1; 210134b2d0dSStanislaw Gruszka 211331419b2SStanislaw Gruszka mt76_wr_copy(dev, MT_WCID_ATTR_BASE, vals, MT76_N_WCIDS * 2); 212134b2d0dSStanislaw Gruszka kfree(vals); 213331419b2SStanislaw Gruszka return 0; 214134b2d0dSStanislaw Gruszka } 215134b2d0dSStanislaw Gruszka 216b2d871c0SLorenzo Bianconi static void mt76x0_reset_counters(struct mt76x02_dev *dev) 217134b2d0dSStanislaw Gruszka { 218797ea240SStanislaw Gruszka mt76_rr(dev, MT_RX_STAT_0); 219797ea240SStanislaw Gruszka mt76_rr(dev, MT_RX_STAT_1); 220797ea240SStanislaw Gruszka mt76_rr(dev, MT_RX_STAT_2); 221797ea240SStanislaw Gruszka mt76_rr(dev, MT_TX_STA_0); 222797ea240SStanislaw Gruszka mt76_rr(dev, MT_TX_STA_1); 223797ea240SStanislaw Gruszka mt76_rr(dev, MT_TX_STA_2); 224134b2d0dSStanislaw Gruszka } 225134b2d0dSStanislaw Gruszka 226b2d871c0SLorenzo Bianconi int mt76x0_mac_start(struct mt76x02_dev *dev) 227134b2d0dSStanislaw Gruszka { 228134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); 229134b2d0dSStanislaw Gruszka 2303b11db26SLorenzo Bianconi if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000)) 231134b2d0dSStanislaw Gruszka return -ETIMEDOUT; 232134b2d0dSStanislaw Gruszka 233108a4861SStanislaw Gruszka mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter); 234134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_MAC_SYS_CTRL, 235134b2d0dSStanislaw Gruszka MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); 236134b2d0dSStanislaw Gruszka 2373b11db26SLorenzo Bianconi return !mt76x02_wait_for_wpdma(&dev->mt76, 50) ? -ETIMEDOUT : 0; 238134b2d0dSStanislaw Gruszka } 239b11e1969SLorenzo Bianconi EXPORT_SYMBOL_GPL(mt76x0_mac_start); 240134b2d0dSStanislaw Gruszka 241b2d871c0SLorenzo Bianconi void mt76x0_mac_stop(struct mt76x02_dev *dev) 242134b2d0dSStanislaw Gruszka { 243b11e1969SLorenzo Bianconi int i = 200, ok = 0; 244134b2d0dSStanislaw Gruszka 245134b2d0dSStanislaw Gruszka /* Page count on TxQ */ 246134b2d0dSStanislaw Gruszka while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || 247134b2d0dSStanislaw Gruszka (mt76_rr(dev, 0x0a30) & 0x000000ff) || 248134b2d0dSStanislaw Gruszka (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) 249134b2d0dSStanislaw Gruszka msleep(10); 250134b2d0dSStanislaw Gruszka 251134b2d0dSStanislaw Gruszka if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) 252134b2d0dSStanislaw Gruszka dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n"); 253134b2d0dSStanislaw Gruszka 254134b2d0dSStanislaw Gruszka mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | 255134b2d0dSStanislaw Gruszka MT_MAC_SYS_CTRL_ENABLE_TX); 256134b2d0dSStanislaw Gruszka 257134b2d0dSStanislaw Gruszka /* Page count on RxQ */ 258b11e1969SLorenzo Bianconi for (i = 0; i < 200; i++) { 259134b2d0dSStanislaw Gruszka if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) && 260134b2d0dSStanislaw Gruszka !mt76_rr(dev, 0x0a30) && 261134b2d0dSStanislaw Gruszka !mt76_rr(dev, 0x0a34)) { 262134b2d0dSStanislaw Gruszka if (ok++ > 5) 263134b2d0dSStanislaw Gruszka break; 264134b2d0dSStanislaw Gruszka continue; 265134b2d0dSStanislaw Gruszka } 266134b2d0dSStanislaw Gruszka msleep(1); 267134b2d0dSStanislaw Gruszka } 268134b2d0dSStanislaw Gruszka 269134b2d0dSStanislaw Gruszka if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) 270134b2d0dSStanislaw Gruszka dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n"); 271134b2d0dSStanislaw Gruszka } 272c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_mac_stop); 273134b2d0dSStanislaw Gruszka 274b2d871c0SLorenzo Bianconi int mt76x0_init_hardware(struct mt76x02_dev *dev) 275134b2d0dSStanislaw Gruszka { 276134b2d0dSStanislaw Gruszka int ret; 277134b2d0dSStanislaw Gruszka 2783b11db26SLorenzo Bianconi if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000)) 279e30a655eSLorenzo Bianconi return -EIO; 280134b2d0dSStanislaw Gruszka 281134b2d0dSStanislaw Gruszka /* Wait for ASIC ready after FW load. */ 282e30a655eSLorenzo Bianconi if (!mt76x02_wait_for_mac(&dev->mt76)) 283e30a655eSLorenzo Bianconi return -ETIMEDOUT; 284134b2d0dSStanislaw Gruszka 285134b2d0dSStanislaw Gruszka mt76x0_reset_csr_bbp(dev); 28628041571SLorenzo Bianconi ret = mt76x02_mcu_function_select(&dev->mt76, Q_SELECT, 1, false); 287134b2d0dSStanislaw Gruszka if (ret) 288e30a655eSLorenzo Bianconi return ret; 28930ec9152SLorenzo Bianconi 290134b2d0dSStanislaw Gruszka mt76x0_init_mac_registers(dev); 291134b2d0dSStanislaw Gruszka 2923b11db26SLorenzo Bianconi if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) 293e30a655eSLorenzo Bianconi return -EIO; 294134b2d0dSStanislaw Gruszka 295134b2d0dSStanislaw Gruszka ret = mt76x0_init_bbp(dev); 296134b2d0dSStanislaw Gruszka if (ret) 297e30a655eSLorenzo Bianconi return ret; 298134b2d0dSStanislaw Gruszka 299a31821abSLorenzo Bianconi dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 300a31821abSLorenzo Bianconi 301134b2d0dSStanislaw Gruszka ret = mt76x0_init_wcid_mem(dev); 302134b2d0dSStanislaw Gruszka if (ret) 303e30a655eSLorenzo Bianconi return ret; 304e30a655eSLorenzo Bianconi 305331419b2SStanislaw Gruszka mt76x0_init_key_mem(dev); 306e30a655eSLorenzo Bianconi 307134b2d0dSStanislaw Gruszka ret = mt76x0_init_wcid_attr_mem(dev); 308134b2d0dSStanislaw Gruszka if (ret) 309e30a655eSLorenzo Bianconi return ret; 310134b2d0dSStanislaw Gruszka 311134b2d0dSStanislaw Gruszka mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | 312134b2d0dSStanislaw Gruszka MT_BEACON_TIME_CFG_SYNC_MODE | 313134b2d0dSStanislaw Gruszka MT_BEACON_TIME_CFG_TBTT_EN | 314134b2d0dSStanislaw Gruszka MT_BEACON_TIME_CFG_BEACON_TX)); 315134b2d0dSStanislaw Gruszka 316134b2d0dSStanislaw Gruszka mt76x0_reset_counters(dev); 317134b2d0dSStanislaw Gruszka 318134b2d0dSStanislaw Gruszka ret = mt76x0_eeprom_init(dev); 319134b2d0dSStanislaw Gruszka if (ret) 320e30a655eSLorenzo Bianconi return ret; 321134b2d0dSStanislaw Gruszka 322134b2d0dSStanislaw Gruszka mt76x0_phy_init(dev); 323134b2d0dSStanislaw Gruszka 324e30a655eSLorenzo Bianconi return 0; 325134b2d0dSStanislaw Gruszka } 326c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_init_hardware); 327134b2d0dSStanislaw Gruszka 328b2d871c0SLorenzo Bianconi struct mt76x02_dev * 329b11e1969SLorenzo Bianconi mt76x0_alloc_device(struct device *pdev, 330b11e1969SLorenzo Bianconi const struct mt76_driver_ops *drv_ops, 331b11e1969SLorenzo Bianconi const struct ieee80211_ops *ops) 332134b2d0dSStanislaw Gruszka { 333b2d871c0SLorenzo Bianconi struct mt76x02_dev *dev; 33495e507d2SLorenzo Bianconi struct mt76_dev *mdev; 335134b2d0dSStanislaw Gruszka 336b11e1969SLorenzo Bianconi mdev = mt76_alloc_device(sizeof(*dev), ops); 33795e507d2SLorenzo Bianconi if (!mdev) 338134b2d0dSStanislaw Gruszka return NULL; 339134b2d0dSStanislaw Gruszka 34095e507d2SLorenzo Bianconi mdev->dev = pdev; 341835123b7SStanislaw Gruszka mdev->drv = drv_ops; 34295e507d2SLorenzo Bianconi 343b2d871c0SLorenzo Bianconi dev = container_of(mdev, struct mt76x02_dev, mt76); 344b2d871c0SLorenzo Bianconi mutex_init(&dev->phy_mutex); 345134b2d0dSStanislaw Gruszka atomic_set(&dev->avg_ampdu_len, 1); 346134b2d0dSStanislaw Gruszka 347134b2d0dSStanislaw Gruszka return dev; 348134b2d0dSStanislaw Gruszka } 349c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_alloc_device); 350134b2d0dSStanislaw Gruszka 351b2d871c0SLorenzo Bianconi int mt76x0_register_device(struct mt76x02_dev *dev) 352134b2d0dSStanislaw Gruszka { 3531bee323aSLorenzo Bianconi struct mt76_dev *mdev = &dev->mt76; 3541bee323aSLorenzo Bianconi struct ieee80211_hw *hw = mdev->hw; 355134b2d0dSStanislaw Gruszka struct wiphy *wiphy = hw->wiphy; 356134b2d0dSStanislaw Gruszka int ret; 357134b2d0dSStanislaw Gruszka 358134b2d0dSStanislaw Gruszka /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to 359134b2d0dSStanislaw Gruszka * entry no. 1 like it does in the vendor driver. 360134b2d0dSStanislaw Gruszka */ 3611bee323aSLorenzo Bianconi mdev->wcid_mask[0] |= 1; 362134b2d0dSStanislaw Gruszka 363134b2d0dSStanislaw Gruszka /* init fake wcid for monitor interfaces */ 3641bee323aSLorenzo Bianconi mdev->global_wcid.idx = 0xff; 3651bee323aSLorenzo Bianconi mdev->global_wcid.hw_key_idx = -1; 366134b2d0dSStanislaw Gruszka 3671bee323aSLorenzo Bianconi /* init antenna configuration */ 3681bee323aSLorenzo Bianconi mdev->antenna_mask = 1; 369134b2d0dSStanislaw Gruszka 370134b2d0dSStanislaw Gruszka hw->queues = 4; 371134b2d0dSStanislaw Gruszka hw->max_rates = 1; 372134b2d0dSStanislaw Gruszka hw->max_report_rates = 7; 373134b2d0dSStanislaw Gruszka hw->max_rate_tries = 1; 374493703aaSStanislaw Gruszka hw->extra_tx_headroom = sizeof(struct mt76x02_txwi) + 4 + 2; 375134b2d0dSStanislaw Gruszka 37616c8a792SStanislaw Gruszka hw->sta_data_size = sizeof(struct mt76x02_sta); 37798ff26e5SStanislaw Gruszka hw->vif_data_size = sizeof(struct mt76x02_vif); 378134b2d0dSStanislaw Gruszka 379134b2d0dSStanislaw Gruszka wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 380134b2d0dSStanislaw Gruszka 381134b2d0dSStanislaw Gruszka INIT_DELAYED_WORK(&dev->mac_work, mt76x0_mac_work); 382134b2d0dSStanislaw Gruszka 3831bee323aSLorenzo Bianconi ret = mt76_register_device(mdev, true, mt76x02_rates, 3841bee323aSLorenzo Bianconi ARRAY_SIZE(mt76x02_rates)); 385134b2d0dSStanislaw Gruszka if (ret) 386134b2d0dSStanislaw Gruszka return ret; 387134b2d0dSStanislaw Gruszka 3881bee323aSLorenzo Bianconi /* overwrite unsupported features */ 3891bee323aSLorenzo Bianconi if (mdev->cap.has_5ghz) 3901bee323aSLorenzo Bianconi mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband); 3911bee323aSLorenzo Bianconi 392134b2d0dSStanislaw Gruszka mt76x0_init_debugfs(dev); 393134b2d0dSStanislaw Gruszka 394134b2d0dSStanislaw Gruszka return 0; 395134b2d0dSStanislaw Gruszka } 396c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_register_device); 397