11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2134b2d0dSStanislaw Gruszka /*
3134b2d0dSStanislaw Gruszka * (c) Copyright 2002-2010, Ralink Technology, Inc.
4134b2d0dSStanislaw Gruszka * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
5134b2d0dSStanislaw Gruszka * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
6134b2d0dSStanislaw Gruszka * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
7134b2d0dSStanislaw Gruszka */
8134b2d0dSStanislaw Gruszka
9134b2d0dSStanislaw Gruszka #include "mt76x0.h"
10134b2d0dSStanislaw Gruszka #include "eeprom.h"
11134b2d0dSStanislaw Gruszka #include "mcu.h"
12134b2d0dSStanislaw Gruszka #include "initvals.h"
13328cecf3SLee Jones #include "initvals_init.h"
141ffe410eSLorenzo Bianconi #include "../mt76x02_phy.h"
15134b2d0dSStanislaw Gruszka
16134b2d0dSStanislaw Gruszka static void
mt76x0_set_wlan_state(struct mt76x02_dev * dev,u32 val,bool enable)17b2d871c0SLorenzo Bianconi mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable)
18134b2d0dSStanislaw Gruszka {
195b394355SLorenzo Bianconi u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD;
20134b2d0dSStanislaw Gruszka
21134b2d0dSStanislaw Gruszka /* Note: we don't turn off WLAN_CLK because that makes the device
22134b2d0dSStanislaw Gruszka * not respond properly on the probe path.
23134b2d0dSStanislaw Gruszka * In case anyone (PSM?) wants to use this function we can
24134b2d0dSStanislaw Gruszka * bring the clock stuff back and fixup the probe path.
25134b2d0dSStanislaw Gruszka */
26134b2d0dSStanislaw Gruszka
27134b2d0dSStanislaw Gruszka if (enable)
28134b2d0dSStanislaw Gruszka val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
29134b2d0dSStanislaw Gruszka MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
30134b2d0dSStanislaw Gruszka else
31134b2d0dSStanislaw Gruszka val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
32134b2d0dSStanislaw Gruszka
33134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
34134b2d0dSStanislaw Gruszka udelay(20);
35134b2d0dSStanislaw Gruszka
36134b2d0dSStanislaw Gruszka /* Note: vendor driver tries to disable/enable wlan here and retry
37134b2d0dSStanislaw Gruszka * but the code which does it is so buggy it must have never
38134b2d0dSStanislaw Gruszka * triggered, so don't bother.
39134b2d0dSStanislaw Gruszka */
405b394355SLorenzo Bianconi if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000))
415b394355SLorenzo Bianconi dev_err(dev->mt76.dev, "PLL and XTAL check failed\n");
42134b2d0dSStanislaw Gruszka }
43134b2d0dSStanislaw Gruszka
mt76x0_chip_onoff(struct mt76x02_dev * dev,bool enable,bool reset)44b2d871c0SLorenzo Bianconi void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset)
45134b2d0dSStanislaw Gruszka {
46134b2d0dSStanislaw Gruszka u32 val;
47134b2d0dSStanislaw Gruszka
48134b2d0dSStanislaw Gruszka val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
49134b2d0dSStanislaw Gruszka
50134b2d0dSStanislaw Gruszka if (reset) {
51134b2d0dSStanislaw Gruszka val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
52134b2d0dSStanislaw Gruszka val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
53134b2d0dSStanislaw Gruszka
54134b2d0dSStanislaw Gruszka if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
55134b2d0dSStanislaw Gruszka val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
56134b2d0dSStanislaw Gruszka MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
57134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
58134b2d0dSStanislaw Gruszka udelay(20);
59134b2d0dSStanislaw Gruszka
60134b2d0dSStanislaw Gruszka val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
61134b2d0dSStanislaw Gruszka MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
62134b2d0dSStanislaw Gruszka }
63134b2d0dSStanislaw Gruszka }
64134b2d0dSStanislaw Gruszka
65134b2d0dSStanislaw Gruszka mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
66134b2d0dSStanislaw Gruszka udelay(20);
67134b2d0dSStanislaw Gruszka
68134b2d0dSStanislaw Gruszka mt76x0_set_wlan_state(dev, val, enable);
69134b2d0dSStanislaw Gruszka }
70c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_chip_onoff);
71134b2d0dSStanislaw Gruszka
mt76x0_reset_csr_bbp(struct mt76x02_dev * dev)72b2d871c0SLorenzo Bianconi static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev)
73134b2d0dSStanislaw Gruszka {
74512bd4b1SLorenzo Bianconi mt76_wr(dev, MT_MAC_SYS_CTRL,
75512bd4b1SLorenzo Bianconi MT_MAC_SYS_CTRL_RESET_CSR |
76134b2d0dSStanislaw Gruszka MT_MAC_SYS_CTRL_RESET_BBP);
77134b2d0dSStanislaw Gruszka msleep(200);
782b2cb40bSLorenzo Bianconi mt76_clear(dev, MT_MAC_SYS_CTRL,
792b2cb40bSLorenzo Bianconi MT_MAC_SYS_CTRL_RESET_CSR |
802b2cb40bSLorenzo Bianconi MT_MAC_SYS_CTRL_RESET_BBP);
81134b2d0dSStanislaw Gruszka }
82134b2d0dSStanislaw Gruszka
83134b2d0dSStanislaw Gruszka #define RANDOM_WRITE(dev, tab) \
8417507157SLorenzo Bianconi mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \
85f1638c7cSStanislaw Gruszka tab, ARRAY_SIZE(tab))
86134b2d0dSStanislaw Gruszka
mt76x0_init_bbp(struct mt76x02_dev * dev)87b2d871c0SLorenzo Bianconi static int mt76x0_init_bbp(struct mt76x02_dev *dev)
88134b2d0dSStanislaw Gruszka {
89134b2d0dSStanislaw Gruszka int ret, i;
90134b2d0dSStanislaw Gruszka
919c410782SLorenzo Bianconi ret = mt76x0_phy_wait_bbp_ready(dev);
92134b2d0dSStanislaw Gruszka if (ret)
93134b2d0dSStanislaw Gruszka return ret;
94134b2d0dSStanislaw Gruszka
95134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, mt76x0_bbp_init_tab);
96134b2d0dSStanislaw Gruszka
97134b2d0dSStanislaw Gruszka for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) {
98134b2d0dSStanislaw Gruszka const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i];
99134b2d0dSStanislaw Gruszka const struct mt76_reg_pair *pair = &item->reg_pair;
100134b2d0dSStanislaw Gruszka
101134b2d0dSStanislaw Gruszka if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20))
102134b2d0dSStanislaw Gruszka mt76_wr(dev, pair->reg, pair->value);
103134b2d0dSStanislaw Gruszka }
104134b2d0dSStanislaw Gruszka
105134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, mt76x0_dcoc_tab);
106134b2d0dSStanislaw Gruszka
107134b2d0dSStanislaw Gruszka return 0;
108134b2d0dSStanislaw Gruszka }
109134b2d0dSStanislaw Gruszka
mt76x0_init_mac_registers(struct mt76x02_dev * dev)110b2d871c0SLorenzo Bianconi static void mt76x0_init_mac_registers(struct mt76x02_dev *dev)
111134b2d0dSStanislaw Gruszka {
112134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, common_mac_reg_table);
113134b2d0dSStanislaw Gruszka
114134b2d0dSStanislaw Gruszka /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
115134b2d0dSStanislaw Gruszka RANDOM_WRITE(dev, mt76x0_mac_reg_table);
116134b2d0dSStanislaw Gruszka
117134b2d0dSStanislaw Gruszka /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */
11800eccdd6SLorenzo Bianconi mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3);
119134b2d0dSStanislaw Gruszka
120134b2d0dSStanislaw Gruszka /* Set 0x141C[15:12]=0xF */
12100eccdd6SLorenzo Bianconi mt76_set(dev, MT_EXT_CCA_CFG, 0xf000);
122134b2d0dSStanislaw Gruszka
123134b2d0dSStanislaw Gruszka mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
124134b2d0dSStanislaw Gruszka
125134b2d0dSStanislaw Gruszka /*
12600eccdd6SLorenzo Bianconi * tx_ring 9 is for mgmt frame
12700eccdd6SLorenzo Bianconi * tx_ring 8 is for in-band command frame.
12800eccdd6SLorenzo Bianconi * WMM_RG0_TXQMA: this register setting is for FCE to
12900eccdd6SLorenzo Bianconi * define the rule of tx_ring 9
13000eccdd6SLorenzo Bianconi * WMM_RG1_TXQMA: this register setting is for FCE to
13100eccdd6SLorenzo Bianconi * define the rule of tx_ring 8
132134b2d0dSStanislaw Gruszka */
13300eccdd6SLorenzo Bianconi mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201);
134134b2d0dSStanislaw Gruszka }
135134b2d0dSStanislaw Gruszka
mt76x0_mac_stop(struct mt76x02_dev * dev)136b2d871c0SLorenzo Bianconi void mt76x0_mac_stop(struct mt76x02_dev *dev)
137134b2d0dSStanislaw Gruszka {
138b11e1969SLorenzo Bianconi int i = 200, ok = 0;
139134b2d0dSStanislaw Gruszka
1404606a26cSFelix Fietkau mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
1414606a26cSFelix Fietkau
142134b2d0dSStanislaw Gruszka /* Page count on TxQ */
143134b2d0dSStanislaw Gruszka while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
144134b2d0dSStanislaw Gruszka (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
145134b2d0dSStanislaw Gruszka (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
146134b2d0dSStanislaw Gruszka msleep(10);
147134b2d0dSStanislaw Gruszka
148134b2d0dSStanislaw Gruszka if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
149134b2d0dSStanislaw Gruszka dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n");
150134b2d0dSStanislaw Gruszka
151134b2d0dSStanislaw Gruszka mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
152134b2d0dSStanislaw Gruszka MT_MAC_SYS_CTRL_ENABLE_TX);
153134b2d0dSStanislaw Gruszka
154134b2d0dSStanislaw Gruszka /* Page count on RxQ */
155b11e1969SLorenzo Bianconi for (i = 0; i < 200; i++) {
156134b2d0dSStanislaw Gruszka if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
157134b2d0dSStanislaw Gruszka !mt76_rr(dev, 0x0a30) &&
158134b2d0dSStanislaw Gruszka !mt76_rr(dev, 0x0a34)) {
159134b2d0dSStanislaw Gruszka if (ok++ > 5)
160134b2d0dSStanislaw Gruszka break;
161134b2d0dSStanislaw Gruszka continue;
162134b2d0dSStanislaw Gruszka }
163134b2d0dSStanislaw Gruszka msleep(1);
164134b2d0dSStanislaw Gruszka }
165134b2d0dSStanislaw Gruszka
166134b2d0dSStanislaw Gruszka if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
167134b2d0dSStanislaw Gruszka dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n");
168134b2d0dSStanislaw Gruszka }
169c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_mac_stop);
170134b2d0dSStanislaw Gruszka
mt76x0_init_hardware(struct mt76x02_dev * dev)171b2d871c0SLorenzo Bianconi int mt76x0_init_hardware(struct mt76x02_dev *dev)
172134b2d0dSStanislaw Gruszka {
17348c76588SLorenzo Bianconi int ret, i, k;
174134b2d0dSStanislaw Gruszka
1753b11db26SLorenzo Bianconi if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000))
176e30a655eSLorenzo Bianconi return -EIO;
177134b2d0dSStanislaw Gruszka
178134b2d0dSStanislaw Gruszka /* Wait for ASIC ready after FW load. */
179e30a655eSLorenzo Bianconi if (!mt76x02_wait_for_mac(&dev->mt76))
180e30a655eSLorenzo Bianconi return -ETIMEDOUT;
181134b2d0dSStanislaw Gruszka
182134b2d0dSStanislaw Gruszka mt76x0_reset_csr_bbp(dev);
1833d2d61b5SStanislaw Gruszka ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1);
184134b2d0dSStanislaw Gruszka if (ret)
185e30a655eSLorenzo Bianconi return ret;
18630ec9152SLorenzo Bianconi
187134b2d0dSStanislaw Gruszka mt76x0_init_mac_registers(dev);
188134b2d0dSStanislaw Gruszka
1893b11db26SLorenzo Bianconi if (!mt76x02_wait_for_txrx_idle(&dev->mt76))
190e30a655eSLorenzo Bianconi return -EIO;
191134b2d0dSStanislaw Gruszka
192134b2d0dSStanislaw Gruszka ret = mt76x0_init_bbp(dev);
193134b2d0dSStanislaw Gruszka if (ret)
194e30a655eSLorenzo Bianconi return ret;
195134b2d0dSStanislaw Gruszka
196a31821abSLorenzo Bianconi dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
197a31821abSLorenzo Bianconi
19848c76588SLorenzo Bianconi for (i = 0; i < 16; i++)
19948c76588SLorenzo Bianconi for (k = 0; k < 4; k++)
20048c76588SLorenzo Bianconi mt76x02_mac_shared_key_setup(dev, i, k, NULL);
201e30a655eSLorenzo Bianconi
20224702cdbSLorenzo Bianconi for (i = 0; i < 256; i++)
20324702cdbSLorenzo Bianconi mt76x02_mac_wcid_setup(dev, i, 0, NULL);
204134b2d0dSStanislaw Gruszka
205134b2d0dSStanislaw Gruszka ret = mt76x0_eeprom_init(dev);
206134b2d0dSStanislaw Gruszka if (ret)
207e30a655eSLorenzo Bianconi return ret;
208134b2d0dSStanislaw Gruszka
209134b2d0dSStanislaw Gruszka mt76x0_phy_init(dev);
210134b2d0dSStanislaw Gruszka
211e30a655eSLorenzo Bianconi return 0;
212134b2d0dSStanislaw Gruszka }
213c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_init_hardware);
214134b2d0dSStanislaw Gruszka
2151ffe410eSLorenzo Bianconi static void
mt76x0_init_txpower(struct mt76x02_dev * dev,struct ieee80211_supported_band * sband)2161ffe410eSLorenzo Bianconi mt76x0_init_txpower(struct mt76x02_dev *dev,
2171ffe410eSLorenzo Bianconi struct ieee80211_supported_band *sband)
2181ffe410eSLorenzo Bianconi {
2191ffe410eSLorenzo Bianconi struct ieee80211_channel *chan;
220*b376d963SFelix Fietkau struct mt76x02_rate_power t;
2211ffe410eSLorenzo Bianconi s8 tp;
2221ffe410eSLorenzo Bianconi int i;
2231ffe410eSLorenzo Bianconi
2241ffe410eSLorenzo Bianconi for (i = 0; i < sband->n_channels; i++) {
2251ffe410eSLorenzo Bianconi chan = &sband->channels[i];
2261ffe410eSLorenzo Bianconi
2271ffe410eSLorenzo Bianconi mt76x0_get_tx_power_per_rate(dev, chan, &t);
2281ffe410eSLorenzo Bianconi mt76x0_get_power_info(dev, chan, &tp);
2291ffe410eSLorenzo Bianconi
23009952572SFelix Fietkau chan->orig_mpwr = (mt76x02_get_max_rate_power(&t) + tp) / 2;
23109952572SFelix Fietkau chan->max_power = min_t(int, chan->max_reg_power,
23209952572SFelix Fietkau chan->orig_mpwr);
2331ffe410eSLorenzo Bianconi }
2341ffe410eSLorenzo Bianconi }
2351ffe410eSLorenzo Bianconi
mt76x0_register_device(struct mt76x02_dev * dev)236b2d871c0SLorenzo Bianconi int mt76x0_register_device(struct mt76x02_dev *dev)
237134b2d0dSStanislaw Gruszka {
238134b2d0dSStanislaw Gruszka int ret;
239134b2d0dSStanislaw Gruszka
240633f77b5SLorenzo Bianconi ret = mt76x02_init_device(dev);
241633f77b5SLorenzo Bianconi if (ret)
242633f77b5SLorenzo Bianconi return ret;
243633f77b5SLorenzo Bianconi
244269906acSLorenzo Bianconi mt76x02_config_mac_addr_list(dev);
245269906acSLorenzo Bianconi
2465cbace02SLorenzo Bianconi ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
2471bee323aSLorenzo Bianconi ARRAY_SIZE(mt76x02_rates));
248134b2d0dSStanislaw Gruszka if (ret)
249134b2d0dSStanislaw Gruszka return ret;
250134b2d0dSStanislaw Gruszka
25148dbce5cSLorenzo Bianconi if (dev->mphy.cap.has_5ghz) {
25265ba7fa4SLorenzo Bianconi struct ieee80211_supported_band *sband;
25365ba7fa4SLorenzo Bianconi
25465ba7fa4SLorenzo Bianconi sband = &dev->mphy.sband_5g.sband;
25565ba7fa4SLorenzo Bianconi sband->vht_cap.cap &= ~IEEE80211_VHT_CAP_RXLDPC;
25665ba7fa4SLorenzo Bianconi mt76x0_init_txpower(dev, sband);
2571ffe410eSLorenzo Bianconi }
2581ffe410eSLorenzo Bianconi
25948dbce5cSLorenzo Bianconi if (dev->mphy.cap.has_2ghz)
26096747a51SFelix Fietkau mt76x0_init_txpower(dev, &dev->mphy.sband_2g.sband);
2611bee323aSLorenzo Bianconi
26263f15d94SLorenzo Bianconi mt76x02_init_debugfs(dev);
263134b2d0dSStanislaw Gruszka
264134b2d0dSStanislaw Gruszka return 0;
265134b2d0dSStanislaw Gruszka }
266c2a4d9fbSStanislaw Gruszka EXPORT_SYMBOL_GPL(mt76x0_register_device);
267