1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_H 5 #define __MT76_CONNAC_H 6 7 #include "mt76.h" 8 9 #define MT76_CONNAC_SCAN_IE_LEN 600 10 #define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL 10 11 #define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX 12 #define MT76_CONNAC_MAX_SCHED_SCAN_SSID 10 13 #define MT76_CONNAC_MAX_SCAN_MATCH 16 14 15 #define MT76_CONNAC_MAX_WMM_SETS 4 16 17 #define MT76_CONNAC_COREDUMP_TIMEOUT (HZ / 20) 18 #define MT76_CONNAC_COREDUMP_SZ (1300 * 1024) 19 20 #define MT_TXD_SIZE (8 * 4) 21 22 #define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 23 #define MT_USB_HDR_SIZE 4 24 #define MT_USB_TAIL_SIZE 4 25 26 #define MT_SDIO_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 27 #define MT_SDIO_TAIL_SIZE 8 28 #define MT_SDIO_HDR_SIZE 4 29 30 #define MT_MSDU_ID_VALID BIT(15) 31 32 #define MT_TXD_LEN_LAST BIT(15) 33 #define MT_TXD_LEN_MASK GENMASK(11, 0) 34 #define MT_TXD_LEN_MSDU_LAST BIT(14) 35 #define MT_TXD_LEN_AMSDU_LAST BIT(15) 36 37 enum { 38 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 39 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 40 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 41 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 42 CMD_CBW_10MHZ, 43 CMD_CBW_5MHZ, 44 CMD_CBW_8080MHZ, 45 46 CMD_HE_MCS_BW80 = 0, 47 CMD_HE_MCS_BW160, 48 CMD_HE_MCS_BW8080, 49 CMD_HE_MCS_BW_NUM 50 }; 51 52 enum { 53 HW_BSSID_0 = 0x0, 54 HW_BSSID_1, 55 HW_BSSID_2, 56 HW_BSSID_3, 57 HW_BSSID_MAX = HW_BSSID_3, 58 EXT_BSSID_START = 0x10, 59 EXT_BSSID_1, 60 EXT_BSSID_15 = 0x1f, 61 EXT_BSSID_MAX = EXT_BSSID_15, 62 REPEATER_BSSID_START = 0x20, 63 REPEATER_BSSID_MAX = 0x3f, 64 }; 65 66 struct mt76_connac_pm { 67 bool enable:1; 68 bool enable_user:1; 69 bool ds_enable:1; 70 bool ds_enable_user:1; 71 bool suspended:1; 72 73 spinlock_t txq_lock; 74 struct { 75 struct mt76_wcid *wcid; 76 struct sk_buff *skb; 77 } tx_q[IEEE80211_NUM_ACS]; 78 79 struct work_struct wake_work; 80 wait_queue_head_t wait; 81 82 struct { 83 spinlock_t lock; 84 u32 count; 85 } wake; 86 struct mutex mutex; 87 88 struct delayed_work ps_work; 89 unsigned long last_activity; 90 unsigned long idle_timeout; 91 92 struct { 93 unsigned long last_wake_event; 94 unsigned long awake_time; 95 unsigned long last_doze_event; 96 unsigned long doze_time; 97 unsigned int lp_wake; 98 } stats; 99 }; 100 101 struct mt76_connac_coredump { 102 struct sk_buff_head msg_list; 103 struct delayed_work work; 104 unsigned long last_activity; 105 }; 106 107 struct mt76_connac_sta_key_conf { 108 s8 keyidx; 109 u8 key[16]; 110 }; 111 112 #define MT_TXP_MAX_BUF_NUM 6 113 114 struct mt76_connac_fw_txp { 115 __le16 flags; 116 __le16 token; 117 u8 bss_idx; 118 __le16 rept_wds_wcid; 119 u8 nbuf; 120 __le32 buf[MT_TXP_MAX_BUF_NUM]; 121 __le16 len[MT_TXP_MAX_BUF_NUM]; 122 } __packed __aligned(4); 123 124 #define MT_HW_TXP_MAX_MSDU_NUM 4 125 #define MT_HW_TXP_MAX_BUF_NUM 4 126 127 struct mt76_connac_txp_ptr { 128 __le32 buf0; 129 __le16 len0; 130 __le16 len1; 131 __le32 buf1; 132 } __packed __aligned(4); 133 134 struct mt76_connac_hw_txp { 135 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM]; 136 struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2]; 137 } __packed __aligned(4); 138 139 struct mt76_connac_txp_common { 140 union { 141 struct mt76_connac_fw_txp fw; 142 struct mt76_connac_hw_txp hw; 143 }; 144 }; 145 146 struct mt76_connac_tx_free { 147 __le16 rx_byte_cnt; 148 __le16 ctrl; 149 __le32 txd; 150 } __packed __aligned(4); 151 152 extern const struct wiphy_wowlan_support mt76_connac_wowlan_support; 153 154 static inline bool is_mt7922(struct mt76_dev *dev) 155 { 156 return mt76_chip(dev) == 0x7922; 157 } 158 159 static inline bool is_mt7921(struct mt76_dev *dev) 160 { 161 return mt76_chip(dev) == 0x7961 || is_mt7922(dev); 162 } 163 164 static inline bool is_mt7663(struct mt76_dev *dev) 165 { 166 return mt76_chip(dev) == 0x7663; 167 } 168 169 static inline bool is_mt7915(struct mt76_dev *dev) 170 { 171 return mt76_chip(dev) == 0x7915; 172 } 173 174 static inline bool is_mt7916(struct mt76_dev *dev) 175 { 176 return mt76_chip(dev) == 0x7906; 177 } 178 179 static inline bool is_mt7986(struct mt76_dev *dev) 180 { 181 return mt76_chip(dev) == 0x7986; 182 } 183 184 static inline bool is_mt7622(struct mt76_dev *dev) 185 { 186 if (!IS_ENABLED(CONFIG_MT7622_WMAC)) 187 return false; 188 189 return mt76_chip(dev) == 0x7622; 190 } 191 192 static inline bool is_mt7615(struct mt76_dev *dev) 193 { 194 return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611; 195 } 196 197 static inline bool is_mt7611(struct mt76_dev *dev) 198 { 199 return mt76_chip(dev) == 0x7611; 200 } 201 202 static inline bool is_connac_v1(struct mt76_dev *dev) 203 { 204 return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev); 205 } 206 207 static inline bool is_mt76_fw_txp(struct mt76_dev *dev) 208 { 209 switch (mt76_chip(dev)) { 210 case 0x7961: 211 case 0x7922: 212 case 0x7663: 213 case 0x7622: 214 return false; 215 default: 216 return true; 217 } 218 } 219 220 static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef) 221 { 222 static const u8 width_to_bw[] = { 223 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ, 224 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ, 225 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ, 226 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ, 227 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ, 228 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ, 229 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ, 230 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ, 231 }; 232 233 if (chandef->width >= ARRAY_SIZE(width_to_bw)) 234 return 0; 235 236 return width_to_bw[chandef->width]; 237 } 238 239 static inline u8 mt76_connac_lmac_mapping(u8 ac) 240 { 241 /* LMAC uses the reverse order of mac80211 AC indexes */ 242 return 3 - ac; 243 } 244 245 static inline void * 246 mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t) 247 { 248 u8 *txwi; 249 250 if (!t) 251 return NULL; 252 253 txwi = mt76_get_txwi_ptr(dev, t); 254 255 return (void *)(txwi + MT_TXD_SIZE); 256 } 257 258 int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm); 259 void mt76_connac_power_save_sched(struct mt76_phy *phy, 260 struct mt76_connac_pm *pm); 261 void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm, 262 struct mt76_wcid *wcid); 263 264 static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev) 265 { 266 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false); 267 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false); 268 } 269 270 static inline bool 271 mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 272 { 273 bool ret = false; 274 275 spin_lock_bh(&pm->wake.lock); 276 if (test_bit(MT76_STATE_PM, &phy->state)) 277 goto out; 278 279 pm->wake.count++; 280 ret = true; 281 out: 282 spin_unlock_bh(&pm->wake.lock); 283 284 return ret; 285 } 286 287 static inline void 288 mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 289 { 290 spin_lock_bh(&pm->wake.lock); 291 292 pm->last_activity = jiffies; 293 if (--pm->wake.count == 0 && 294 test_bit(MT76_STATE_MCU_RUNNING, &phy->state)) 295 mt76_connac_power_save_sched(phy, pm); 296 297 spin_unlock_bh(&pm->wake.lock); 298 } 299 300 static inline bool 301 mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm) 302 { 303 struct mt76_dev *dev = phy->dev; 304 bool ret; 305 306 if (dev->token_count) 307 return true; 308 309 spin_lock_bh(&pm->wake.lock); 310 ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state); 311 spin_unlock_bh(&pm->wake.lock); 312 313 return ret; 314 } 315 316 static inline void 317 mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm) 318 __acquires(&dev->mutex) 319 { 320 mutex_lock(&dev->mutex); 321 mt76_connac_pm_wake(&dev->phy, pm); 322 } 323 324 static inline void 325 mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm) 326 __releases(&dev->mutex) 327 { 328 mt76_connac_power_save_sched(&dev->phy, pm); 329 mutex_unlock(&dev->mutex); 330 } 331 332 int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc, 333 int ring_base, u32 flags); 334 void mt76_connac_write_hw_txp(struct mt76_dev *dev, 335 struct mt76_tx_info *tx_info, 336 void *txp_ptr, u32 id); 337 void mt76_connac_txp_skb_unmap(struct mt76_dev *dev, 338 struct mt76_txwi_cache *txwi); 339 void mt76_connac_tx_complete_skb(struct mt76_dev *mdev, 340 struct mt76_queue_entry *e); 341 void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw, 342 struct mt76_connac_pm *pm, 343 struct mt76_wcid *wcid, 344 struct sk_buff *skb); 345 void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy, 346 struct mt76_connac_pm *pm); 347 void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 348 struct sk_buff *skb, struct mt76_wcid *wcid, 349 struct ieee80211_key_conf *key, int pid, 350 enum mt76_txq_id qid, u32 changed); 351 bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid, 352 int pid, __le32 *txs_data, 353 struct mt76_sta_stats *stats); 354 void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev, 355 struct sk_buff *skb, 356 __le32 *rxv, u32 mode); 357 int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif, 358 struct sk_buff *skb, u16 hdr_offset); 359 int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev, 360 struct mt76_rx_status *status, 361 struct ieee80211_supported_band *sband, 362 __le32 *rxv, u8 *mode); 363 364 #endif /* __MT76_CONNAC_H */ 365