1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #ifndef __MT76_CONNAC_H
5 #define __MT76_CONNAC_H
6 
7 #include "mt76.h"
8 
9 enum rx_pkt_type {
10 	PKT_TYPE_TXS,
11 	PKT_TYPE_TXRXV,
12 	PKT_TYPE_NORMAL,
13 	PKT_TYPE_RX_DUP_RFB,
14 	PKT_TYPE_RX_TMR,
15 	PKT_TYPE_RETRIEVE,
16 	PKT_TYPE_TXRX_NOTIFY,
17 	PKT_TYPE_RX_EVENT,
18 	PKT_TYPE_NORMAL_MCU,
19 	PKT_TYPE_RX_FW_MONITOR	= 0x0c,
20 	PKT_TYPE_TXRX_NOTIFY_V0	= 0x18,
21 };
22 
23 #define MT76_CONNAC_SCAN_IE_LEN			600
24 #define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL	 10
25 #define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX
26 #define MT76_CONNAC_MAX_SCHED_SCAN_SSID		10
27 #define MT76_CONNAC_MAX_SCAN_MATCH		16
28 
29 #define MT76_CONNAC_MAX_WMM_SETS		4
30 
31 #define MT76_CONNAC_COREDUMP_TIMEOUT		(HZ / 20)
32 #define MT76_CONNAC_COREDUMP_SZ			(1300 * 1024)
33 
34 #define MT_TXD_SIZE				(8 * 4)
35 
36 #define MT_USB_TXD_SIZE				(MT_TXD_SIZE + 8 * 4)
37 #define MT_USB_HDR_SIZE				4
38 #define MT_USB_TAIL_SIZE			4
39 
40 #define MT_SDIO_TXD_SIZE			(MT_TXD_SIZE + 8 * 4)
41 #define MT_SDIO_TAIL_SIZE			8
42 #define MT_SDIO_HDR_SIZE			4
43 
44 #define MT_MSDU_ID_VALID		BIT(15)
45 
46 #define MT_TXD_LEN_LAST			BIT(15)
47 #define MT_TXD_LEN_MASK			GENMASK(11, 0)
48 #define MT_TXD_LEN_MSDU_LAST		BIT(14)
49 #define MT_TXD_LEN_AMSDU_LAST		BIT(15)
50 
51 enum {
52 	CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
53 	CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
54 	CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
55 	CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
56 	CMD_CBW_10MHZ,
57 	CMD_CBW_5MHZ,
58 	CMD_CBW_8080MHZ,
59 	CMD_CBW_320MHZ,
60 
61 	CMD_HE_MCS_BW80 = 0,
62 	CMD_HE_MCS_BW160,
63 	CMD_HE_MCS_BW8080,
64 	CMD_HE_MCS_BW_NUM
65 };
66 
67 enum {
68 	HW_BSSID_0 = 0x0,
69 	HW_BSSID_1,
70 	HW_BSSID_2,
71 	HW_BSSID_3,
72 	HW_BSSID_MAX = HW_BSSID_3,
73 	EXT_BSSID_START = 0x10,
74 	EXT_BSSID_1,
75 	EXT_BSSID_15 = 0x1f,
76 	EXT_BSSID_MAX = EXT_BSSID_15,
77 	REPEATER_BSSID_START = 0x20,
78 	REPEATER_BSSID_MAX = 0x3f,
79 };
80 
81 struct mt76_connac_reg_map {
82 	u32 phys;
83 	u32 maps;
84 	u32 size;
85 };
86 
87 struct mt76_connac_pm {
88 	bool enable:1;
89 	bool enable_user:1;
90 	bool ds_enable:1;
91 	bool ds_enable_user:1;
92 	bool suspended:1;
93 
94 	spinlock_t txq_lock;
95 	struct {
96 		struct mt76_wcid *wcid;
97 		struct sk_buff *skb;
98 	} tx_q[IEEE80211_NUM_ACS];
99 
100 	struct work_struct wake_work;
101 	wait_queue_head_t wait;
102 
103 	struct {
104 		spinlock_t lock;
105 		u32 count;
106 	} wake;
107 	struct mutex mutex;
108 
109 	struct delayed_work ps_work;
110 	unsigned long last_activity;
111 	unsigned long idle_timeout;
112 
113 	struct {
114 		unsigned long last_wake_event;
115 		unsigned long awake_time;
116 		unsigned long last_doze_event;
117 		unsigned long doze_time;
118 		unsigned int lp_wake;
119 	} stats;
120 };
121 
122 struct mt76_connac_coredump {
123 	struct sk_buff_head msg_list;
124 	struct delayed_work work;
125 	unsigned long last_activity;
126 };
127 
128 struct mt76_connac_sta_key_conf {
129 	s8 keyidx;
130 	u8 key[16];
131 };
132 
133 #define MT_TXP_MAX_BUF_NUM		6
134 
135 struct mt76_connac_fw_txp {
136 	__le16 flags;
137 	__le16 token;
138 	u8 bss_idx;
139 	__le16 rept_wds_wcid;
140 	u8 nbuf;
141 	__le32 buf[MT_TXP_MAX_BUF_NUM];
142 	__le16 len[MT_TXP_MAX_BUF_NUM];
143 } __packed __aligned(4);
144 
145 #define MT_HW_TXP_MAX_MSDU_NUM		4
146 #define MT_HW_TXP_MAX_BUF_NUM		4
147 
148 struct mt76_connac_txp_ptr {
149 	__le32 buf0;
150 	__le16 len0;
151 	__le16 len1;
152 	__le32 buf1;
153 } __packed __aligned(4);
154 
155 struct mt76_connac_hw_txp {
156 	__le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
157 	struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
158 } __packed __aligned(4);
159 
160 struct mt76_connac_txp_common {
161 	union {
162 		struct mt76_connac_fw_txp fw;
163 		struct mt76_connac_hw_txp hw;
164 	};
165 };
166 
167 struct mt76_connac_tx_free {
168 	__le16 rx_byte_cnt;
169 	__le16 ctrl;
170 	__le32 txd;
171 } __packed __aligned(4);
172 
173 extern const struct wiphy_wowlan_support mt76_connac_wowlan_support;
174 
175 static inline bool is_mt7922(struct mt76_dev *dev)
176 {
177 	return mt76_chip(dev) == 0x7922;
178 }
179 
180 static inline bool is_mt7921(struct mt76_dev *dev)
181 {
182 	return mt76_chip(dev) == 0x7961 || is_mt7922(dev);
183 }
184 
185 static inline bool is_mt7663(struct mt76_dev *dev)
186 {
187 	return mt76_chip(dev) == 0x7663;
188 }
189 
190 static inline bool is_mt7915(struct mt76_dev *dev)
191 {
192 	return mt76_chip(dev) == 0x7915;
193 }
194 
195 static inline bool is_mt7916(struct mt76_dev *dev)
196 {
197 	return mt76_chip(dev) == 0x7906;
198 }
199 
200 static inline bool is_mt7986(struct mt76_dev *dev)
201 {
202 	return mt76_chip(dev) == 0x7986;
203 }
204 
205 static inline bool is_mt7996(struct mt76_dev *dev)
206 {
207 	return mt76_chip(dev) == 0x7990;
208 }
209 
210 static inline bool is_mt7622(struct mt76_dev *dev)
211 {
212 	if (!IS_ENABLED(CONFIG_MT7622_WMAC))
213 		return false;
214 
215 	return mt76_chip(dev) == 0x7622;
216 }
217 
218 static inline bool is_mt7615(struct mt76_dev *dev)
219 {
220 	return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611;
221 }
222 
223 static inline bool is_mt7611(struct mt76_dev *dev)
224 {
225 	return mt76_chip(dev) == 0x7611;
226 }
227 
228 static inline bool is_connac_v1(struct mt76_dev *dev)
229 {
230 	return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev);
231 }
232 
233 static inline bool is_mt76_fw_txp(struct mt76_dev *dev)
234 {
235 	switch (mt76_chip(dev)) {
236 	case 0x7961:
237 	case 0x7922:
238 	case 0x7663:
239 	case 0x7622:
240 		return false;
241 	default:
242 		return true;
243 	}
244 }
245 
246 static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef)
247 {
248 	static const u8 width_to_bw[] = {
249 		[NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
250 		[NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
251 		[NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
252 		[NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
253 		[NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
254 		[NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
255 		[NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
256 		[NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
257 		[NL80211_CHAN_WIDTH_320] = CMD_CBW_320MHZ,
258 	};
259 
260 	if (chandef->width >= ARRAY_SIZE(width_to_bw))
261 		return 0;
262 
263 	return width_to_bw[chandef->width];
264 }
265 
266 static inline u8 mt76_connac_lmac_mapping(u8 ac)
267 {
268 	/* LMAC uses the reverse order of mac80211 AC indexes */
269 	return 3 - ac;
270 }
271 
272 static inline void *
273 mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
274 {
275 	u8 *txwi;
276 
277 	if (!t)
278 		return NULL;
279 
280 	txwi = mt76_get_txwi_ptr(dev, t);
281 
282 	return (void *)(txwi + MT_TXD_SIZE);
283 }
284 
285 static inline u8 mt76_connac_spe_idx(u8 antenna_mask)
286 {
287 	static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0,
288 					9, 8, 6, 10, 16, 12, 18, 0};
289 
290 	if (antenna_mask >= sizeof(ant_to_spe))
291 		return 0;
292 
293 	return ant_to_spe[antenna_mask];
294 }
295 
296 static inline void mt76_connac_irq_enable(struct mt76_dev *dev, u32 mask)
297 {
298 	mt76_set_irq_mask(dev, 0, 0, mask);
299 	tasklet_schedule(&dev->irq_tasklet);
300 }
301 
302 int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm);
303 void mt76_connac_power_save_sched(struct mt76_phy *phy,
304 				  struct mt76_connac_pm *pm);
305 void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,
306 				      struct mt76_wcid *wcid);
307 
308 static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev)
309 {
310 	dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false);
311 	dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false);
312 }
313 
314 static inline bool
315 mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
316 {
317 	bool ret = false;
318 
319 	spin_lock_bh(&pm->wake.lock);
320 	if (test_bit(MT76_STATE_PM, &phy->state))
321 		goto out;
322 
323 	pm->wake.count++;
324 	ret = true;
325 out:
326 	spin_unlock_bh(&pm->wake.lock);
327 
328 	return ret;
329 }
330 
331 static inline void
332 mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
333 {
334 	spin_lock_bh(&pm->wake.lock);
335 
336 	pm->last_activity = jiffies;
337 	if (--pm->wake.count == 0 &&
338 	    test_bit(MT76_STATE_MCU_RUNNING, &phy->state))
339 		mt76_connac_power_save_sched(phy, pm);
340 
341 	spin_unlock_bh(&pm->wake.lock);
342 }
343 
344 static inline bool
345 mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm)
346 {
347 	struct mt76_dev *dev = phy->dev;
348 	bool ret;
349 
350 	if (dev->token_count)
351 		return true;
352 
353 	spin_lock_bh(&pm->wake.lock);
354 	ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state);
355 	spin_unlock_bh(&pm->wake.lock);
356 
357 	return ret;
358 }
359 
360 static inline void
361 mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm)
362 	__acquires(&dev->mutex)
363 {
364 	mutex_lock(&dev->mutex);
365 	mt76_connac_pm_wake(&dev->phy, pm);
366 }
367 
368 static inline void
369 mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm)
370 	__releases(&dev->mutex)
371 {
372 	mt76_connac_power_save_sched(&dev->phy, pm);
373 	mutex_unlock(&dev->mutex);
374 }
375 
376 void mt76_connac_gen_ppe_thresh(u8 *he_ppet, int nss);
377 int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
378 			       int ring_base, u32 flags);
379 void mt76_connac_write_hw_txp(struct mt76_dev *dev,
380 			      struct mt76_tx_info *tx_info,
381 			      void *txp_ptr, u32 id);
382 void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,
383 			       struct mt76_txwi_cache *txwi);
384 void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,
385 				 struct mt76_queue_entry *e);
386 void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,
387 			      struct mt76_connac_pm *pm,
388 			      struct mt76_wcid *wcid,
389 			      struct sk_buff *skb);
390 void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,
391 				 struct mt76_connac_pm *pm);
392 void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
393 				 struct sk_buff *skb, struct mt76_wcid *wcid,
394 				 struct ieee80211_key_conf *key, int pid,
395 				 enum mt76_txq_id qid, u32 changed);
396 u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy,
397 				 struct ieee80211_vif *vif,
398 				 bool beacon, bool mcast);
399 bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid,
400 			       __le32 *txs_data);
401 bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,
402 				  int pid, __le32 *txs_data);
403 void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,
404 					 struct sk_buff *skb,
405 					 __le32 *rxv, u32 mode);
406 int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,
407 					 struct sk_buff *skb, u16 hdr_offset);
408 int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,
409 				  struct mt76_rx_status *status,
410 				  struct ieee80211_supported_band *sband,
411 				  __le32 *rxv, u8 *mode);
412 
413 #endif /* __MT76_CONNAC_H */
414