1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_H 5 #define __MT76_CONNAC_H 6 7 #include "mt76.h" 8 9 #define MT76_CONNAC_SCAN_IE_LEN 600 10 #define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL 10 11 #define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX 12 #define MT76_CONNAC_MAX_SCHED_SCAN_SSID 10 13 #define MT76_CONNAC_MAX_SCAN_MATCH 16 14 15 #define MT76_CONNAC_MAX_WMM_SETS 4 16 17 #define MT76_CONNAC_COREDUMP_TIMEOUT (HZ / 20) 18 #define MT76_CONNAC_COREDUMP_SZ (1300 * 1024) 19 20 #define MT_TXD_SIZE (8 * 4) 21 22 #define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 23 #define MT_USB_HDR_SIZE 4 24 #define MT_USB_TAIL_SIZE 4 25 26 #define MT_SDIO_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 27 #define MT_SDIO_TAIL_SIZE 8 28 #define MT_SDIO_HDR_SIZE 4 29 30 #define MT_MSDU_ID_VALID BIT(15) 31 32 #define MT_TXD_LEN_LAST BIT(15) 33 #define MT_TXD_LEN_MASK GENMASK(11, 0) 34 #define MT_TXD_LEN_MSDU_LAST BIT(14) 35 #define MT_TXD_LEN_AMSDU_LAST BIT(15) 36 37 enum { 38 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 39 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 40 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 41 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 42 CMD_CBW_10MHZ, 43 CMD_CBW_5MHZ, 44 CMD_CBW_8080MHZ, 45 CMD_CBW_320MHZ, 46 47 CMD_HE_MCS_BW80 = 0, 48 CMD_HE_MCS_BW160, 49 CMD_HE_MCS_BW8080, 50 CMD_HE_MCS_BW_NUM 51 }; 52 53 enum { 54 HW_BSSID_0 = 0x0, 55 HW_BSSID_1, 56 HW_BSSID_2, 57 HW_BSSID_3, 58 HW_BSSID_MAX = HW_BSSID_3, 59 EXT_BSSID_START = 0x10, 60 EXT_BSSID_1, 61 EXT_BSSID_15 = 0x1f, 62 EXT_BSSID_MAX = EXT_BSSID_15, 63 REPEATER_BSSID_START = 0x20, 64 REPEATER_BSSID_MAX = 0x3f, 65 }; 66 67 struct mt76_connac_reg_map { 68 u32 phys; 69 u32 maps; 70 u32 size; 71 }; 72 73 struct mt76_connac_pm { 74 bool enable:1; 75 bool enable_user:1; 76 bool ds_enable:1; 77 bool ds_enable_user:1; 78 bool suspended:1; 79 80 spinlock_t txq_lock; 81 struct { 82 struct mt76_wcid *wcid; 83 struct sk_buff *skb; 84 } tx_q[IEEE80211_NUM_ACS]; 85 86 struct work_struct wake_work; 87 wait_queue_head_t wait; 88 89 struct { 90 spinlock_t lock; 91 u32 count; 92 } wake; 93 struct mutex mutex; 94 95 struct delayed_work ps_work; 96 unsigned long last_activity; 97 unsigned long idle_timeout; 98 99 struct { 100 unsigned long last_wake_event; 101 unsigned long awake_time; 102 unsigned long last_doze_event; 103 unsigned long doze_time; 104 unsigned int lp_wake; 105 } stats; 106 }; 107 108 struct mt76_connac_coredump { 109 struct sk_buff_head msg_list; 110 struct delayed_work work; 111 unsigned long last_activity; 112 }; 113 114 struct mt76_connac_sta_key_conf { 115 s8 keyidx; 116 u8 key[16]; 117 }; 118 119 #define MT_TXP_MAX_BUF_NUM 6 120 121 struct mt76_connac_fw_txp { 122 __le16 flags; 123 __le16 token; 124 u8 bss_idx; 125 __le16 rept_wds_wcid; 126 u8 nbuf; 127 __le32 buf[MT_TXP_MAX_BUF_NUM]; 128 __le16 len[MT_TXP_MAX_BUF_NUM]; 129 } __packed __aligned(4); 130 131 #define MT_HW_TXP_MAX_MSDU_NUM 4 132 #define MT_HW_TXP_MAX_BUF_NUM 4 133 134 struct mt76_connac_txp_ptr { 135 __le32 buf0; 136 __le16 len0; 137 __le16 len1; 138 __le32 buf1; 139 } __packed __aligned(4); 140 141 struct mt76_connac_hw_txp { 142 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM]; 143 struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2]; 144 } __packed __aligned(4); 145 146 struct mt76_connac_txp_common { 147 union { 148 struct mt76_connac_fw_txp fw; 149 struct mt76_connac_hw_txp hw; 150 }; 151 }; 152 153 struct mt76_connac_tx_free { 154 __le16 rx_byte_cnt; 155 __le16 ctrl; 156 __le32 txd; 157 } __packed __aligned(4); 158 159 extern const struct wiphy_wowlan_support mt76_connac_wowlan_support; 160 161 static inline bool is_mt7922(struct mt76_dev *dev) 162 { 163 return mt76_chip(dev) == 0x7922; 164 } 165 166 static inline bool is_mt7921(struct mt76_dev *dev) 167 { 168 return mt76_chip(dev) == 0x7961 || is_mt7922(dev); 169 } 170 171 static inline bool is_mt7663(struct mt76_dev *dev) 172 { 173 return mt76_chip(dev) == 0x7663; 174 } 175 176 static inline bool is_mt7915(struct mt76_dev *dev) 177 { 178 return mt76_chip(dev) == 0x7915; 179 } 180 181 static inline bool is_mt7916(struct mt76_dev *dev) 182 { 183 return mt76_chip(dev) == 0x7906; 184 } 185 186 static inline bool is_mt7986(struct mt76_dev *dev) 187 { 188 return mt76_chip(dev) == 0x7986; 189 } 190 191 static inline bool is_mt7996(struct mt76_dev *dev) 192 { 193 return mt76_chip(dev) == 0x7990; 194 } 195 196 static inline bool is_mt7622(struct mt76_dev *dev) 197 { 198 if (!IS_ENABLED(CONFIG_MT7622_WMAC)) 199 return false; 200 201 return mt76_chip(dev) == 0x7622; 202 } 203 204 static inline bool is_mt7615(struct mt76_dev *dev) 205 { 206 return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611; 207 } 208 209 static inline bool is_mt7611(struct mt76_dev *dev) 210 { 211 return mt76_chip(dev) == 0x7611; 212 } 213 214 static inline bool is_connac_v1(struct mt76_dev *dev) 215 { 216 return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev); 217 } 218 219 static inline bool is_mt76_fw_txp(struct mt76_dev *dev) 220 { 221 switch (mt76_chip(dev)) { 222 case 0x7961: 223 case 0x7922: 224 case 0x7663: 225 case 0x7622: 226 return false; 227 default: 228 return true; 229 } 230 } 231 232 static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef) 233 { 234 static const u8 width_to_bw[] = { 235 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ, 236 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ, 237 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ, 238 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ, 239 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ, 240 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ, 241 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ, 242 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ, 243 [NL80211_CHAN_WIDTH_320] = CMD_CBW_320MHZ, 244 }; 245 246 if (chandef->width >= ARRAY_SIZE(width_to_bw)) 247 return 0; 248 249 return width_to_bw[chandef->width]; 250 } 251 252 static inline u8 mt76_connac_lmac_mapping(u8 ac) 253 { 254 /* LMAC uses the reverse order of mac80211 AC indexes */ 255 return 3 - ac; 256 } 257 258 static inline void * 259 mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t) 260 { 261 u8 *txwi; 262 263 if (!t) 264 return NULL; 265 266 txwi = mt76_get_txwi_ptr(dev, t); 267 268 return (void *)(txwi + MT_TXD_SIZE); 269 } 270 271 static inline u8 mt76_connac_spe_idx(u8 antenna_mask) 272 { 273 static const u8 ant_to_spe[] = {0, 0, 1, 0, 3, 2, 4, 0, 274 9, 8, 6, 10, 16, 12, 18, 0}; 275 276 if (antenna_mask >= sizeof(ant_to_spe)) 277 return 0; 278 279 return ant_to_spe[antenna_mask]; 280 } 281 282 int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm); 283 void mt76_connac_power_save_sched(struct mt76_phy *phy, 284 struct mt76_connac_pm *pm); 285 void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm, 286 struct mt76_wcid *wcid); 287 288 static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev) 289 { 290 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false); 291 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false); 292 } 293 294 static inline bool 295 mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 296 { 297 bool ret = false; 298 299 spin_lock_bh(&pm->wake.lock); 300 if (test_bit(MT76_STATE_PM, &phy->state)) 301 goto out; 302 303 pm->wake.count++; 304 ret = true; 305 out: 306 spin_unlock_bh(&pm->wake.lock); 307 308 return ret; 309 } 310 311 static inline void 312 mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 313 { 314 spin_lock_bh(&pm->wake.lock); 315 316 pm->last_activity = jiffies; 317 if (--pm->wake.count == 0 && 318 test_bit(MT76_STATE_MCU_RUNNING, &phy->state)) 319 mt76_connac_power_save_sched(phy, pm); 320 321 spin_unlock_bh(&pm->wake.lock); 322 } 323 324 static inline bool 325 mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm) 326 { 327 struct mt76_dev *dev = phy->dev; 328 bool ret; 329 330 if (dev->token_count) 331 return true; 332 333 spin_lock_bh(&pm->wake.lock); 334 ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state); 335 spin_unlock_bh(&pm->wake.lock); 336 337 return ret; 338 } 339 340 static inline void 341 mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm) 342 __acquires(&dev->mutex) 343 { 344 mutex_lock(&dev->mutex); 345 mt76_connac_pm_wake(&dev->phy, pm); 346 } 347 348 static inline void 349 mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm) 350 __releases(&dev->mutex) 351 { 352 mt76_connac_power_save_sched(&dev->phy, pm); 353 mutex_unlock(&dev->mutex); 354 } 355 356 int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc, 357 int ring_base, u32 flags); 358 void mt76_connac_write_hw_txp(struct mt76_dev *dev, 359 struct mt76_tx_info *tx_info, 360 void *txp_ptr, u32 id); 361 void mt76_connac_txp_skb_unmap(struct mt76_dev *dev, 362 struct mt76_txwi_cache *txwi); 363 void mt76_connac_tx_complete_skb(struct mt76_dev *mdev, 364 struct mt76_queue_entry *e); 365 void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw, 366 struct mt76_connac_pm *pm, 367 struct mt76_wcid *wcid, 368 struct sk_buff *skb); 369 void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy, 370 struct mt76_connac_pm *pm); 371 void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 372 struct sk_buff *skb, struct mt76_wcid *wcid, 373 struct ieee80211_key_conf *key, int pid, 374 enum mt76_txq_id qid, u32 changed); 375 u16 mt76_connac2_mac_tx_rate_val(struct mt76_phy *mphy, 376 struct ieee80211_vif *vif, 377 bool beacon, bool mcast); 378 bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid, 379 __le32 *txs_data); 380 bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid, 381 int pid, __le32 *txs_data); 382 void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev, 383 struct sk_buff *skb, 384 __le32 *rxv, u32 mode); 385 int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif, 386 struct sk_buff *skb, u16 hdr_offset); 387 int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev, 388 struct mt76_rx_status *status, 389 struct ieee80211_supported_band *sband, 390 __le32 *rxv, u8 *mode); 391 392 #endif /* __MT76_CONNAC_H */ 393