1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2019 MediaTek Inc. */ 3 4 #ifndef __MT7615_MCU_H 5 #define __MT7615_MCU_H 6 7 struct mt7615_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /** 27 * struct mt7615_uni_txd - mcu command descriptor for firmware v3 28 * @txd: hardware descriptor 29 * @len: total length not including txd 30 * @cid: command identifier 31 * @pkt_type: must be 0xa0 (cmd packet by long format) 32 * @frag_n: fragment number 33 * @seq: sequence number 34 * @checksum: 0 mean there is no checksum 35 * @s2d_index: index for command source and destination 36 * Definition | value | note 37 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 38 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 39 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 40 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 41 * 42 * @option: command option 43 * BIT[0]: UNI_CMD_OPT_BIT_ACK 44 * set to 1 to request a fw reply 45 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 46 * is set, mcu firmware will send response event EID = 0x01 47 * (UNI_EVENT_ID_CMD_RESULT) to the host. 48 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 49 * 0: original command 50 * 1: unified command 51 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 52 * 0: QUERY command 53 * 1: SET command 54 */ 55 struct mt7615_uni_txd { 56 __le32 txd[8]; 57 58 /* DW1 */ 59 __le16 len; 60 __le16 cid; 61 62 /* DW2 */ 63 u8 reserved; 64 u8 pkt_type; 65 u8 frag_n; 66 u8 seq; 67 68 /* DW3 */ 69 __le16 checksum; 70 u8 s2d_index; 71 u8 option; 72 73 /* DW4 */ 74 u8 reserved2[4]; 75 } __packed __aligned(4); 76 77 /* event table */ 78 enum { 79 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 80 MCU_EVENT_FW_START = 0x01, 81 MCU_EVENT_GENERIC = 0x01, 82 MCU_EVENT_ACCESS_REG = 0x02, 83 MCU_EVENT_MT_PATCH_SEM = 0x04, 84 MCU_EVENT_REG_ACCESS = 0x05, 85 MCU_EVENT_SCAN_DONE = 0x0d, 86 MCU_EVENT_ROC = 0x10, 87 MCU_EVENT_BSS_ABSENCE = 0x11, 88 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 89 MCU_EVENT_CH_PRIVILEGE = 0x18, 90 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 91 MCU_EVENT_EXT = 0xed, 92 MCU_EVENT_RESTART_DL = 0xef, 93 }; 94 95 /* ext event table */ 96 enum { 97 MCU_EXT_EVENT_PS_SYNC = 0x5, 98 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 99 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 100 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 101 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 102 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 103 }; 104 105 enum { 106 MT_SKU_CCK_1_2 = 0, 107 MT_SKU_CCK_55_11, 108 MT_SKU_OFDM_6_9, 109 MT_SKU_OFDM_12_18, 110 MT_SKU_OFDM_24_36, 111 MT_SKU_OFDM_48, 112 MT_SKU_OFDM_54, 113 MT_SKU_HT20_0_8, 114 MT_SKU_HT20_32, 115 MT_SKU_HT20_1_2_9_10, 116 MT_SKU_HT20_3_4_11_12, 117 MT_SKU_HT20_5_13, 118 MT_SKU_HT20_6_14, 119 MT_SKU_HT20_7_15, 120 MT_SKU_HT40_0_8, 121 MT_SKU_HT40_32, 122 MT_SKU_HT40_1_2_9_10, 123 MT_SKU_HT40_3_4_11_12, 124 MT_SKU_HT40_5_13, 125 MT_SKU_HT40_6_14, 126 MT_SKU_HT40_7_15, 127 MT_SKU_VHT20_0, 128 MT_SKU_VHT20_1_2, 129 MT_SKU_VHT20_3_4, 130 MT_SKU_VHT20_5_6, 131 MT_SKU_VHT20_7, 132 MT_SKU_VHT20_8, 133 MT_SKU_VHT20_9, 134 MT_SKU_VHT40_0, 135 MT_SKU_VHT40_1_2, 136 MT_SKU_VHT40_3_4, 137 MT_SKU_VHT40_5_6, 138 MT_SKU_VHT40_7, 139 MT_SKU_VHT40_8, 140 MT_SKU_VHT40_9, 141 MT_SKU_VHT80_0, 142 MT_SKU_VHT80_1_2, 143 MT_SKU_VHT80_3_4, 144 MT_SKU_VHT80_5_6, 145 MT_SKU_VHT80_7, 146 MT_SKU_VHT80_8, 147 MT_SKU_VHT80_9, 148 MT_SKU_VHT160_0, 149 MT_SKU_VHT160_1_2, 150 MT_SKU_VHT160_3_4, 151 MT_SKU_VHT160_5_6, 152 MT_SKU_VHT160_7, 153 MT_SKU_VHT160_8, 154 MT_SKU_VHT160_9, 155 MT_SKU_1SS_DELTA, 156 MT_SKU_2SS_DELTA, 157 MT_SKU_3SS_DELTA, 158 MT_SKU_4SS_DELTA, 159 }; 160 161 struct mt7615_mcu_rxd { 162 __le32 rxd[4]; 163 164 __le16 len; 165 __le16 pkt_type_id; 166 167 u8 eid; 168 u8 seq; 169 __le16 __rsv; 170 171 u8 ext_eid; 172 u8 __rsv1[2]; 173 u8 s2d_index; 174 }; 175 176 struct mt7615_mcu_rdd_report { 177 struct mt7615_mcu_rxd rxd; 178 179 u8 idx; 180 u8 long_detected; 181 u8 constant_prf_detected; 182 u8 staggered_prf_detected; 183 u8 radar_type_idx; 184 u8 periodic_pulse_num; 185 u8 long_pulse_num; 186 u8 hw_pulse_num; 187 188 u8 out_lpn; 189 u8 out_spn; 190 u8 out_crpn; 191 u8 out_crpw; 192 u8 out_crbn; 193 u8 out_stgpn; 194 u8 out_stgpw; 195 196 u8 _rsv[2]; 197 198 __le32 out_pri_const; 199 __le32 out_pri_stg[3]; 200 201 struct { 202 __le32 start; 203 __le16 pulse_width; 204 __le16 pulse_power; 205 } long_pulse[32]; 206 207 struct { 208 __le32 start; 209 __le16 pulse_width; 210 __le16 pulse_power; 211 } periodic_pulse[32]; 212 213 struct { 214 __le32 start; 215 __le16 pulse_width; 216 __le16 pulse_power; 217 u8 sc_pass; 218 u8 sw_reset; 219 } hw_pulse[32]; 220 }; 221 222 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 223 #define MCU_PKT_ID 0xa0 224 225 enum { 226 MCU_Q_QUERY, 227 MCU_Q_SET, 228 MCU_Q_RESERVED, 229 MCU_Q_NA 230 }; 231 232 enum { 233 MCU_S2D_H2N, 234 MCU_S2D_C2N, 235 MCU_S2D_H2C, 236 MCU_S2D_H2CN 237 }; 238 239 #define MCU_FW_PREFIX BIT(31) 240 #define MCU_UNI_PREFIX BIT(30) 241 #define MCU_CE_PREFIX BIT(29) 242 #define MCU_QUERY_PREFIX BIT(28) 243 #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \ 244 MCU_CE_PREFIX | MCU_QUERY_PREFIX) 245 246 #define MCU_QUERY_MASK BIT(16) 247 248 enum { 249 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01, 250 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02, 251 MCU_CMD_INIT_ACCESS_REG = 0x3, 252 MCU_CMD_PATCH_START_REQ = 0x05, 253 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07, 254 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10, 255 MCU_CMD_EXT_CID = 0xED, 256 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xEE, 257 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xEF, 258 }; 259 260 enum { 261 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 262 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 263 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 264 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 265 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 266 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 267 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 268 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 269 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 270 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 271 MCU_EXT_CMD_GET_TEMP = 0x2c, 272 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 273 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 274 MCU_EXT_CMD_ATE_CTRL = 0x3d, 275 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 276 MCU_EXT_CMD_DBDC_CTRL = 0x45, 277 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 278 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 279 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 280 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 281 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 282 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 283 MCU_EXT_CMD_TXDPD_CAL = 0x60, 284 MCU_EXT_CMD_SET_RDD_TH = 0x7c, 285 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 286 }; 287 288 enum { 289 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01, 290 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02, 291 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03, 292 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05, 293 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06, 294 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07, 295 }; 296 297 enum { 298 MCU_ATE_SET_FREQ_OFFSET = 0xa, 299 MCU_ATE_SET_TX_POWER_CONTROL = 0x15, 300 }; 301 302 struct mt7615_mcu_uni_event { 303 u8 cid; 304 u8 pad[3]; 305 __le32 status; /* 0: success, others: fail */ 306 } __packed; 307 308 struct mt7615_beacon_loss_event { 309 u8 bss_idx; 310 u8 reason; 311 u8 pad[2]; 312 } __packed; 313 314 struct mt7615_mcu_scan_ssid { 315 __le32 ssid_len; 316 u8 ssid[IEEE80211_MAX_SSID_LEN]; 317 } __packed; 318 319 struct mt7615_mcu_scan_channel { 320 u8 band; /* 1: 2.4GHz 321 * 2: 5.0GHz 322 * Others: Reserved 323 */ 324 u8 channel_num; 325 } __packed; 326 327 struct mt7615_mcu_scan_match { 328 __le32 rssi_th; 329 u8 ssid[IEEE80211_MAX_SSID_LEN]; 330 u8 ssid_len; 331 u8 rsv[3]; 332 } __packed; 333 334 struct mt7615_hw_scan_req { 335 u8 seq_num; 336 u8 bss_idx; 337 u8 scan_type; /* 0: PASSIVE SCAN 338 * 1: ACTIVE SCAN 339 */ 340 u8 ssid_type; /* BIT(0) wildcard SSID 341 * BIT(1) P2P wildcard SSID 342 * BIT(2) specified SSID + wildcard SSID 343 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 344 */ 345 u8 ssids_num; 346 u8 probe_req_num; /* Number of probe request for each SSID */ 347 u8 scan_func; /* BIT(0) Enable random MAC scan 348 * BIT(1) Disable DBDC scan type 1~3. 349 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 350 */ 351 u8 version; /* 0: Not support fields after ies. 352 * 1: Support fields after ies. 353 */ 354 struct mt7615_mcu_scan_ssid ssids[4]; 355 __le16 probe_delay_time; 356 __le16 channel_dwell_time; /* channel Dwell interval */ 357 __le16 timeout_value; 358 u8 channel_type; /* 0: Full channels 359 * 1: Only 2.4GHz channels 360 * 2: Only 5GHz channels 361 * 3: P2P social channel only (channel #1, #6 and #11) 362 * 4: Specified channels 363 * Others: Reserved 364 */ 365 u8 channels_num; /* valid when channel_type is 4 */ 366 /* valid when channels_num is set */ 367 struct mt7615_mcu_scan_channel channels[32]; 368 __le16 ies_len; 369 u8 ies[MT7615_SCAN_IE_LEN]; 370 /* following fields are valid if version > 0 */ 371 u8 ext_channels_num; 372 u8 ext_ssids_num; 373 __le16 channel_min_dwell_time; 374 struct mt7615_mcu_scan_channel ext_channels[32]; 375 struct mt7615_mcu_scan_ssid ext_ssids[6]; 376 u8 bssid[ETH_ALEN]; 377 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 378 u8 pad[63]; 379 u8 ssid_type_ext; 380 } __packed; 381 382 #define SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 383 struct mt7615_hw_scan_done { 384 u8 seq_num; 385 u8 sparse_channel_num; 386 struct mt7615_mcu_scan_channel sparse_channel; 387 u8 complete_channel_num; 388 u8 current_state; 389 u8 version; 390 u8 pad; 391 __le32 beacon_scan_num; 392 u8 pno_enabled; 393 u8 pad2[3]; 394 u8 sparse_channel_valid_num; 395 u8 pad3[3]; 396 u8 channel_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 397 /* idle format for channel_idle_time 398 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 399 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 400 * 2: dwell time (16us) 401 */ 402 __le16 channel_idle_time[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 403 /* beacon and probe response count */ 404 u8 beacon_probe_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 405 u8 mdrdy_count[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 406 __le32 beacon_2g_num; 407 __le32 beacon_5g_num; 408 } __packed; 409 410 struct mt7615_sched_scan_req { 411 u8 version; 412 u8 seq_num; 413 u8 stop_on_match; 414 u8 ssids_num; 415 u8 match_num; 416 u8 pad; 417 __le16 ie_len; 418 struct mt7615_mcu_scan_ssid ssids[MT7615_MAX_SCHED_SCAN_SSID]; 419 struct mt7615_mcu_scan_match match[MT7615_MAX_SCAN_MATCH]; 420 u8 channel_type; 421 u8 channels_num; 422 u8 intervals_num; 423 u8 scan_func; /* BIT(0) eable random mac address */ 424 struct mt7615_mcu_scan_channel channels[64]; 425 __le16 intervals[MT7615_MAX_SCHED_SCAN_INTERVAL]; 426 u8 random_mac[ETH_ALEN]; /* valid when BIT(0) in scan_func is set */ 427 u8 pad2[58]; 428 } __packed; 429 430 struct nt7615_sched_scan_done { 431 u8 seq_num; 432 u8 status; /* 0: ssid found */ 433 __le16 pad; 434 } __packed; 435 436 struct mt7615_mcu_reg_event { 437 __le32 reg; 438 __le32 val; 439 } __packed; 440 441 struct mt7615_mcu_bss_event { 442 u8 bss_idx; 443 u8 is_absent; 444 u8 free_quota; 445 u8 pad; 446 } __packed; 447 448 struct mt7615_bss_basic_tlv { 449 __le16 tag; 450 __le16 len; 451 u8 active; 452 u8 omac_idx; 453 u8 hw_bss_idx; 454 u8 band_idx; 455 __le32 conn_type; 456 u8 conn_state; 457 u8 wmm_idx; 458 u8 bssid[ETH_ALEN]; 459 __le16 bmc_tx_wlan_idx; 460 __le16 bcn_interval; 461 u8 dtim_period; 462 u8 phymode; /* bit(0): A 463 * bit(1): B 464 * bit(2): G 465 * bit(3): GN 466 * bit(4): AN 467 * bit(5): AC 468 */ 469 __le16 sta_idx; 470 u8 nonht_basic_phy; 471 u8 pad[3]; 472 } __packed; 473 474 struct mt7615_bss_qos_tlv { 475 __le16 tag; 476 __le16 len; 477 u8 qos; 478 u8 pad[3]; 479 } __packed; 480 481 enum { 482 WOW_USB = 1, 483 WOW_PCIE = 2, 484 WOW_GPIO = 3, 485 }; 486 487 struct mt7615_wow_ctrl_tlv { 488 __le16 tag; 489 __le16 len; 490 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 491 * 0x2: PM_WOWLAN_REQ_STOP 492 * 0x3: PM_WOWLAN_PARAM_CLEAR 493 */ 494 u8 trigger; /* 0: NONE 495 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 496 * BIT(1): NL80211_WOWLAN_TRIG_ANY 497 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 498 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 499 * BIT(4): BEACON_LOST 500 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 501 */ 502 u8 wakeup_hif; /* 0x0: HIF_SDIO 503 * 0x1: HIF_USB 504 * 0x2: HIF_PCIE 505 * 0x3: HIF_GPIO 506 */ 507 u8 pad; 508 u8 rsv[4]; 509 } __packed; 510 511 struct mt7615_wow_gpio_param_tlv { 512 __le16 tag; 513 __le16 len; 514 u8 gpio_pin; 515 u8 trigger_lvl; 516 u8 pad[2]; 517 __le32 gpio_interval; 518 u8 rsv[4]; 519 } __packed; 520 521 #define MT7615_WOW_MASK_MAX_LEN 16 522 #define MT7615_WOW_PATTEN_MAX_LEN 128 523 struct mt7615_wow_pattern_tlv { 524 __le16 tag; 525 __le16 len; 526 u8 index; /* pattern index */ 527 u8 enable; /* 0: disable 528 * 1: enable 529 */ 530 u8 data_len; /* pattern length */ 531 u8 pad; 532 u8 mask[MT7615_WOW_MASK_MAX_LEN]; 533 u8 pattern[MT7615_WOW_PATTEN_MAX_LEN]; 534 u8 rsv[4]; 535 } __packed; 536 537 struct mt7615_suspend_tlv { 538 __le16 tag; 539 __le16 len; 540 u8 enable; /* 0: suspend mode disabled 541 * 1: suspend mode enabled 542 */ 543 u8 mdtim; /* LP parameter */ 544 u8 wow_suspend; /* 0: update by origin policy 545 * 1: update by wow dtim 546 */ 547 u8 pad[5]; 548 } __packed; 549 550 struct mt7615_gtk_rekey_tlv { 551 __le16 tag; 552 __le16 len; 553 u8 kek[NL80211_KEK_LEN]; 554 u8 kck[NL80211_KCK_LEN]; 555 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 556 u8 rekey_mode; /* 0: rekey offload enable 557 * 1: rekey offload disable 558 * 2: rekey update 559 */ 560 u8 keyid; 561 u8 pad[2]; 562 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 563 __le32 pairwise_cipher; 564 __le32 group_cipher; 565 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 566 __le32 mgmt_group_cipher; 567 u8 option; /* 1: rekey data update without enabling offload */ 568 u8 reserverd[3]; 569 } __packed; 570 571 struct mt7615_roc_tlv { 572 u8 bss_idx; 573 u8 token; 574 u8 active; 575 u8 primary_chan; 576 u8 sco; 577 u8 band; 578 u8 width; /* To support 80/160MHz bandwidth */ 579 u8 freq_seg1; /* To support 80/160MHz bandwidth */ 580 u8 freq_seg2; /* To support 80/160MHz bandwidth */ 581 u8 req_type; 582 u8 dbdc_band; 583 u8 rsv0; 584 __le32 max_interval; /* ms */ 585 u8 rsv1[8]; 586 } __packed; 587 588 struct mt7615_arpns_tlv { 589 __le16 tag; 590 __le16 len; 591 u8 mode; 592 u8 ips_num; 593 u8 option; 594 u8 pad[1]; 595 } __packed; 596 597 /* offload mcu commands */ 598 enum { 599 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03, 600 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05, 601 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f, 602 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16, 603 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17, 604 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b, 605 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1c, 606 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33, 607 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61, 608 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62, 609 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0, 610 MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0, 611 }; 612 613 #define MCU_CMD_ACK BIT(0) 614 #define MCU_CMD_UNI BIT(1) 615 #define MCU_CMD_QUERY BIT(2) 616 617 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | MCU_CMD_QUERY) 618 619 enum { 620 UNI_BSS_INFO_BASIC = 0, 621 UNI_BSS_INFO_RLM = 2, 622 UNI_BSS_INFO_BCN_CONTENT = 7, 623 UNI_BSS_INFO_QBSS = 15, 624 UNI_BSS_INFO_UAPSD = 19, 625 }; 626 627 enum { 628 UNI_SUSPEND_MODE_SETTING, 629 UNI_SUSPEND_WOW_CTRL, 630 UNI_SUSPEND_WOW_GPIO_PARAM, 631 UNI_SUSPEND_WOW_WAKEUP_PORT, 632 UNI_SUSPEND_WOW_PATTERN, 633 }; 634 635 enum { 636 UNI_OFFLOAD_OFFLOAD_ARP, 637 UNI_OFFLOAD_OFFLOAD_ND, 638 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 639 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 640 }; 641 642 enum { 643 PATCH_SEM_RELEASE = 0x0, 644 PATCH_SEM_GET = 0x1 645 }; 646 647 enum { 648 PATCH_NOT_DL_SEM_FAIL = 0x0, 649 PATCH_IS_DL = 0x1, 650 PATCH_NOT_DL_SEM_SUCCESS = 0x2, 651 PATCH_REL_SEM_SUCCESS = 0x3 652 }; 653 654 enum { 655 FW_STATE_INITIAL = 0, 656 FW_STATE_FW_DOWNLOAD = 1, 657 FW_STATE_NORMAL_OPERATION = 2, 658 FW_STATE_NORMAL_TRX = 3, 659 FW_STATE_CR4_RDY = 7 660 }; 661 662 enum { 663 FW_STATE_PWR_ON = 1, 664 FW_STATE_N9_RDY = 2, 665 }; 666 667 #define STA_TYPE_STA BIT(0) 668 #define STA_TYPE_AP BIT(1) 669 #define STA_TYPE_ADHOC BIT(2) 670 #define STA_TYPE_WDS BIT(4) 671 #define STA_TYPE_BC BIT(5) 672 673 #define NETWORK_INFRA BIT(16) 674 #define NETWORK_P2P BIT(17) 675 #define NETWORK_IBSS BIT(18) 676 #define NETWORK_WDS BIT(21) 677 678 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 679 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 680 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 681 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 682 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 683 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 684 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 685 686 #define CONN_STATE_DISCONNECT 0 687 #define CONN_STATE_CONNECT 1 688 #define CONN_STATE_PORT_SECURE 2 689 690 enum { 691 DEV_INFO_ACTIVE, 692 DEV_INFO_MAX_NUM 693 }; 694 695 enum { 696 DBDC_TYPE_WMM, 697 DBDC_TYPE_MGMT, 698 DBDC_TYPE_BSS, 699 DBDC_TYPE_MBSS, 700 DBDC_TYPE_REPEATER, 701 DBDC_TYPE_MU, 702 DBDC_TYPE_BF, 703 DBDC_TYPE_PTA, 704 __DBDC_TYPE_MAX, 705 }; 706 707 struct tlv { 708 __le16 tag; 709 __le16 len; 710 } __packed; 711 712 struct bss_info_omac { 713 __le16 tag; 714 __le16 len; 715 u8 hw_bss_idx; 716 u8 omac_idx; 717 u8 band_idx; 718 u8 rsv0; 719 __le32 conn_type; 720 u32 rsv1; 721 } __packed; 722 723 struct bss_info_basic { 724 __le16 tag; 725 __le16 len; 726 __le32 network_type; 727 u8 active; 728 u8 rsv0; 729 __le16 bcn_interval; 730 u8 bssid[ETH_ALEN]; 731 u8 wmm_idx; 732 u8 dtim_period; 733 u8 bmc_tx_wlan_idx; 734 u8 cipher; /* not used */ 735 u8 phymode; /* not used */ 736 u8 rsv1[5]; 737 } __packed; 738 739 struct bss_info_rf_ch { 740 __le16 tag; 741 __le16 len; 742 u8 pri_ch; 743 u8 central_ch0; 744 u8 central_ch1; 745 u8 bw; 746 } __packed; 747 748 struct bss_info_ext_bss { 749 __le16 tag; 750 __le16 len; 751 __le32 mbss_tsf_offset; /* in unit of us */ 752 u8 rsv[8]; 753 } __packed; 754 755 enum { 756 BSS_INFO_OMAC, 757 BSS_INFO_BASIC, 758 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 759 BSS_INFO_PM, /* sta only */ 760 BSS_INFO_UAPSD, /* sta only */ 761 BSS_INFO_ROAM_DETECTION, /* obsoleted */ 762 BSS_INFO_LQ_RM, /* obsoleted */ 763 BSS_INFO_EXT_BSS, 764 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 765 BSS_INFO_SYNC_MODE, /* obsoleted */ 766 BSS_INFO_RA, 767 BSS_INFO_MAX_NUM 768 }; 769 770 enum { 771 WTBL_RESET_AND_SET = 1, 772 WTBL_SET, 773 WTBL_QUERY, 774 WTBL_RESET_ALL 775 }; 776 777 struct wtbl_req_hdr { 778 u8 wlan_idx; 779 u8 operation; 780 __le16 tlv_num; 781 u8 rsv[4]; 782 } __packed; 783 784 struct wtbl_generic { 785 __le16 tag; 786 __le16 len; 787 u8 peer_addr[ETH_ALEN]; 788 u8 muar_idx; 789 u8 skip_tx; 790 u8 cf_ack; 791 u8 qos; 792 u8 mesh; 793 u8 adm; 794 __le16 partial_aid; 795 u8 baf_en; 796 u8 aad_om; 797 } __packed; 798 799 struct wtbl_rx { 800 __le16 tag; 801 __le16 len; 802 u8 rcid; 803 u8 rca1; 804 u8 rca2; 805 u8 rv; 806 u8 rsv[4]; 807 } __packed; 808 809 struct wtbl_ht { 810 __le16 tag; 811 __le16 len; 812 u8 ht; 813 u8 ldpc; 814 u8 af; 815 u8 mm; 816 u8 rsv[4]; 817 } __packed; 818 819 struct wtbl_vht { 820 __le16 tag; 821 __le16 len; 822 u8 ldpc; 823 u8 dyn_bw; 824 u8 vht; 825 u8 txop_ps; 826 u8 rsv[4]; 827 } __packed; 828 829 struct wtbl_tx_ps { 830 __le16 tag; 831 __le16 len; 832 u8 txps; 833 u8 rsv[3]; 834 } __packed; 835 836 struct wtbl_hdr_trans { 837 __le16 tag; 838 __le16 len; 839 u8 to_ds; 840 u8 from_ds; 841 u8 disable_rx_trans; 842 u8 rsv; 843 } __packed; 844 845 enum { 846 MT_BA_TYPE_INVALID, 847 MT_BA_TYPE_ORIGINATOR, 848 MT_BA_TYPE_RECIPIENT 849 }; 850 851 enum { 852 RST_BA_MAC_TID_MATCH, 853 RST_BA_MAC_MATCH, 854 RST_BA_NO_MATCH 855 }; 856 857 struct wtbl_ba { 858 __le16 tag; 859 __le16 len; 860 /* common */ 861 u8 tid; 862 u8 ba_type; 863 u8 rsv0[2]; 864 /* originator only */ 865 __le16 sn; 866 u8 ba_en; 867 u8 ba_winsize_idx; 868 __le16 ba_winsize; 869 /* recipient only */ 870 u8 peer_addr[ETH_ALEN]; 871 u8 rst_ba_tid; 872 u8 rst_ba_sel; 873 u8 rst_ba_sb; 874 u8 band_idx; 875 u8 rsv1[4]; 876 } __packed; 877 878 struct wtbl_bf { 879 __le16 tag; 880 __le16 len; 881 u8 ibf; 882 u8 ebf; 883 u8 ibf_vht; 884 u8 ebf_vht; 885 u8 gid; 886 u8 pfmu_idx; 887 u8 rsv[2]; 888 } __packed; 889 890 struct wtbl_smps { 891 __le16 tag; 892 __le16 len; 893 u8 smps; 894 u8 rsv[3]; 895 } __packed; 896 897 struct wtbl_pn { 898 __le16 tag; 899 __le16 len; 900 u8 pn[6]; 901 u8 rsv[2]; 902 } __packed; 903 904 struct wtbl_spe { 905 __le16 tag; 906 __le16 len; 907 u8 spe_idx; 908 u8 rsv[3]; 909 } __packed; 910 911 struct wtbl_raw { 912 __le16 tag; 913 __le16 len; 914 u8 wtbl_idx; 915 u8 dw; 916 u8 rsv[2]; 917 __le32 msk; 918 __le32 val; 919 } __packed; 920 921 #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 922 sizeof(struct wtbl_generic) + \ 923 sizeof(struct wtbl_rx) + \ 924 sizeof(struct wtbl_ht) + \ 925 sizeof(struct wtbl_vht) + \ 926 sizeof(struct wtbl_tx_ps) + \ 927 sizeof(struct wtbl_hdr_trans) +\ 928 sizeof(struct wtbl_ba) + \ 929 sizeof(struct wtbl_bf) + \ 930 sizeof(struct wtbl_smps) + \ 931 sizeof(struct wtbl_pn) + \ 932 sizeof(struct wtbl_spe)) 933 934 #define MT7615_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 935 sizeof(struct sta_rec_basic) + \ 936 sizeof(struct sta_rec_ht) + \ 937 sizeof(struct sta_rec_vht) + \ 938 sizeof(struct sta_rec_uapsd) + \ 939 sizeof(struct tlv) + \ 940 MT7615_WTBL_UPDATE_MAX_SIZE) 941 942 #define MT7615_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 943 sizeof(struct wtbl_ba)) 944 945 enum { 946 WTBL_GENERIC, 947 WTBL_RX, 948 WTBL_HT, 949 WTBL_VHT, 950 WTBL_PEER_PS, /* not used */ 951 WTBL_TX_PS, 952 WTBL_HDR_TRANS, 953 WTBL_SEC_KEY, 954 WTBL_BA, 955 WTBL_RDG, /* obsoleted */ 956 WTBL_PROTECT, /* not used */ 957 WTBL_CLEAR, /* not used */ 958 WTBL_BF, 959 WTBL_SMPS, 960 WTBL_RAW_DATA, /* debug only */ 961 WTBL_PN, 962 WTBL_SPE, 963 WTBL_MAX_NUM 964 }; 965 966 struct sta_ntlv_hdr { 967 u8 rsv[2]; 968 __le16 tlv_num; 969 } __packed; 970 971 struct sta_req_hdr { 972 u8 bss_idx; 973 u8 wlan_idx; 974 __le16 tlv_num; 975 u8 is_tlv_append; 976 u8 muar_idx; 977 u8 rsv[2]; 978 } __packed; 979 980 struct sta_rec_state { 981 __le16 tag; 982 __le16 len; 983 u8 state; 984 __le32 flags; 985 u8 vhtop; 986 u8 pad[2]; 987 } __packed; 988 989 struct sta_rec_basic { 990 __le16 tag; 991 __le16 len; 992 __le32 conn_type; 993 u8 conn_state; 994 u8 qos; 995 __le16 aid; 996 u8 peer_addr[ETH_ALEN]; 997 #define EXTRA_INFO_VER BIT(0) 998 #define EXTRA_INFO_NEW BIT(1) 999 __le16 extra_info; 1000 } __packed; 1001 1002 struct sta_rec_ht { 1003 __le16 tag; 1004 __le16 len; 1005 __le16 ht_cap; 1006 u16 rsv; 1007 } __packed; 1008 1009 struct sta_rec_vht { 1010 __le16 tag; 1011 __le16 len; 1012 __le32 vht_cap; 1013 __le16 vht_rx_mcs_map; 1014 __le16 vht_tx_mcs_map; 1015 } __packed; 1016 1017 struct sta_rec_ba { 1018 __le16 tag; 1019 __le16 len; 1020 u8 tid; 1021 u8 ba_type; 1022 u8 amsdu; 1023 u8 ba_en; 1024 __le16 ssn; 1025 __le16 winsize; 1026 } __packed; 1027 1028 struct sta_rec_uapsd { 1029 __le16 tag; 1030 __le16 len; 1031 u8 dac_map; 1032 u8 tac_map; 1033 u8 max_sp; 1034 u8 rsv0; 1035 __le16 listen_interval; 1036 u8 rsv1[2]; 1037 } __packed; 1038 1039 enum { 1040 STA_REC_BASIC, 1041 STA_REC_RA, 1042 STA_REC_RA_CMM_INFO, 1043 STA_REC_RA_UPDATE, 1044 STA_REC_BF, 1045 STA_REC_AMSDU, /* for CR4 */ 1046 STA_REC_BA, 1047 STA_REC_STATE, 1048 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 1049 STA_REC_HT, 1050 STA_REC_VHT, 1051 STA_REC_APPS, 1052 STA_REC_WTBL = 13, 1053 STA_REC_MAX_NUM 1054 }; 1055 1056 enum { 1057 CMD_CBW_20MHZ, 1058 CMD_CBW_40MHZ, 1059 CMD_CBW_80MHZ, 1060 CMD_CBW_160MHZ, 1061 CMD_CBW_10MHZ, 1062 CMD_CBW_5MHZ, 1063 CMD_CBW_8080MHZ 1064 }; 1065 1066 enum { 1067 CH_SWITCH_NORMAL = 0, 1068 CH_SWITCH_SCAN = 3, 1069 CH_SWITCH_MCC = 4, 1070 CH_SWITCH_DFS = 5, 1071 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1072 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1073 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1074 CH_SWITCH_SCAN_BYPASS_DPD = 9 1075 }; 1076 1077 #endif 1078