1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2019 MediaTek Inc. */ 3 4 #ifndef __MT7615_MCU_H 5 #define __MT7615_MCU_H 6 7 struct mt7615_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 struct mt7615_mcu_rxd { 27 __le32 rxd[4]; 28 29 __le16 len; 30 __le16 pkt_type_id; 31 32 u8 eid; 33 u8 seq; 34 __le16 __rsv; 35 36 u8 ext_eid; 37 u8 __rsv1[2]; 38 u8 s2d_index; 39 }; 40 41 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 42 #define MCU_PKT_ID 0xa0 43 44 enum { 45 MCU_Q_QUERY, 46 MCU_Q_SET, 47 MCU_Q_RESERVED, 48 MCU_Q_NA 49 }; 50 51 enum { 52 MCU_S2D_H2N, 53 MCU_S2D_C2N, 54 MCU_S2D_H2C, 55 MCU_S2D_H2CN 56 }; 57 58 enum { 59 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 60 MCU_CMD_FW_START_REQ = 0x02, 61 MCU_CMD_INIT_ACCESS_REG = 0x3, 62 MCU_CMD_PATCH_START_REQ = 0x05, 63 MCU_CMD_PATCH_FINISH_REQ = 0x07, 64 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 65 MCU_CMD_EXT_CID = 0xED, 66 MCU_CMD_FW_SCATTER = 0xEE, 67 MCU_CMD_RESTART_DL_REQ = 0xEF, 68 }; 69 70 enum { 71 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 72 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 73 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 74 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 75 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 76 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 77 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 78 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 79 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 80 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 81 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 82 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 83 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 84 }; 85 86 enum { 87 PATCH_SEM_RELEASE = 0x0, 88 PATCH_SEM_GET = 0x1 89 }; 90 91 enum { 92 PATCH_NOT_DL_SEM_FAIL = 0x0, 93 PATCH_IS_DL = 0x1, 94 PATCH_NOT_DL_SEM_SUCCESS = 0x2, 95 PATCH_REL_SEM_SUCCESS = 0x3 96 }; 97 98 enum { 99 FW_STATE_INITIAL = 0, 100 FW_STATE_FW_DOWNLOAD = 1, 101 FW_STATE_NORMAL_OPERATION = 2, 102 FW_STATE_NORMAL_TRX = 3, 103 FW_STATE_CR4_RDY = 7 104 }; 105 106 #define STA_TYPE_STA BIT(0) 107 #define STA_TYPE_AP BIT(1) 108 #define STA_TYPE_ADHOC BIT(2) 109 #define STA_TYPE_WDS BIT(4) 110 #define STA_TYPE_BC BIT(5) 111 112 #define NETWORK_INFRA BIT(16) 113 #define NETWORK_P2P BIT(17) 114 #define NETWORK_IBSS BIT(18) 115 #define NETWORK_WDS BIT(21) 116 117 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 118 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 119 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 120 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 121 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 122 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 123 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 124 125 #define CONN_STATE_DISCONNECT 0 126 #define CONN_STATE_CONNECT 1 127 #define CONN_STATE_PORT_SECURE 2 128 129 enum { 130 DEV_INFO_ACTIVE, 131 DEV_INFO_MAX_NUM 132 }; 133 134 struct bss_info_omac { 135 __le16 tag; 136 __le16 len; 137 u8 hw_bss_idx; 138 u8 omac_idx; 139 u8 band_idx; 140 u8 rsv0; 141 __le32 conn_type; 142 u32 rsv1; 143 } __packed; 144 145 struct bss_info_basic { 146 __le16 tag; 147 __le16 len; 148 __le32 network_type; 149 u8 active; 150 u8 rsv0; 151 __le16 bcn_interval; 152 u8 bssid[ETH_ALEN]; 153 u8 wmm_idx; 154 u8 dtim_period; 155 u8 bmc_tx_wlan_idx; 156 u8 cipher; /* not used */ 157 u8 phymode; /* not used */ 158 u8 rsv1[5]; 159 } __packed; 160 161 struct bss_info_rf_ch { 162 __le16 tag; 163 __le16 len; 164 u8 pri_ch; 165 u8 central_ch0; 166 u8 central_ch1; 167 u8 bw; 168 } __packed; 169 170 struct bss_info_ext_bss { 171 __le16 tag; 172 __le16 len; 173 __le32 mbss_tsf_offset; /* in unit of us */ 174 u8 rsv[8]; 175 } __packed; 176 177 enum { 178 BSS_INFO_OMAC, 179 BSS_INFO_BASIC, 180 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 181 BSS_INFO_PM, /* sta only */ 182 BSS_INFO_UAPSD, /* sta only */ 183 BSS_INFO_ROAM_DETECTION, /* obsoleted */ 184 BSS_INFO_LQ_RM, /* obsoleted */ 185 BSS_INFO_EXT_BSS, 186 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 187 BSS_INFO_SYNC_MODE, /* obsoleted */ 188 BSS_INFO_RA, 189 BSS_INFO_MAX_NUM 190 }; 191 192 enum { 193 WTBL_RESET_AND_SET = 1, 194 WTBL_SET, 195 WTBL_QUERY, 196 WTBL_RESET_ALL 197 }; 198 199 struct wtbl_req_hdr { 200 u8 wlan_idx; 201 u8 operation; 202 __le16 tlv_num; 203 u8 rsv[4]; 204 } __packed; 205 206 struct wtbl_generic { 207 __le16 tag; 208 __le16 len; 209 u8 peer_addr[ETH_ALEN]; 210 u8 muar_idx; 211 u8 skip_tx; 212 u8 cf_ack; 213 u8 qos; 214 u8 mesh; 215 u8 adm; 216 __le16 partial_aid; 217 u8 baf_en; 218 u8 aad_om; 219 } __packed; 220 221 struct wtbl_rx { 222 __le16 tag; 223 __le16 len; 224 u8 rcid; 225 u8 rca1; 226 u8 rca2; 227 u8 rv; 228 u8 rsv[4]; 229 } __packed; 230 231 struct wtbl_ht { 232 __le16 tag; 233 __le16 len; 234 u8 ht; 235 u8 ldpc; 236 u8 af; 237 u8 mm; 238 u8 rsv[4]; 239 } __packed; 240 241 struct wtbl_vht { 242 __le16 tag; 243 __le16 len; 244 u8 ldpc; 245 u8 dyn_bw; 246 u8 vht; 247 u8 txop_ps; 248 u8 rsv[4]; 249 } __packed; 250 251 struct wtbl_tx_ps { 252 __le16 tag; 253 __le16 len; 254 u8 txps; 255 u8 rsv[3]; 256 } __packed; 257 258 struct wtbl_hdr_trans { 259 __le16 tag; 260 __le16 len; 261 u8 to_ds; 262 u8 from_ds; 263 u8 disable_rx_trans; 264 u8 rsv; 265 } __packed; 266 267 enum mt7615_cipher_type { 268 MT_CIPHER_NONE, 269 MT_CIPHER_WEP40, 270 MT_CIPHER_TKIP, 271 MT_CIPHER_TKIP_NO_MIC, 272 MT_CIPHER_AES_CCMP, 273 MT_CIPHER_WEP104, 274 MT_CIPHER_BIP_CMAC_128, 275 MT_CIPHER_WEP128, 276 MT_CIPHER_WAPI, 277 MT_CIPHER_CCMP_256 = 10, 278 MT_CIPHER_GCMP, 279 MT_CIPHER_GCMP_256, 280 }; 281 282 struct wtbl_sec_key { 283 __le16 tag; 284 __le16 len; 285 u8 add; /* 0: add, 1: remove */ 286 u8 rkv; 287 u8 ikv; 288 u8 cipher_id; 289 u8 key_id; 290 u8 key_len; 291 u8 rsv[2]; 292 u8 key_material[32]; 293 } __packed; 294 295 enum { 296 MT_BA_TYPE_INVALID, 297 MT_BA_TYPE_ORIGINATOR, 298 MT_BA_TYPE_RECIPIENT 299 }; 300 301 enum { 302 RST_BA_MAC_TID_MATCH, 303 RST_BA_MAC_MATCH, 304 RST_BA_NO_MATCH 305 }; 306 307 struct wtbl_ba { 308 __le16 tag; 309 __le16 len; 310 /* common */ 311 u8 tid; 312 u8 ba_type; 313 u8 rsv0[2]; 314 /* originator only */ 315 __le16 sn; 316 u8 ba_en; 317 u8 ba_winsize_idx; 318 __le16 ba_winsize; 319 /* recipient only */ 320 u8 peer_addr[ETH_ALEN]; 321 u8 rst_ba_tid; 322 u8 rst_ba_sel; 323 u8 rst_ba_sb; 324 u8 band_idx; 325 u8 rsv1[4]; 326 } __packed; 327 328 struct wtbl_bf { 329 __le16 tag; 330 __le16 len; 331 u8 ibf; 332 u8 ebf; 333 u8 ibf_vht; 334 u8 ebf_vht; 335 u8 gid; 336 u8 pfmu_idx; 337 u8 rsv[2]; 338 } __packed; 339 340 struct wtbl_smps { 341 __le16 tag; 342 __le16 len; 343 u8 smps; 344 u8 rsv[3]; 345 } __packed; 346 347 struct wtbl_pn { 348 __le16 tag; 349 __le16 len; 350 u8 pn[6]; 351 u8 rsv[2]; 352 } __packed; 353 354 struct wtbl_spe { 355 __le16 tag; 356 __le16 len; 357 u8 spe_idx; 358 u8 rsv[3]; 359 } __packed; 360 361 struct wtbl_raw { 362 __le16 tag; 363 __le16 len; 364 u8 wtbl_idx; 365 u8 dw; 366 u8 rsv[2]; 367 __le32 msk; 368 __le32 val; 369 } __packed; 370 371 #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 372 sizeof(struct wtbl_generic) + \ 373 sizeof(struct wtbl_rx) + \ 374 sizeof(struct wtbl_ht) + \ 375 sizeof(struct wtbl_vht) + \ 376 sizeof(struct wtbl_tx_ps) + \ 377 sizeof(struct wtbl_hdr_trans) + \ 378 sizeof(struct wtbl_sec_key) + \ 379 sizeof(struct wtbl_ba) + \ 380 sizeof(struct wtbl_bf) + \ 381 sizeof(struct wtbl_smps) + \ 382 sizeof(struct wtbl_pn) + \ 383 sizeof(struct wtbl_spe)) 384 385 enum { 386 WTBL_GENERIC, 387 WTBL_RX, 388 WTBL_HT, 389 WTBL_VHT, 390 WTBL_PEER_PS, /* not used */ 391 WTBL_TX_PS, 392 WTBL_HDR_TRANS, 393 WTBL_SEC_KEY, 394 WTBL_BA, 395 WTBL_RDG, /* obsoleted */ 396 WTBL_PROTECT, /* not used */ 397 WTBL_CLEAR, /* not used */ 398 WTBL_BF, 399 WTBL_SMPS, 400 WTBL_RAW_DATA, /* debug only */ 401 WTBL_PN, 402 WTBL_SPE, 403 WTBL_MAX_NUM 404 }; 405 406 struct sta_req_hdr { 407 u8 bss_idx; 408 u8 wlan_idx; 409 __le16 tlv_num; 410 u8 is_tlv_append; 411 u8 muar_idx; 412 u8 rsv[2]; 413 } __packed; 414 415 struct sta_rec_basic { 416 __le16 tag; 417 __le16 len; 418 __le32 conn_type; 419 u8 conn_state; 420 u8 qos; 421 __le16 aid; 422 u8 peer_addr[ETH_ALEN]; 423 #define EXTRA_INFO_VER BIT(0) 424 #define EXTRA_INFO_NEW BIT(1) 425 __le16 extra_info; 426 } __packed; 427 428 struct sta_rec_ht { 429 __le16 tag; 430 __le16 len; 431 __le16 ht_cap; 432 u16 rsv; 433 } __packed; 434 435 struct sta_rec_vht { 436 __le16 tag; 437 __le16 len; 438 __le32 vht_cap; 439 __le16 vht_rx_mcs_map; 440 __le16 vht_tx_mcs_map; 441 } __packed; 442 443 struct sta_rec_ba { 444 __le16 tag; 445 __le16 len; 446 u8 tid; 447 u8 ba_type; 448 u8 amsdu; 449 u8 ba_en; 450 __le16 ssn; 451 __le16 winsize; 452 } __packed; 453 454 #define MT7615_STA_REC_UPDATE_MAX_SIZE (sizeof(struct sta_rec_basic) + \ 455 sizeof(struct sta_rec_ht) + \ 456 sizeof(struct sta_rec_vht)) 457 458 enum { 459 STA_REC_BASIC, 460 STA_REC_RA, 461 STA_REC_RA_CMM_INFO, 462 STA_REC_RA_UPDATE, 463 STA_REC_BF, 464 STA_REC_AMSDU, /* for CR4 */ 465 STA_REC_BA, 466 STA_REC_RED, /* not used */ 467 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 468 STA_REC_HT, 469 STA_REC_VHT, 470 STA_REC_APPS, 471 STA_REC_MAX_NUM 472 }; 473 474 enum { 475 CMD_CBW_20MHZ, 476 CMD_CBW_40MHZ, 477 CMD_CBW_80MHZ, 478 CMD_CBW_160MHZ, 479 CMD_CBW_10MHZ, 480 CMD_CBW_5MHZ, 481 CMD_CBW_8080MHZ 482 }; 483 484 enum { 485 CH_SWITCH_NORMAL = 0, 486 CH_SWITCH_SCAN = 3, 487 CH_SWITCH_MCC = 4, 488 CH_SWITCH_DFS = 5, 489 CH_SWITCH_BACKGROUND_SCAN_START = 6, 490 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 491 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 492 CH_SWITCH_SCAN_BYPASS_DPD = 9 493 }; 494 495 static inline struct sk_buff * 496 mt7615_mcu_msg_alloc(const void *data, int len) 497 { 498 return mt76_mcu_msg_alloc(data, sizeof(struct mt7615_mcu_txd), 499 len, 0); 500 } 501 502 #endif 503