1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2019 MediaTek Inc. */ 3 4 #ifndef __MT7615_MCU_H 5 #define __MT7615_MCU_H 6 7 #include "../mt76_connac_mcu.h" 8 9 struct mt7615_mcu_txd { 10 __le32 txd[8]; 11 12 __le16 len; 13 __le16 pq_id; 14 15 u8 cid; 16 u8 pkt_type; 17 u8 set_query; /* FW don't care */ 18 u8 seq; 19 20 u8 uc_d2b0_rev; 21 u8 ext_cid; 22 u8 s2d_index; 23 u8 ext_cid_ack; 24 25 u32 reserved[5]; 26 } __packed __aligned(4); 27 28 /** 29 * struct mt7615_uni_txd - mcu command descriptor for firmware v3 30 * @txd: hardware descriptor 31 * @len: total length not including txd 32 * @cid: command identifier 33 * @pkt_type: must be 0xa0 (cmd packet by long format) 34 * @frag_n: fragment number 35 * @seq: sequence number 36 * @checksum: 0 mean there is no checksum 37 * @s2d_index: index for command source and destination 38 * Definition | value | note 39 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 40 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 41 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 42 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 43 * 44 * @option: command option 45 * BIT[0]: UNI_CMD_OPT_BIT_ACK 46 * set to 1 to request a fw reply 47 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 48 * is set, mcu firmware will send response event EID = 0x01 49 * (UNI_EVENT_ID_CMD_RESULT) to the host. 50 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 51 * 0: original command 52 * 1: unified command 53 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 54 * 0: QUERY command 55 * 1: SET command 56 */ 57 struct mt7615_uni_txd { 58 __le32 txd[8]; 59 60 /* DW1 */ 61 __le16 len; 62 __le16 cid; 63 64 /* DW2 */ 65 u8 reserved; 66 u8 pkt_type; 67 u8 frag_n; 68 u8 seq; 69 70 /* DW3 */ 71 __le16 checksum; 72 u8 s2d_index; 73 u8 option; 74 75 /* DW4 */ 76 u8 reserved2[4]; 77 } __packed __aligned(4); 78 79 /* event table */ 80 enum { 81 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 82 MCU_EVENT_FW_START = 0x01, 83 MCU_EVENT_GENERIC = 0x01, 84 MCU_EVENT_ACCESS_REG = 0x02, 85 MCU_EVENT_MT_PATCH_SEM = 0x04, 86 MCU_EVENT_REG_ACCESS = 0x05, 87 MCU_EVENT_SCAN_DONE = 0x0d, 88 MCU_EVENT_ROC = 0x10, 89 MCU_EVENT_BSS_ABSENCE = 0x11, 90 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 91 MCU_EVENT_CH_PRIVILEGE = 0x18, 92 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 93 MCU_EVENT_EXT = 0xed, 94 MCU_EVENT_RESTART_DL = 0xef, 95 MCU_EVENT_COREDUMP = 0xf0, 96 }; 97 98 /* ext event table */ 99 enum { 100 MCU_EXT_EVENT_PS_SYNC = 0x5, 101 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 102 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 103 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 104 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 105 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 106 }; 107 108 enum { 109 MT_SKU_CCK_1_2 = 0, 110 MT_SKU_CCK_55_11, 111 MT_SKU_OFDM_6_9, 112 MT_SKU_OFDM_12_18, 113 MT_SKU_OFDM_24_36, 114 MT_SKU_OFDM_48, 115 MT_SKU_OFDM_54, 116 MT_SKU_HT20_0_8, 117 MT_SKU_HT20_32, 118 MT_SKU_HT20_1_2_9_10, 119 MT_SKU_HT20_3_4_11_12, 120 MT_SKU_HT20_5_13, 121 MT_SKU_HT20_6_14, 122 MT_SKU_HT20_7_15, 123 MT_SKU_HT40_0_8, 124 MT_SKU_HT40_32, 125 MT_SKU_HT40_1_2_9_10, 126 MT_SKU_HT40_3_4_11_12, 127 MT_SKU_HT40_5_13, 128 MT_SKU_HT40_6_14, 129 MT_SKU_HT40_7_15, 130 MT_SKU_VHT20_0, 131 MT_SKU_VHT20_1_2, 132 MT_SKU_VHT20_3_4, 133 MT_SKU_VHT20_5_6, 134 MT_SKU_VHT20_7, 135 MT_SKU_VHT20_8, 136 MT_SKU_VHT20_9, 137 MT_SKU_VHT40_0, 138 MT_SKU_VHT40_1_2, 139 MT_SKU_VHT40_3_4, 140 MT_SKU_VHT40_5_6, 141 MT_SKU_VHT40_7, 142 MT_SKU_VHT40_8, 143 MT_SKU_VHT40_9, 144 MT_SKU_VHT80_0, 145 MT_SKU_VHT80_1_2, 146 MT_SKU_VHT80_3_4, 147 MT_SKU_VHT80_5_6, 148 MT_SKU_VHT80_7, 149 MT_SKU_VHT80_8, 150 MT_SKU_VHT80_9, 151 MT_SKU_VHT160_0, 152 MT_SKU_VHT160_1_2, 153 MT_SKU_VHT160_3_4, 154 MT_SKU_VHT160_5_6, 155 MT_SKU_VHT160_7, 156 MT_SKU_VHT160_8, 157 MT_SKU_VHT160_9, 158 MT_SKU_1SS_DELTA, 159 MT_SKU_2SS_DELTA, 160 MT_SKU_3SS_DELTA, 161 MT_SKU_4SS_DELTA, 162 }; 163 164 struct mt7615_mcu_rxd { 165 __le32 rxd[4]; 166 167 __le16 len; 168 __le16 pkt_type_id; 169 170 u8 eid; 171 u8 seq; 172 __le16 __rsv; 173 174 u8 ext_eid; 175 u8 __rsv1[2]; 176 u8 s2d_index; 177 }; 178 179 struct mt7615_mcu_rdd_report { 180 struct mt7615_mcu_rxd rxd; 181 182 u8 idx; 183 u8 long_detected; 184 u8 constant_prf_detected; 185 u8 staggered_prf_detected; 186 u8 radar_type_idx; 187 u8 periodic_pulse_num; 188 u8 long_pulse_num; 189 u8 hw_pulse_num; 190 191 u8 out_lpn; 192 u8 out_spn; 193 u8 out_crpn; 194 u8 out_crpw; 195 u8 out_crbn; 196 u8 out_stgpn; 197 u8 out_stgpw; 198 199 u8 _rsv[2]; 200 201 __le32 out_pri_const; 202 __le32 out_pri_stg[3]; 203 204 struct { 205 __le32 start; 206 __le16 pulse_width; 207 __le16 pulse_power; 208 } long_pulse[32]; 209 210 struct { 211 __le32 start; 212 __le16 pulse_width; 213 __le16 pulse_power; 214 } periodic_pulse[32]; 215 216 struct { 217 __le32 start; 218 __le16 pulse_width; 219 __le16 pulse_power; 220 u8 sc_pass; 221 u8 sw_reset; 222 } hw_pulse[32]; 223 }; 224 225 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 226 #define MCU_PKT_ID 0xa0 227 228 enum { 229 MCU_Q_QUERY, 230 MCU_Q_SET, 231 MCU_Q_RESERVED, 232 MCU_Q_NA 233 }; 234 235 enum { 236 MCU_S2D_H2N, 237 MCU_S2D_C2N, 238 MCU_S2D_H2C, 239 MCU_S2D_H2CN 240 }; 241 242 enum { 243 MCU_ATE_SET_FREQ_OFFSET = 0xa, 244 MCU_ATE_SET_TX_POWER_CONTROL = 0x15, 245 }; 246 247 struct mt7615_mcu_uni_event { 248 u8 cid; 249 u8 pad[3]; 250 __le32 status; /* 0: success, others: fail */ 251 } __packed; 252 253 struct mt7615_mcu_reg_event { 254 __le32 reg; 255 __le32 val; 256 } __packed; 257 258 struct mt7615_roc_tlv { 259 u8 bss_idx; 260 u8 token; 261 u8 active; 262 u8 primary_chan; 263 u8 sco; 264 u8 band; 265 u8 width; /* To support 80/160MHz bandwidth */ 266 u8 freq_seg1; /* To support 80/160MHz bandwidth */ 267 u8 freq_seg2; /* To support 80/160MHz bandwidth */ 268 u8 req_type; 269 u8 dbdc_band; 270 u8 rsv0; 271 __le32 max_interval; /* ms */ 272 u8 rsv1[8]; 273 } __packed; 274 275 enum { 276 PATCH_NOT_DL_SEM_FAIL = 0x0, 277 PATCH_IS_DL = 0x1, 278 PATCH_NOT_DL_SEM_SUCCESS = 0x2, 279 PATCH_REL_SEM_SUCCESS = 0x3 280 }; 281 282 enum { 283 FW_STATE_INITIAL = 0, 284 FW_STATE_FW_DOWNLOAD = 1, 285 FW_STATE_NORMAL_OPERATION = 2, 286 FW_STATE_NORMAL_TRX = 3, 287 FW_STATE_CR4_RDY = 7 288 }; 289 290 enum { 291 FW_STATE_PWR_ON = 1, 292 FW_STATE_N9_RDY = 2, 293 }; 294 295 enum { 296 DBDC_TYPE_WMM, 297 DBDC_TYPE_MGMT, 298 DBDC_TYPE_BSS, 299 DBDC_TYPE_MBSS, 300 DBDC_TYPE_REPEATER, 301 DBDC_TYPE_MU, 302 DBDC_TYPE_BF, 303 DBDC_TYPE_PTA, 304 __DBDC_TYPE_MAX, 305 }; 306 307 struct bss_info_omac { 308 __le16 tag; 309 __le16 len; 310 u8 hw_bss_idx; 311 u8 omac_idx; 312 u8 band_idx; 313 u8 rsv0; 314 __le32 conn_type; 315 u32 rsv1; 316 } __packed; 317 318 struct bss_info_basic { 319 __le16 tag; 320 __le16 len; 321 __le32 network_type; 322 u8 active; 323 u8 rsv0; 324 __le16 bcn_interval; 325 u8 bssid[ETH_ALEN]; 326 u8 wmm_idx; 327 u8 dtim_period; 328 u8 bmc_tx_wlan_idx; 329 u8 cipher; /* not used */ 330 u8 phymode; /* not used */ 331 u8 rsv1[5]; 332 } __packed; 333 334 struct bss_info_rf_ch { 335 __le16 tag; 336 __le16 len; 337 u8 pri_ch; 338 u8 central_ch0; 339 u8 central_ch1; 340 u8 bw; 341 } __packed; 342 343 struct bss_info_ext_bss { 344 __le16 tag; 345 __le16 len; 346 __le32 mbss_tsf_offset; /* in unit of us */ 347 u8 rsv[8]; 348 } __packed; 349 350 enum { 351 BSS_INFO_OMAC, 352 BSS_INFO_BASIC, 353 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 354 BSS_INFO_PM, /* sta only */ 355 BSS_INFO_UAPSD, /* sta only */ 356 BSS_INFO_ROAM_DETECTION, /* obsoleted */ 357 BSS_INFO_LQ_RM, /* obsoleted */ 358 BSS_INFO_EXT_BSS, 359 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 360 BSS_INFO_SYNC_MODE, /* obsoleted */ 361 BSS_INFO_RA, 362 BSS_INFO_MAX_NUM 363 }; 364 365 #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 366 sizeof(struct wtbl_generic) + \ 367 sizeof(struct wtbl_rx) + \ 368 sizeof(struct wtbl_ht) + \ 369 sizeof(struct wtbl_vht) + \ 370 sizeof(struct wtbl_tx_ps) + \ 371 sizeof(struct wtbl_hdr_trans) +\ 372 sizeof(struct wtbl_ba) + \ 373 sizeof(struct wtbl_bf) + \ 374 sizeof(struct wtbl_smps) + \ 375 sizeof(struct wtbl_pn) + \ 376 sizeof(struct wtbl_spe)) 377 378 #define MT7615_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 379 sizeof(struct sta_rec_basic) + \ 380 sizeof(struct sta_rec_ht) + \ 381 sizeof(struct sta_rec_vht) + \ 382 sizeof(struct sta_rec_uapsd) + \ 383 sizeof(struct tlv) + \ 384 MT7615_WTBL_UPDATE_MAX_SIZE) 385 386 #define MT7615_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 387 sizeof(struct wtbl_ba)) 388 389 enum { 390 CH_SWITCH_NORMAL = 0, 391 CH_SWITCH_SCAN = 3, 392 CH_SWITCH_MCC = 4, 393 CH_SWITCH_DFS = 5, 394 CH_SWITCH_BACKGROUND_SCAN_START = 6, 395 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 396 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 397 CH_SWITCH_SCAN_BYPASS_DPD = 9 398 }; 399 400 #endif 401