1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2019 MediaTek Inc. */
3 
4 #ifndef __MT7615_MAC_H
5 #define __MT7615_MAC_H
6 
7 #define MT_CT_PARSE_LEN			72
8 #define MT_CT_DMA_BUF_NUM		2
9 
10 #define MT_RXD0_LENGTH			GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG                GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE		GENMASK(31, 29)
13 
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM		BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM	BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1		BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2		BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3		BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4		BIT(28)
21 
22 enum rx_pkt_type {
23 	PKT_TYPE_TXS,
24 	PKT_TYPE_TXRXV,
25 	PKT_TYPE_NORMAL,
26 	PKT_TYPE_RX_DUP_RFB,
27 	PKT_TYPE_RX_TMR,
28 	PKT_TYPE_RETRIEVE,
29 	PKT_TYPE_TXRX_NOTIFY,
30 	PKT_TYPE_RX_EVENT,
31 	PKT_TYPE_NORMAL_MCU,
32 };
33 
34 #define MT_RXD1_NORMAL_BSSID		GENMASK(31, 26)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT	GENMASK(25, 24)
36 #define MT_RXD1_FIRST_AMSDU_FRAME	GENMASK(1, 0)
37 #define MT_RXD1_MID_AMSDU_FRAME		BIT(1)
38 #define MT_RXD1_LAST_AMSDU_FRAME	BIT(0)
39 #define MT_RXD1_NORMAL_HDR_TRANS	BIT(23)
40 #define MT_RXD1_NORMAL_HDR_OFFSET	BIT(22)
41 #define MT_RXD1_NORMAL_MAC_HDR_LEN	GENMASK(21, 16)
42 #define MT_RXD1_NORMAL_CH_FREQ		GENMASK(15, 8)
43 #define MT_RXD1_NORMAL_KEY_ID		GENMASK(7, 6)
44 #define MT_RXD1_NORMAL_BEACON_UC	BIT(5)
45 #define MT_RXD1_NORMAL_BEACON_MC	BIT(4)
46 #define MT_RXD1_NORMAL_BF_REPORT	BIT(3)
47 #define MT_RXD1_NORMAL_ADDR_TYPE	GENMASK(2, 1)
48 #define MT_RXD1_NORMAL_BCAST		GENMASK(2, 1)
49 #define MT_RXD1_NORMAL_MCAST		BIT(2)
50 #define MT_RXD1_NORMAL_U2M		BIT(1)
51 #define MT_RXD1_NORMAL_HTC_VLD		BIT(0)
52 
53 #define MT_RXD2_NORMAL_NON_AMPDU	BIT(31)
54 #define MT_RXD2_NORMAL_NON_AMPDU_SUB	BIT(30)
55 #define MT_RXD2_NORMAL_NDATA		BIT(29)
56 #define MT_RXD2_NORMAL_NULL_FRAME	BIT(28)
57 #define MT_RXD2_NORMAL_FRAG		BIT(27)
58 #define MT_RXD2_NORMAL_INT_FRAME	BIT(26)
59 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR	BIT(25)
60 #define MT_RXD2_NORMAL_MAX_LEN_ERROR	BIT(24)
61 #define MT_RXD2_NORMAL_AMSDU_ERR	BIT(23)
62 #define MT_RXD2_NORMAL_LEN_MISMATCH	BIT(22)
63 #define MT_RXD2_NORMAL_TKIP_MIC_ERR	BIT(21)
64 #define MT_RXD2_NORMAL_ICV_ERR		BIT(20)
65 #define MT_RXD2_NORMAL_CLM		BIT(19)
66 #define MT_RXD2_NORMAL_CM		BIT(18)
67 #define MT_RXD2_NORMAL_FCS_ERR		BIT(17)
68 #define MT_RXD2_NORMAL_SW_BIT		BIT(16)
69 #define MT_RXD2_NORMAL_SEC_MODE		GENMASK(15, 12)
70 #define MT_RXD2_NORMAL_TID		GENMASK(11, 8)
71 #define MT_RXD2_NORMAL_WLAN_IDX		GENMASK(7, 0)
72 
73 #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
74 #define MT_RXD3_NORMAL_PF_MODE		BIT(29)
75 #define MT_RXD3_NORMAL_CLS_BITMAP	GENMASK(28, 19)
76 #define MT_RXD3_NORMAL_WOL		GENMASK(18, 14)
77 #define MT_RXD3_NORMAL_MAGIC_PKT	BIT(13)
78 #define MT_RXD3_NORMAL_OFLD		GENMASK(12, 11)
79 #define MT_RXD3_NORMAL_CLS		BIT(10)
80 #define MT_RXD3_NORMAL_PATTERN_DROP	BIT(9)
81 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS	BIT(8)
82 #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
83 
84 #define MT_RXD4_FRAME_CONTROL		GENMASK(15, 0)
85 
86 #define MT_RXD6_SEQ_CTRL		GENMASK(15, 0)
87 #define MT_RXD6_QOS_CTL			GENMASK(31, 16)
88 
89 #define MT_RXD7_HT_CONTROL		GENMASK(31, 0)
90 
91 #define MT_RXV1_ACID_DET_H		BIT(31)
92 #define MT_RXV1_ACID_DET_L		BIT(30)
93 #define MT_RXV1_VHTA2_B8_B3		GENMASK(29, 24)
94 #define MT_RXV1_NUM_RX			GENMASK(23, 22)
95 #define MT_RXV1_HT_NO_SOUND		BIT(21)
96 #define MT_RXV1_HT_SMOOTH		BIT(20)
97 #define MT_RXV1_HT_SHORT_GI		BIT(19)
98 #define MT_RXV1_HT_AGGR			BIT(18)
99 #define MT_RXV1_VHTA1_B22		BIT(17)
100 #define MT_RXV1_FRAME_MODE		GENMASK(16, 15)
101 #define MT_RXV1_TX_MODE			GENMASK(14, 12)
102 #define MT_RXV1_HT_EXT_LTF		GENMASK(11, 10)
103 #define MT_RXV1_HT_AD_CODE		BIT(9)
104 #define MT_RXV1_HT_STBC			GENMASK(8, 7)
105 #define MT_RXV1_TX_RATE			GENMASK(6, 0)
106 
107 #define MT_RXV2_SEL_ANT			BIT(31)
108 #define MT_RXV2_VALID_BIT		BIT(30)
109 #define MT_RXV2_NSTS			GENMASK(29, 27)
110 #define MT_RXV2_GROUP_ID		GENMASK(26, 21)
111 #define MT_RXV2_LENGTH			GENMASK(20, 0)
112 
113 #define MT_RXV3_WB_RSSI			GENMASK(31, 24)
114 #define MT_RXV3_IB_RSSI			GENMASK(23, 16)
115 
116 #define MT_RXV4_RCPI3			GENMASK(31, 24)
117 #define MT_RXV4_RCPI2			GENMASK(23, 16)
118 #define MT_RXV4_RCPI1			GENMASK(15, 8)
119 #define MT_RXV4_RCPI0			GENMASK(7, 0)
120 
121 #define MT_RXV5_FOE			GENMASK(11, 0)
122 
123 #define MT_RXV6_NF3			GENMASK(31, 24)
124 #define MT_RXV6_NF2			GENMASK(23, 16)
125 #define MT_RXV6_NF1			GENMASK(15, 8)
126 #define MT_RXV6_NF0			GENMASK(7, 0)
127 
128 enum tx_header_format {
129 	MT_HDR_FORMAT_802_3,
130 	MT_HDR_FORMAT_CMD,
131 	MT_HDR_FORMAT_802_11,
132 	MT_HDR_FORMAT_802_11_EXT,
133 };
134 
135 enum tx_pkt_type {
136 	MT_TX_TYPE_CT,
137 	MT_TX_TYPE_SF,
138 	MT_TX_TYPE_CMD,
139 	MT_TX_TYPE_FW,
140 };
141 
142 enum tx_port_idx {
143 	MT_TX_PORT_IDX_LMAC,
144 	MT_TX_PORT_IDX_MCU
145 };
146 
147 enum tx_mcu_port_q_idx {
148 	MT_TX_MCU_PORT_RX_Q0 = 0,
149 	MT_TX_MCU_PORT_RX_Q1,
150 	MT_TX_MCU_PORT_RX_Q2,
151 	MT_TX_MCU_PORT_RX_Q3,
152 	MT_TX_MCU_PORT_RX_FWDL = 0x1e
153 };
154 
155 enum tx_phy_bandwidth {
156 	MT_PHY_BW_20,
157 	MT_PHY_BW_40,
158 	MT_PHY_BW_80,
159 	MT_PHY_BW_160,
160 };
161 
162 #define MT_CT_INFO_APPLY_TXD		BIT(0)
163 #define MT_CT_INFO_COPY_HOST_TXD_ALL	BIT(1)
164 #define MT_CT_INFO_MGMT_FRAME		BIT(2)
165 #define MT_CT_INFO_NONE_CIPHER_FRAME	BIT(3)
166 #define MT_CT_INFO_HSR2_TX		BIT(4)
167 
168 #define MT_TXD0_P_IDX			BIT(31)
169 #define MT_TXD0_Q_IDX			GENMASK(30, 26)
170 #define MT_TXD0_UDP_TCP_SUM		BIT(24)
171 #define MT_TXD0_IP_SUM			BIT(23)
172 #define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)
173 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
174 
175 #define MT_TXD1_OWN_MAC			GENMASK(31, 26)
176 #define MT_TXD1_PKT_FMT			GENMASK(25, 24)
177 #define MT_TXD1_TID			GENMASK(23, 21)
178 #define MT_TXD1_AMSDU			BIT(20)
179 #define MT_TXD1_UNXV			BIT(19)
180 #define MT_TXD1_HDR_PAD			GENMASK(18, 17)
181 #define MT_TXD1_TXD_LEN			BIT(16)
182 #define MT_TXD1_LONG_FORMAT		BIT(15)
183 #define MT_TXD1_HDR_FORMAT		GENMASK(14, 13)
184 #define MT_TXD1_HDR_INFO		GENMASK(12, 8)
185 #define MT_TXD1_WLAN_IDX		GENMASK(7, 0)
186 
187 #define MT_TXD2_FIX_RATE		BIT(31)
188 #define MT_TXD2_TIMING_MEASURE		BIT(30)
189 #define MT_TXD2_BA_DISABLE		BIT(29)
190 #define MT_TXD2_POWER_OFFSET		GENMASK(28, 24)
191 #define MT_TXD2_MAX_TX_TIME		GENMASK(23, 16)
192 #define MT_TXD2_FRAG			GENMASK(15, 14)
193 #define MT_TXD2_HTC_VLD			BIT(13)
194 #define MT_TXD2_DURATION		BIT(12)
195 #define MT_TXD2_BIP			BIT(11)
196 #define MT_TXD2_MULTICAST		BIT(10)
197 #define MT_TXD2_RTS			BIT(9)
198 #define MT_TXD2_SOUNDING		BIT(8)
199 #define MT_TXD2_NDPA			BIT(7)
200 #define MT_TXD2_NDP			BIT(6)
201 #define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)
202 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
203 
204 #define MT_TXD3_SN_VALID		BIT(31)
205 #define MT_TXD3_PN_VALID		BIT(30)
206 #define MT_TXD3_SEQ			GENMASK(27, 16)
207 #define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)
208 #define MT_TXD3_TX_COUNT		GENMASK(10, 6)
209 #define MT_TXD3_PROTECT_FRAME		BIT(1)
210 #define MT_TXD3_NO_ACK			BIT(0)
211 
212 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
213 
214 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
215 #define MT_TXD5_SW_POWER_MGMT		BIT(13)
216 #define MT_TXD5_DA_SELECT		BIT(11)
217 #define MT_TXD5_TX_STATUS_HOST		BIT(10)
218 #define MT_TXD5_TX_STATUS_MCU		BIT(9)
219 #define MT_TXD5_TX_STATUS_FMT		BIT(8)
220 #define MT_TXD5_PID			GENMASK(7, 0)
221 
222 #define MT_TXD6_FIXED_RATE		BIT(31)
223 #define MT_TXD6_SGI			BIT(30)
224 #define MT_TXD6_LDPC			BIT(29)
225 #define MT_TXD6_TX_BF			BIT(28)
226 #define MT_TXD6_TX_RATE			GENMASK(27, 16)
227 #define MT_TXD6_ANT_ID			GENMASK(15, 4)
228 #define MT_TXD6_DYN_BW			BIT(3)
229 #define MT_TXD6_FIXED_BW		BIT(2)
230 #define MT_TXD6_BW			GENMASK(1, 0)
231 
232 /* MT7663 DW7 HW-AMSDU */
233 #define MT_TXD7_HW_AMSDU_CAP		BIT(30)
234 #define MT_TXD7_TYPE			GENMASK(21, 20)
235 #define MT_TXD7_SUB_TYPE		GENMASK(19, 16)
236 #define MT_TXD7_SPE_IDX			GENMASK(15, 11)
237 #define MT_TXD7_SPE_IDX_SLE		BIT(10)
238 
239 #define MT_TXD8_L_TYPE			GENMASK(5, 4)
240 #define MT_TXD8_L_SUB_TYPE		GENMASK(3, 0)
241 
242 #define MT_TX_RATE_STBC			BIT(11)
243 #define MT_TX_RATE_NSS			GENMASK(10, 9)
244 #define MT_TX_RATE_MODE			GENMASK(8, 6)
245 #define MT_TX_RATE_IDX			GENMASK(5, 0)
246 
247 #define MT_TX_FREE_MSDU_ID_CNT		GENMASK(6, 0)
248 
249 #define MT_TXS0_PID			GENMASK(31, 24)
250 #define MT_TXS0_BA_ERROR		BIT(22)
251 #define MT_TXS0_PS_FLAG			BIT(21)
252 #define MT_TXS0_TXOP_TIMEOUT		BIT(20)
253 #define MT_TXS0_BIP_ERROR		BIT(19)
254 
255 #define MT_TXS0_QUEUE_TIMEOUT		BIT(18)
256 #define MT_TXS0_RTS_TIMEOUT		BIT(17)
257 #define MT_TXS0_ACK_TIMEOUT		BIT(16)
258 #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
259 
260 #define MT_TXS0_TX_STATUS_HOST		BIT(15)
261 #define MT_TXS0_TX_STATUS_MCU		BIT(14)
262 #define MT_TXS0_TXS_FORMAT		BIT(13)
263 #define MT_TXS0_FIXED_RATE		BIT(12)
264 #define MT_TXS0_TX_RATE			GENMASK(11, 0)
265 
266 #define MT_TXS1_ANT_ID			GENMASK(31, 20)
267 #define MT_TXS1_RESP_RATE		GENMASK(19, 16)
268 #define MT_TXS1_BW			GENMASK(15, 14)
269 #define MT_TXS1_I_TXBF			BIT(13)
270 #define MT_TXS1_E_TXBF			BIT(12)
271 #define MT_TXS1_TID			GENMASK(11, 9)
272 #define MT_TXS1_AMPDU			BIT(8)
273 #define MT_TXS1_ACKED_MPDU		BIT(7)
274 #define MT_TXS1_TX_POWER_DBM		GENMASK(6, 0)
275 
276 #define MT_TXS2_WCID			GENMASK(31, 24)
277 #define MT_TXS2_RXV_SEQNO		GENMASK(23, 16)
278 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
279 
280 #define MT_TXS3_LAST_TX_RATE		GENMASK(31, 29)
281 #define MT_TXS3_TX_COUNT		GENMASK(28, 24)
282 #define MT_TXS3_F1_TSSI1		GENMASK(23, 12)
283 #define MT_TXS3_F1_TSSI0		GENMASK(11, 0)
284 #define MT_TXS3_F0_SEQNO		GENMASK(11, 0)
285 
286 #define MT_TXS4_F0_TIMESTAMP		GENMASK(31, 0)
287 #define MT_TXS4_F1_TSSI3		GENMASK(23, 12)
288 #define MT_TXS4_F1_TSSI2		GENMASK(11, 0)
289 
290 #define MT_TXS5_F0_FRONT_TIME		GENMASK(24, 0)
291 #define MT_TXS5_F1_NOISE_2		GENMASK(23, 16)
292 #define MT_TXS5_F1_NOISE_1		GENMASK(15, 8)
293 #define MT_TXS5_F1_NOISE_0		GENMASK(7, 0)
294 
295 #define MT_TXS6_F1_RCPI_3		GENMASK(31, 24)
296 #define MT_TXS6_F1_RCPI_2		GENMASK(23, 16)
297 #define MT_TXS6_F1_RCPI_1		GENMASK(15, 8)
298 #define MT_TXS6_F1_RCPI_0		GENMASK(7, 0)
299 
300 struct mt7615_dfs_pulse {
301 	u32 max_width;		/* us */
302 	int max_pwr;		/* dbm */
303 	int min_pwr;		/* dbm */
304 	u32 min_stgr_pri;	/* us */
305 	u32 max_stgr_pri;	/* us */
306 	u32 min_cr_pri;		/* us */
307 	u32 max_cr_pri;		/* us */
308 };
309 
310 struct mt7615_dfs_pattern {
311 	u8 enb;
312 	u8 stgr;
313 	u8 min_crpn;
314 	u8 max_crpn;
315 	u8 min_crpr;
316 	u8 min_pw;
317 	u8 max_pw;
318 	u32 min_pri;
319 	u32 max_pri;
320 	u8 min_crbn;
321 	u8 max_crbn;
322 	u8 min_stgpn;
323 	u8 max_stgpn;
324 	u8 min_stgpr;
325 };
326 
327 struct mt7615_dfs_radar_spec {
328 	struct mt7615_dfs_pulse pulse_th;
329 	struct mt7615_dfs_pattern radar_pattern[16];
330 };
331 
332 static inline u32 mt7615_mac_wtbl_addr(struct mt7615_dev *dev, int wcid)
333 {
334 	return MT_WTBL_BASE(dev) + wcid * MT_WTBL_ENTRY_SIZE;
335 }
336 
337 #endif
338